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fujitsu semiconductor confidential MB86R01 lsi product specifications october, 2010 the 1.5 edition
i MB86R01 lsi product specifications fujitsu semiconductor confidential preface objectives and intended reader thank you very much for your continued special support for fujitsu semiconductor products. MB86R01 is lsi product for the graphics applications. this manual describes functions and operations of MB86R01 for engineers who design products using MB86R01. read through this manual before use. trademarks arm is a registered trademark of arm limited in uk, usa and taiwan. arm is a trademark of arm limited in japan and korea. arm powered logo is a register ed trademark of arm limited in japan, uk, usa, and taiwan. arm powered logo is a trademark of arm limited in korea. arm926ej-s and etm9 are trademarks of arm limited. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. license please acquire license of medialb from smsc. hardware related manuals MB86R01 hardware related manuals are shown below. refer them as the situation demands. ? MB86R01 lsi product specification graphics display controller (gdc) ? MB86R01 lsi product specification sd memory controller (note) ? MB86R01 data sheet ? MB86R01 errata sheet note) this specification document is for sd card licensee.
ii MB86R01 lsi product specifications fujitsu semiconductor confidential the contents of this document are subject to change without notice. customers are advised to consult with sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu semiconductor does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu semiconductor assumes no liability for any damage s whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu semiconductor or any third party or does fujitsu semiconductor warrant non-infringement of any third-party's intellectual property right or other right by using such information. fujitsu semiconductor assumes no liability for any infringement of the intellectual property rights or other rights of third pa rties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, ai r traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu semicondu ctor will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. exportation/release of any produc ts described in this document ma y require necessary procedures in accordance with the regulations of th e foreign exchange and foreign trade control law of japan and/or us export control laws. the company names and brand names herein are the trad emarks or registered trad emarks of their respective owners. all rights reserved, copyright fujitsu semiconductor limited 2007-2010
iii MB86R01 lsi product specifications fujitsu semiconductor confidential revision history date ver. contents 2007/06/06 1.0 newly issued 2007/09/14 1.1 whole contents: modified name and abbreviation of module ? sd memory interface ? sd memory controller ? sd i/f ? sdmc ? hdmac ? dmac ? usb2.0 host fjreg ? usb2.0 host phycnt ? usb2.0 host ohci ? usb1.1 ohci host ? usb2.0 host ehci ? usb2.0 ehci host ? usb2.0 func/dmac ? usb2.0 function dmac ? dma module ? dmac 1.6.15. ddr2 related pin ? modified description of *5 and *6 1.6.22. etm related pin ? modified description in the table 3.2. register access ? added description of sdmc in the table 3.3. register map ? revised description of drcf register ? revised description of pwm0bcr register ? revised description of idedmactl ? added usb2.0 ohci host 4.4. arm926ej-s and etm setting ? revised etmcssingle to etm9cs single 5.4.10. ahb(b) bus clock gate control register (crhb) ? revised description of hbgate[15:0] bit 5.5.1. generation of reset ? revised description of factor 5.5.2. clock generation ? revised figure 5-3 ? revised description of frequency change ? revised figure 5-6 ? revised description of stop mode 7.3.2. extension irq interrupt vector of irc0/irc1 ? revised exception factor name of the table 7.4.1. register list ? revised description column of table 7-5 7.5.2. initialization ? revised description of step 7 7.5.5. resume from stop and standby modes ? revised description 8.5.1. sram/flash mode regi ster 0/2/4 (mcfmode0/2/4) ? revised description of "bit 6: rdy" 8.5.2. sram/flash timing re gister 0/2/4 (mcftim0/2/4) ? revised description of "bit 23 - 20: wadc" 8.5.3. sram/flash area re gister 0/2/4 (mcfarea0/2/4) ? added table to "bit 7-0: addr" 8.7. example of access waveform ? revised figure 8-2 ? revised figure 8-3
iv MB86R01 lsi product specifications fujitsu semiconductor confidential date ver. contents 2007/09/14 1.1 8.8.2. low-speed device interface function ? revised description 8.8.3. endian and byte lane to each access ? revised table 8-2 9.4.13. dram odt setting register (dros) ? revised bit 1's initial value 9.4.17. odt auto bias adjust register (droaba) ? revised description of iavset bit 9.4.18. odt bias select register (drobs) ? revised description of auto bit 9.5.2. dram initialization procedure ? revised flow 9.5.2.1. sdram initialization procedure ? revised flow 9.5.2.2. odt adjustment procedure ? revised flow 9.5.5. dram ctrl add register (drca) ? revised description of bit 3-0 11.7. example of dmac setting ? revised title 11.7.1. dma start in single channel ? revised flow 11.7.3. block/transfer count resetting ? deleted section 14.7.6. pwmx status register (pwmxcr) ? revised bit field no. of "(reserved)" ? revised description of bit field no. 2-1 15.8.4. adcx clock selection register (adcxcksel) ? revised description of cksel[2:0] bit 17.6.4. i2sxcntreg register ? revised description of fsph bit 17.6.11. i2sxstatus register ? revised description of eopi 17.7.2. transfer start, stop, and malfunction ? revised description of "transmission only mode" 19.7.5. arbitration ? revised figure 21. can interface (can) ? added 21.1., outline ? added 21.2., block diagram ? added 21.3., register 23. usb host controller ? revised description 23.4. block diagram ? added figure 23.5.4. capability parameter register (hccparams) ? revised description 23.5.6. usb status register (usbsts) ? revised description of hostsystem-error bit 23.5.22. command/status re gister (hccommandstatus) ? revised description of blf bit ? revised description of clf bit
v MB86R01 lsi product specifications fujitsu semiconductor confidential date ver. contents 2007/09/14 1.1 23.5.23. interrupt status register (hcinterruptstatus) ? revised description of ue bit 23.5.31. bulk current ed register (hcbulkcurrented) ? revised description of bced bit 23.5.38. root hub descriptor a register (hcrhdescriptora) ? revised description of bit field no. 9 and 8 23.5.39. root hub descriptor b register (hcrhdescriptorb) ? revised description of ppcm bit ? revised description of dr bit 23.5.41. root hub port status/contr ol register 1 (hcrhportstatus[1]) ? added description of bit field no. 3-0 23.5.43. phy mode setti ng 1 register (phymodesetting1) ? added description of bit field no. 24 and 25 24. usb function controller ? added 24.1., outline ? added 24.2., feature ? added 24.4., block diagram 24.4. register ? revised the table 24.4.4. usb function device status register (ufdvs) ? revised bit 8's initial value 24.4.13. usb function endpoint 0 rx size register (ufeprs0) ? added bit description 24.4.14. usb function endpoint 1 rx size register (ufeprs1) ? added bit description 24.4.15. usb function endpoint 2 rx size register (ufeprs2) ? added bit description 24.4.16. usb function endpoint 3 rx size register (ufeprs3) ? added bit description 24.4.17. ufcuscnt register ? added this section 24.4.18. ufcalb register ? added this section 24.4.19. ufeplpbk register ? added this section 24.4.20. ufintfaltnum register ? added this section 24.4.21. usb function endpoint 0 control register (ufepc0) ? revised description of init0o bit ? revised description of init0i bit 24.4.23. usb function endpoint 1 control register (ufepc1) ? revised description of inififo1 bit 24.4.25. usb function endpoint 2 control register (ufepc2) ? revised description of inififo2 bit 24.4.27. usb function endpoint 3 control register (ufepc3) ? revised description of inififo3 bit 24.4.37. usb function endpoint 1 dma control/status register (ufepdc1) ? revised bit 8 to "reserved" ? revised description of epnf1 bit ? revised description of epne1 bit ? revised description of epdf1 bit 24.4.38. usb function endpoint 2 dma control/status register (ufepdc2) ? revised bit 8 to "reserved" ? revised description of epne2 bit ? revised description of epdf2 bit
vi MB86R01 lsi product specifications fujitsu semiconductor confidential date ver. contents 2007/09/14 1.1 24.4.41. usb function endpoint 1 dma size register (ufepds1) ? revised description of epds1 bit 24.4.42. usb function endpoint 2 dma size register (ufepds2) ? revised description of epds2 bit 24.5. operation ? added this section 25.6.36. dma control register (idedmactl) ? revised bit 7-1 to "reserved" 25.6.37. dma transfer control register (idedmatc) ? revised abbreviation of register (idedmactl ? idedmatc) ? revised description of type bit 26.5.1. register list ? revised table 26-1 26.5.4. interrupt status register (cist) ? revised description of int31/28/27/26/24/5 bit 26.5.12. multiplex mode setting register (cmux_md) ? revised description of mpx_mode_2 26.5.16. byte swap switchover register (cbsc) ? revised field name of bit 20-22 26.5.18. softreset register 0 for macro (cmsr0) ? revised field name of bit 16 ? revised description of srst0_3 bit 26.5.19. softreset register 1 for macro (cmsr1) ? revised field name of bit 23-19 and 4 2007/11/12 1.2 1.3 function list ? revised contents of the list 1.5. pin assignment ? revised figures in 1-8/1-9 pages ? added "top view" statement 1.6.1. pin multiplex ? revised description of note ? added mode setting description to pin multiplex group #1 ~ #5 ? revised table of pin multiplex group #2 and #4 1.6.6. usb 2.0 host/function related pin ? revised description of usb_ext12k pin 1.6.7. external interr upt controller related pin ? revised title 1.6.14. a/d converter related pin revised pin name: ad_avd0 ad_avd, ad_avs1 ad_avs 1.6.26. unused pin ? added this section 1.6.27. unused pin with pin mu ltiplex function in the duplex case ? added this section 5.5.2. clock generation ? revised figure 5-3 and table 5-4 6.4. supply clock ? added this section 8.4. supply clock ? added this section 8.6.1. sram/flash mode register 0/2/4 ? revised description of rdy, page, and wdth bit 8.6.2. sram/flash timing register 0/2/4 ? revised description of wwec, wadc, wacc, ridlc, radc, and racc bit
vii MB86R01 lsi product specifications fujitsu semiconductor confidential date ver. contents 2007/11/12 1.2 8.6.3. sram/fla sh area register 0/2/4 ? revised descript ion of addr bit 8.8. example of access waveform ? revised figure of word read access to 16 bit width sram/nor flash ? revised figure of word write access to 16 bit width sram/nor flash ? revised figure 8-2 and 8-3 of read/write to low speed device ? added figure 8-4 and 8-5 of read/write to low speed device ? revised figure of page read of 16 bit nor flash 8.9.2. low-speed device interface function ? revised description 9.4. supply clock ? added this section 9.5.8. dram ctrl set time2 register ? revised description of trfc bit 10.4. supply clock ? added this section 11.5. supply clock ? added this section 12.3. supply clock ? added this section 13.4. supply clock ? added this section 17.6.10. i2sxintcnt register ? revised description of rxfdm bit ? revised description of rxfim bit 17.6.11. i2sxstatus register ? revised description of rxovr bit 19.6.8. expansion cs register ? deleted description of bit 7 and 6 ? revised description of note 20.4. supply clock ? added this section 21.3. supply clock ? added this section 22. medialb interface ? revised description 22.3. supply clock ? added this section 23.3. feature ? revised function description of companion controller 23.5. supply clock ? added this section 24.4. supply clock ? added this section 24.5.17. ufcuscnt register ? revised description of bit 2-1 24.6.19. pull-up resistor ? revised description 25.6.17. ide command register ? revised description of dma interface enable bit 25.6.26. udma command resister ? revised description and bit name of bit 3 ? revised description of udma enable bit
viii MB86R01 lsi product specifications fujitsu semiconductor confidential date ver. contents 2007/11/12 1.2 25.6.28. rxfifo rest count compare value ? revised description 25.6.36. dma control register ? revised description of dma start bit 26.5.2. chip id register (ccid) ? revised description of bit year[15:0] bit 27.4. supply clock ? added this section 2008/02/07 1.3 1.5. pin assignment ? revised figure and table 1.6.4. ide66 related pin ? revised type ? revised status pin after reset 1.6.5. sd memory controller related pin ? unified sd_dat[0] and sd_dat[3:1] 1.6.6. usb 2.0 host/function related pin ? revised usb_avdb to usb_avsb 1.6.9. can related pin ? revised type 1.6.10. i2s related pin ? revised type ? revised status pin after reset 1.6.12. spi related pin ? revised type 1.6.13. pwm related pin ? revised type ? added comment 1.6.15. ddr2 related pin ? revised i/o of ocd and odt to i ? revised resistance value of *2 1.6.17. video capture related pin ? revised type ? added comment 1.6.20. ice related pin ? revised status pin after reset of xsrst 1.6.22. etm related pin ? revised pin name in description column of traceclk 1.6.24. medialb related pin ? revised pin name ? revised type 1.6.26. unused pin ? revised process ? deleted bigend ? revised pin name of b17, b16, c17, c16, and d16 1.6.27. unused pin with pin mu ltiplex function in the duplex case ? revised process 9.5.10. dram ctrl fifo register (drcf) ? revised bit name ? revised initial value of bit 15 ? added description of bit 15 to the list
ix MB86R01 lsi product specifications fujitsu semiconductor confidential date ver. contents 2008/02/07 1.3 9.5.17. odt auto bias adjust register (droaba) ? deleted and merged odtaut o (bit 1) to odtbias ? revised ndrv/pdrv to odt of the i/o cell ? revised remark description ? revised description of bit 7 9.5.18. odt bias select register (drobs) ? revised description of bit 0 11.8.1. dma start in single channel ? revised title of the figure ? revised figure ? added description of note ? added example of demand transfer by software request (with dmac ch0) 11.8.2. dma start in all channels (in demand transfer mode) ? revised title ? revised description 12.4. specification ? revised description 13.5.3. data direction register 0-2 (gpddr2-0) ? revised initial value of bit 7 ~ 0 18.6.9. line status register (urtxlsr) ? revised description of bit 1 18.7.2. example of transfer procedure ? revised description 23.6.40. root hub status register (hcrhstatus) ? revised description of bit 1 26.5.2. chip id register (ccid) ? revised description of bit 7-0 26.5.4. interrupt status register (cist) ? revised name of bit 25 26.5.11. axi polarity setting register (caxi_ps) ? revised initial value of bit 18, 13, 12, 9, and 4 ? revised description of bit 18-16 26.5.12. multiplex mode setting register (cmux_md) ? revised initial value of bit 5, 4, and 2 ~ 0 26.5.17. ddr2 controller reset control register (cdcrc) ? revised name of bit 1 from irreset to iusrrst ? exchanged description in function column of bit 1 and 0 2008/06/12 1.4 3.3 register map ? revised description of external bus interface 8.2. spec limitation ? added this section 8.7.1. sram/flash mode register 0-7 (mcfarea0-7) ? revised title ? revised description in re gister address column 8.7.2. sram/flash timing register 0-7 (mcftim0-7) ? revised title ? revised description in re gister address column 8.7.3. sram/flash area register 0-7 (mcfarea0-7) ? revised title ? revised description in register column ? revised description in bit 22-16 9.6.2.3. odt setting procedure ? revised description ? revised figure 9-6
x MB86R01 lsi product specifications fujitsu semiconductor confidential date ver. contents 2008/06/12 1.4 11.6.3. dma configuration a register (dmacax) ? revised from 16 to 16 (fh) in bit 19-16 ? revised 65536 to 65536 (ffffh) in bit 15-0 17.2. feature ? revised description 17.7.3.1. 1 sub frame construction ? revised figure 17-2 17.7.3.2. 2 sub frame construction ? revised figure 17-3 18.3. block diagram ? revised figure 18-1 22.4. register ? revised description 23.6.3. structural parame ter register (hcsparams) ? revised initial value of bit 11-8 and 3-0 ? revised description of bit 11-8 and 3-0 23.6.19. utmi control status register (insnreg05) ? revised initial value of bit 12 23.6.23. interrupt status register (hcinterruptstatus) ? added note description ? deleted description of bit 6 23.6.28. control head ed register (hccontrolheaded) ? revised bit field number 23.6.38. root hub descriptor a register (hcrhdescriptora) ? revised initial value of bit 7-0 ? revised description of bit 7-0 23.6.39. root hub descriptor b register (hcrhdescriptorb) ? revised initial value of bit 31-16 ? revised description of bit 31-16 23.6.43. phy mode setti ng 1 register (phymodesetting1) ? revised initial value of bit 25 and 24 26.5.19. software reset register 1 for macro (cmsr1) ? revised description of bit 26 2010/10/15 1.5 1.6.1. pin multiplex ? revised description of note 4.4. arm926ej- s and etm setting ? revised url of arm926e j-s-related material 5.4.2. pll control register (crpr) ? revised description of bit 4-0 5.4.3. watchdog timer control register (crwr) ? revised description of bit 7 ? revised description of bit 4 7.6.4. interrupt level mask register (ir0ilm/ir1ilm) ? revised description of bit 3-0 7.7.1. outline ? revised figure 7-2 8.7.2. sram/flash timi ng register 0-7 (mcftim0-7) ? revised description of bit 19-16 8.8. connection example ? added figure 8-6 8.9. example of access waveform ? revised figure 8-8 ? revised figure 8-10 ? revised figure 8-12
xi MB86R01 lsi product specifications fujitsu semiconductor confidential date ver. contents 2010/10/15 1.5 9.5.1. register list ? revised table 9-2 9.5.7. dram ctrl set time1 register (drcst1) ? revised description of bit 10-8 ? revised description of bit 3-0 9.5.15. io buffer setting ocd (dribsocd) (*) ? deleted section *) it is a section number and a title of version 1.4 9.5.16. io buffer setting ocd2 (dribsocd2) (*) ? deleted section *) it is a section number and a title of version 1.4 9.5.19. io monitor register 1 (drimr1) ~ 9.5.22. io monitor register 4 (drimr4) (*) ? deleted section *) it is a section number and a title of version 1.4 9.6.1. dram initialization sequence ? revised figure 9-2 9.6.2.1. sdram initialization procedure ? revised figure 9-4 9.6.2.2. ocd adjustment procedure (*) ? deleted section *) it is a section number and a title of version 1.4 9.6.2.2. odt setting procedure ? revised figure 9-6 13.5.1. register list ? revised table 13-1 13.5.3. data direction register 0-2 (gpddr2-0) ? revised description of bit 7-0 (ddr0_7-0) ? revised description of bit 7-0 (ddr1_15-8) ? revised description of bit 7-0 (ddr2_23-16) 13.6.1. direction control ? revised description 17.6.2. i2sxrxfdat register ? revised description 17.6.3. i2sxtxfdat register ? revised description 17.6.11. i2sxstatus register ? revised description of bit 31 ? revised description of bit 30 ? revised bit 13-8 to bit 15-8 (txnum[5:0] ? txnum[7:0]) ? revised description of bit 15-8 ? revised bit 5-0 to bit 7-0 (rxnum[5:0] ? rxnum[7:0] ) ? revised description of bit 7-0 17.7.1. outline ? revised description 17.7.4. fifo structure and description ? revised figure 17-6 ? revised description of "simultaneous tran smission and reception mode (txdis = 0 and rxdis = 0)" ? revised figure 17-7 ? revised description of "transmission only mode (txdis = 0 and rxdis = 1)" ? revised figure 17-8 ? revised description of " reception only mode (txdis = 1 and rxdis = 0)" 18.6.4. interrupt enable register (urtxier) ? revised description of bit 1
xii MB86R01 lsi product specifications fujitsu semiconductor confidential date ver. contents 2010/10/15 1.5 18.6.7. line c ontrol register (urtxlcr) ? revised description of bit 7 18.6.8. modem control register (urtxmcr) ? revised description of bit 4 ? revised bit 3, bit 2, and bit 0 to "reserved bit" 18.6.10. modem status register (urtxmsr) ? revised bit 7-5 and bit 3-1 to "reserved bit" 20.6.2. spi control register (spicr) ? revised figure 20-4 ? revised figure 20-5 23.6.1. register list ? revised description ? revised table 23-2 ? revised table 23-3 ? revised table 23-4 23.6.2.1. hccapbase (capabil ity register) ~ 23.6.2.18. insn reg05 (utmi control status register) ? revised description 23.6.3.1. hcrevision (revision register) ? revised description of bit 7-0 23.6.3.2. hccontrol (control register) ~ 23. 6.3.3. hccommandstatus (c ommand/status register) ? revised description 23.6.3.4. hcinterruptstatus (interrupt status register) ? revised description in r/w column ? revised description of bit 4 23.6.3.5. hcinterruptenable (interrupt enab le register) ~ 23.6.3.6. hcinterruptdisable (interrupt disable register) ? revised description in r/w column 23.6.3.8. hcperiodcurrented (periodic curren t ed register) ~ 23.6.3.19. hcrhdescriptora (root hub descriptor a register) ? revised description in r/w column 23.6.3.21. hcrhstatus (root hub status register) ~ 23.6.3.22. hcrhportstatus[1] (root hub port status/control register 1) ? revised description in r/w column 23.6.4.1. linkmodesetting (link mode setting register) ? revised description in initial value column ? revised description of bit 31-0 23.6.4.2. phymodesetting1 (p hy mode setting 1 register) ? revised description in initial value column ? revised description of bit 27-24 ? revised description of bit 0 26.5.2. chip id register (ccid) ? revised description in initial value column of bit 7-0 ? revised description of bit 7-0 26.5.11. axi polarity setting register (caxi_ps) ? revised description ? added note ? revised description of bit 18-16 ? revised description of bit 14-12 ? revised description of bit 10-8 ? revised description of bit 6-4 ? revised description of bit 2-0 26.5.12. multiplex mode setting register (cmux_md) ? added note
xiii MB86R01 lsi product specifications fujitsu semiconductor confidential contents 1. outline .............................................................................................................. 1-1 1.1. feature........................................................................................................................ .......................... 1-1 1.2. block diagram .................................................................................................................. .................... 1-3 1.3. function list.................................................................................................................. ........................ 1-5 1.4. package dimension.............................................................................................................. ................. 1-7 1.5. pin assignment ................................................................................................................. .................... 1-8 1.6. pin function ................................................................................................................... ..................... 1-11 1.6.1. pin multip lex.................................................................................................................. ............ 1-11 1.6.2. pin function ................................................................................................................... ............. 1-17 1.6.3. external bus inte rface related pin............................................................................................. .. 1-18 1.6.4. ide66 related pin .............................................................................................................. ......... 1-18 1.6.5. sd memory controlle r related pin .............................................................................................. 1 -19 1.6.6. usb 2.0 host/functio n related pin ............................................................................................ 1- 19 1.6.7. external interrupt cont roller related pin ..................................................................................... 1 -19 1.6.8. uart relate d pin ............................................................................................................... ........ 1-20 1.6.9. can related pin ................................................................................................................ ......... 1-20 1.6.10. i2s related pin ................................................................................................................ ............ 1-21 1.6.11. i 2 c related pin .................................................................................................................. .......... 1-21 1.6.12. spi related pin ................................................................................................................ ............ 1-21 1.6.13. pwm relate d pin ................................................................................................................ ........ 1-22 1.6.14. a/d converter related pin...................................................................................................... ..... 1-22 1.6.15. ddr2 related pin ............................................................................................................... ........ 1-23 1.6.16. display related pin ............................................................................................................ ..... 1-24 1.6.17. video capture related pin...................................................................................................... ...... 1-25 1.6.18. system related pin ............................................................................................................. ......... 1-25 1.6.19. jtag rela ted pin ............................................................................................................... ......... 1-26 1.6.20. ice relate d pin ................................................................................................................ ........... 1-26 1.6.21. multiplex setting related pin .................................................................................................. .... 1-26 1.6.22. etm relate d pin ................................................................................................................ ......... 1-27 1.6.23. power supply related pin ....................................................................................................... ..... 1-27 1.6.24. medialb rela ted pin............................................................................................................ ....... 1-27 1.6.25. gpio rela ted pin ............................................................................................................... ......... 1-27 1.6.26. unused pin ..................................................................................................................... ............ 1-28 1.6.27. unused pin in the duplex case with pin multiple x functio n ....................................................... 1-36 2. system confi guration ...................................................................................... 2-1 3. memory map .................................................................................................... 3-1 3.1. memory map of lsi.............................................................................................................. ............... 3-1 3.2. register access ................................................................................................................ ..................... 3-3 3.3. register map ................................................................................................................... ..................... 3-4 4. cpu (arm926ej-s co re part) ......................................................................... 4-1 4.1. outline........................................................................................................................ .......................... 4-1 4.2. feature........................................................................................................................ .......................... 4-1
xiv MB86R01 lsi product specifications fujitsu semiconductor confidential 4.3. block diagram .................................................................................................................. .................... 4-1 4.4. arm926ej-s an d etm se tting ..................................................................................................... ...... 4-2 5. clock reset genera tor (crg) .......................................................................... 5-1 5.1. outline........................................................................................................................ .......................... 5-1 5.2. feature........................................................................................................................ .......................... 5-1 5.3. block diagram .................................................................................................................. .................... 5-2 5.4. register ....................................................................................................................... ......................... 5-3 5.4.1. register list .................................................................................................................. ................ 5-3 5.4.2. pll control regi ster (crpr).................................................................................................... .... 5-5 5.4.3. watchdog timer control register (crwr) .................................................................................... 5-7 5.4.4. reset/standby control register (crsr)........................................................................................ 5- 9 5.4.5. clock divider control re gister a (crda)................................................................................... 5-11 5.4.6. clock divider control re gister b ( crdb)................................................................................... 5-13 5.4.7. ahb (a) bus clock gate cont rol register (crha) ..................................................................... 5-14 5.4.8. apb (a) bus clock gate cont rol register (crpa)....................................................................... 5-15 5.4.9. apb (b) bus clock gate cont rol register (crpb) ....................................................................... 5-16 5.4.10. ahb (b) bus clock gate cont rol register (crhb)...................................................................... 5-17 5.4.11. arm core clock gate cont rol register (cram) ......................................................................... 5-18 5.5. operation...................................................................................................................... ...................... 5-19 5.5.1. generation of reset ............................................................................................................ ......... 5-19 5.5.2. clock generation ............................................................................................................... ......... 5-22 6. remap boot contro ller ( rbc) ......................................................................... 6-1 6.1. outline........................................................................................................................ .......................... 6-1 6.2. feature........................................................................................................................ .......................... 6-1 6.3. block diagram .................................................................................................................. .................... 6-1 6.4. supply clock................................................................................................................... ...................... 6-2 6.5. register ....................................................................................................................... ......................... 6-2 6.5.1. register list .................................................................................................................. ................ 6-2 6.5.2. remap control regist er (rbremap)........................................................................................... 6-4 6.5.3. vinithi control register a (rbviha) ....................................................................................... 6-5 6.5.4. initram control regist er a (rbitra)...................................................................................... 6-6 6.6. operation...................................................................................................................... ........................ 6-7 6.6.1. rbc rese t ...................................................................................................................... ............... 6-7 6.6.2. remap control .................................................................................................................. ............ 6-7 6.6.3. vinithi control ................................................................................................................ .......... 6-7 6.6.4. initram c ontrol ................................................................................................................ ........ 6-8 7. interrupt contro ller (irc) ................................................................................. 7-1 7.1. outline........................................................................................................................ .......................... 7-1 7.2. feature........................................................................................................................ .......................... 7-1 7.3. block diagram .................................................................................................................. .................... 7-2 7.4. supply clock................................................................................................................... ...................... 7-3 7.5. interrupt map.................................................................................................................. ...................... 7-3 7.5.1. exception vector to arm926ej-s core ....................................................................................... 7-3 7.5.2. extension irq interrupt vector of irc0/irc1i rc0/irc1 .......................................................... 7-4 7.6. register ....................................................................................................................... ......................... 7-6 7.6.1. register list .................................................................................................................. ................ 7-6
xv MB86R01 lsi product specifications fujitsu semiconductor confidential 7.6.2. irq flag register (i r0irqf/ ir1i rqf) ..................................................................................... 7-10 7.6.3. irq mask register (ir0irqm/ir1irqm) ................................................................................. 7-11 7.6.4. interrupt level mask regist er (ir0ilm/ir 1ilm)........................................................................ 7-12 7.6.5. icr monitoring register (ir0icrmn/ir1i crmn)................................................................... 7-13 7.6.6. delay interrupt control re gister 0 (ir0 dicr0) .......................................................................... 7-14 7.6.7. delay interrupt control re gister 1 (ir0 dicr1) .......................................................................... 7-15 7.6.8. table base register (ir0tbr/ir 1tbr)...................................................................................... 7-16 7.6.9. interrupt vector regist er (ir0vct/i r1vct) ............................................................................. 7-17 7.6.10. interrupt control register (ir0icr31/ ir1icr31 ? ir0icr00 /ir1icr00)................................. 7-18 7.7. operation...................................................................................................................... ...................... 7-19 7.7.1. outline........................................................................................................................ ................ 7-19 7.7.2. initializa tion ................................................................................................................. .............. 7-19 7.7.3. multiple interr upt process ..................................................................................................... ..... 7-20 7.7.4. example of irq interrupt handler.............................................................................................. 7 -20 7.7.5. resume from stop and standby m odes ...................................................................................... 7-22 7.7.6. notice for us ing irc ........................................................................................................... ....... 7-22 8. external bus in terface ..................................................................................... 8-1 8.1. outline........................................................................................................................ .......................... 8-1 8.2. spec limita tion ................................................................................................................ ..................... 8-1 8.3. feature........................................................................................................................ .......................... 8-3 8.4. block diagram .................................................................................................................. .................... 8-3 8.5. related pin .................................................................................................................... ....................... 8-4 8.6. supply clock................................................................................................................... ...................... 8-4 8.7. register ....................................................................................................................... ......................... 8-5 8.7.1. sram/flash mode register 0-7 (mcfmode0-7)....................................................................... 8-5 8.7.2. sram/flash timing register 0-7 (mcfti m0-7).......................................................................... 8-7 8.7.3. sram/flash area register 0-7 (mcfar ea0-7) .......................................................................... 8-9 8.7.4. memory controller error register (m cerr) .............................................................................. 8-11 8.8. connection example............................................................................................................. .............. 8-12 8.9. example of ac cess waveform..................................................................................................... ........ 8-14 8.10. operation...................................................................................................................... ...................... 8-18 8.10.1. external bu s inte rface......................................................................................................... ........ 8-18 8.10.2. low-speed device inte rface function ......................................................................................... 8-1 8 8.10.3. endian and byte la ne to each access........................................................................................... 8 -19 9. ddr2 contro ller ............................................................................................... 9-1 9.1. outline........................................................................................................................ .......................... 9-1 9.2. feature........................................................................................................................ .......................... 9-1 9.3. block diagram .................................................................................................................. .................... 9-2 9.4. supply clock................................................................................................................... ...................... 9-3 9.5. register ....................................................................................................................... ......................... 9-3 9.5.1. register list .................................................................................................................. ................ 9-3 9.5.2. dram initialization contro l register (dric) .............................................................................. 9-5 9.5.3. dram initialization command re gister [1] (d ric1) .................................................................. 9-7 9.5.4. dram initialization command re gister [2] (d ric2) .................................................................. 9-7 9.5.5. dram ctrl add register (drca).......................................................................................... 9-8 9.5.6. dram control mode re gister (drcm) ....................................................................................... 9-9 9.5.7. dram ctrl set time1 re gister (drcs t1) ....................................................................... 9-10 9.5.8. dram ctrl set time2 re gister (drcst2)......................................................................... 9-12
xvi MB86R01 lsi product specifications fujitsu semiconductor confidential 9.5.9. dram ctrl refresh register (drcr) ............................................................................... 9-14 9.5.10. dram ctrl fifo re gister (d rcf) ........................................................................................ 9-15 9.5.11. axi setting regist er (drasr) ................................................................................................... 9-16 9.5.12. dram if macro setting dl l register (drimsd).......................................................... 9-17 9.5.13. dram odt setting re gister (d ros).................................................................................. 9-18 9.5.14. io buffer setting odt1 (dribsod t1)..................................................................................... 9-19 9.5.15. odt auto bias adjust register (droaba)................................................................................. 9-20 9.5.16. odt bias select regi ster (drobs) ............................................................................................ 9-2 1 9.5.17. ocd impedance setting rrgi ster1 (droisr1).......................................................................... 9-22 9.5.18. ocd impedance setting regi ster2 (droisr2) .......................................................................... 9-22 9.6. operation...................................................................................................................... ...................... 9-23 9.6.1. dram initializa tion sequence ................................................................................................... 9-23 9.6.2. dram initializati on procedure.................................................................................................. 9-24 9.6.2.1. sdram initialization procedur e........................................................................................ 9-25 9.6.2.2. odt setting pro cedure ....................................................................................................... 9-2 7 10. built-in s ram................................................................................................. 10-1 10.1. outline........................................................................................................................ ........................ 10-1 10.2. feature........................................................................................................................ ........................ 10-1 10.3. block diagram .................................................................................................................. .................. 10-1 10.4. supply clock................................................................................................................... .................... 10-1 11. dma controller (dmac) ................................................................................. 11-1 11.1. outline........................................................................................................................ ........................ 11-1 11.2. feature........................................................................................................................ ........................ 11-1 11.3. block diagram .................................................................................................................. .................. 11-2 11.4. related pin .................................................................................................................... ..................... 11-3 11.5. supply clock................................................................................................................... .................... 11-3 11.6. register ....................................................................................................................... ....................... 11-4 11.6.1. register list .................................................................................................................. .............. 11-4 11.6.2. dma configuration re gister (d macr) ..................................................................................... 11-6 11.6.3. dma configuration a re gister (dma cax) ............................................................................... 11-8 11.6.4. dma configuration b regi ster (dmacbx) ............................................................................. 11-11 11.6.5. dmac source address regi ster (dmacsax).......................................................................... 11-14 11.6.6. dmac destination address re gister (dmacdax) .................................................................. 11-15 11.7. operation...................................................................................................................... .................... 11-16 11.7.1. transfer mode .................................................................................................................. ........ 11-16 11.7.1.1. block transfer ................................................................................................................. .. 11-16 11.7.1.2. burst transfer................................................................................................................. ... 11-20 11.7.1.3. demand transfer ............................................................................................................... 1 1-24 11.7.2. beat transfer .................................................................................................................. ........... 11-28 11.7.2.1. normal and single transfer............................................................................................... 11-28 11.7.2.2. increment and lap transfer................................................................................................ 11-29 11.7.3. channel prior ity control ....................................................................................................... .... 11-30 11.7.3.1. fixed pr ior ity................................................................................................................. ... 11-30 11.7.3.2. rotate pr iority ................................................................................................................ .. 11-31 11.7.4. retry, split, and error........................................................................................................ ........ 11-32 11.7.4.1. retry an d sp lit ................................................................................................................ .. 11-32 11.7.4.2. error .......................................................................................................................... ....... 11-33 11.8. example of dm ac setting........................................................................................................ ....... 11-34
xvii MB86R01 lsi product specifications fujitsu semiconductor confidential 11.8.1. dma start in si ngle channel .................................................................................................... 11-34 11.8.2. dma start in all channels (in demand transfer mode).............................................................. 11-35 12. timer (tim er) ................................................................................................ 12-1 12.1. outline........................................................................................................................ ........................ 12-1 12.2. feature........................................................................................................................ ........................ 12-1 12.3. supply clock................................................................................................................... .................... 12-1 12.4. specifica tion.................................................................................................................. ..................... 12-1 13. general-purpose input/out put port (g pio).................................................. 13-1 13.1. outline........................................................................................................................ ........................ 13-1 13.2. feature........................................................................................................................ ........................ 13-1 13.3. block diagram .................................................................................................................. .................. 13-1 13.4. supply clock................................................................................................................... .................... 13-1 13.5. register ....................................................................................................................... ....................... 13-2 13.5.1. register list .................................................................................................................. .............. 13-2 13.5.2. port data register 0-2 (gpdr0-2)............................................................................................... 13-4 13.5.3. data direction register 0-2 (gpddr 2-0) ................................................................................... 13-6 13.6. operation...................................................................................................................... ...................... 13-8 13.6.1. direction control .............................................................................................................. .......... 13-8 13.6.2. data transfer .................................................................................................................. ............. 13-8 14. pwm................................................................................................................ 14-1 14.1. outline........................................................................................................................ ........................ 14-1 14.2. feature........................................................................................................................ ........................ 14-1 14.3. block diagram .................................................................................................................. .................. 14-2 14.4. related pin .................................................................................................................... ..................... 14-2 14.5. supply clock................................................................................................................... .................... 14-2 14.6. interrupt...................................................................................................................... ........................ 14-2 14.7. register ....................................................................................................................... ....................... 14-3 14.7.1. register list .................................................................................................................. .............. 14-3 14.7.2. pwmx base clock regi ster (pwm xbcr)................................................................................... 14-5 14.7.3. pwmx pulse width regi ster (pwmxtpr) ................................................................................. 14-6 14.7.4. pwmx phase regist er (pwmxpr) ............................................................................................. 14-7 14.7.5. pwmx duty regist er (pwmxdr)............................................................................................... 14-8 14.7.6. pwmx status regist er (pwmxcr)............................................................................................. 14-9 14.7.7. pwmx start register (pwmxsr) ............................................................................................. 14-10 14.7.8. pwmx current count regi ster (pwmx ccr) ............................................................................ 14 -11 14.7.9. pwmx interrupt regist er (pwmxir) ....................................................................................... 14-12 14.8. example of se tting register.................................................................................................... ........... 14-13 15. a/d conver ter ................................................................................................. 15-1 15.1. outline........................................................................................................................ ........................ 15-1 15.2. feature........................................................................................................................ ........................ 15-1 15.3. block diagram .................................................................................................................. .................. 15-2 15.4. related pin .................................................................................................................... ..................... 15-2 15.5. supply clock................................................................................................................... .................... 15-2 15.6. output truth value list........................................................................................................ ................. 15-3
xviii MB86R01 lsi product specifications fujitsu semiconductor confidential 15.7. analog pin equiva lent circuit .................................................................................................. ........... 15-4 15.8. register ....................................................................................................................... ....................... 15-5 15.8.1. register list .................................................................................................................. .............. 15-5 15.8.2. adcx data register (adcxdata) ............................................................................................ 15-7 15.8.3. adcx power down control re gister (adc xxpd) ..................................................................... 15-7 15.8.4. adcx clock selection regi ster (adcxcksel) ......................................................................... 15-8 15.8.5. adcx status register (adcxstatus) ...................................................................................... 15-9 15.9. basic opera tion fl ow ........................................................................................................... ............. 15-10 16. graphics display co ntroller (g dc) ............................................................... 16-1 17. serial audio inte rface (i2s )............................................................................ 17-1 17.1. outline........................................................................................................................ ........................ 17-1 17.2. feature........................................................................................................................ ........................ 17-1 17.3. block diagram .................................................................................................................. .................. 17-2 17.4. related pin .................................................................................................................... ..................... 17-3 17.5. supply clock................................................................................................................... .................... 17-3 17.6. register ....................................................................................................................... ....................... 17-4 17.6.1. register list .................................................................................................................. .............. 17-4 17.6.2. i2sxrxfdat register............................................................................................................ .... 17-6 17.6.3. i2sxtxfdat register ............................................................................................................ .... 17-7 17.6.4. i2sxcntreg register ............................................................................................................ ... 17-8 17.6.5. i2sxmcr0reg register .......................................................................................................... 1 7-11 17.6.6. i2sxmcr1reg register .......................................................................................................... 1 7-12 17.6.7. i2sxmcr2reg register .......................................................................................................... 1 7-13 17.6.8. i2sxoprreg register............................................................................................................ .. 17-14 17.6.9. i2sxsrst register.............................................................................................................. ...... 17-15 17.6.10. i2sxintcnt register............................................................................................................ ... 17-16 17.6.11. i2sxstatus register ............................................................................................................ ... 17-19 17.6.12. i2sxdmaact register ............................................................................................................ 17-21 17.7. operation...................................................................................................................... .................... 17-22 17.7.1. outline........................................................................................................................ .............. 17-22 17.7.2. transfer start, stop , and malfunction ........................................................................................ 17 -23 17.7.3. frame cons tructio n............................................................................................................. ...... 17-28 17.7.3.1. 1 sub frame cons truction .................................................................................................. 17-28 17.7.3.2. 2 sub frame cons truction .................................................................................................. 17-29 17.7.3.3. bit ali gnment .................................................................................................................. .. 17-30 17.7.4. fifo structure and description................................................................................................. 17-32 18. uart interf ace ............................................................................................. 18-1 18.1. outline........................................................................................................................ ........................ 18-1 18.2. feature........................................................................................................................ ........................ 18-1 18.3. block diagram .................................................................................................................. .................. 18-1 18.4. related pin .................................................................................................................... ..................... 18-2 18.5. supply clock................................................................................................................... .................... 18-2 18.6. register ....................................................................................................................... ....................... 18-3 18.6.1. register list .................................................................................................................. .............. 18-3 18.6.2. reception fifo regist er (urtxr fr) ........................................................................................ 18-6 18.6.3. transmission fifo regi ster (urtxtfr) ................................................................................... 18-6
xix MB86R01 lsi product specifications fujitsu semiconductor confidential 18.6.4. interrupt enable register (urtxier).......................................................................................... 18 -7 18.6.5. interrupt id register (urtxiir) ................................................................................................ .18-8 18.6.6. fifo control register (urtxfcr) ............................................................................................. 18- 9 18.6.7. line control regist er (urtxlcr) ............................................................................................ 18-1 0 18.6.8. modem control regist er (urtxmcr) ...................................................................................... 18-11 18.6.9. line status regist er (urtxlsr)............................................................................................... 18 -12 18.6.10. modem status register (urtxmsr)......................................................................................... 18-13 18.6.11. divider latch register (urtxdll&urtxdlm) ..................................................................... 18-14 18.7. uart operation ................................................................................................................. .............. 18-16 18.7.1. example of in itial se tting ..................................................................................................... .... 18-16 18.7.2. example of transfer procedure ................................................................................................. 1 8-17 18.7.3. example of recep tion proce dure............................................................................................... 18 -18 18.7.4. basic transmissi on operation................................................................................................... .18-19 18.7.5. basic receptio n operation ...................................................................................................... ... 18-20 18.7.6. line status .................................................................................................................... ............ 18-21 18.7.7. character time-out interrupt ................................................................................................... .. 18-25 19. i 2 c bus inte rface ............................................................................................ 19-1 19.1. outline........................................................................................................................ ........................ 19-1 19.2. feature........................................................................................................................ ........................ 19-1 19.3. block diagram .................................................................................................................. .................. 19-2 19.4. related pin .................................................................................................................... ..................... 19-4 19.5. supply clock................................................................................................................... .................... 19-4 19.6. register ....................................................................................................................... ....................... 19-5 19.6.1. register list .................................................................................................................. .............. 19-5 19.6.2. bus status register (i2cxbsr) .................................................................................................. .19-7 19.6.3. bus control register (i2cxbcr)................................................................................................. 19-9 19.6.4. clock control regist er (i2cxccr) ........................................................................................... 19-1 2 19.6.5. address register (i2cxadr).................................................................................................... 1 9-15 19.6.6. data register (i2cxdar) ........................................................................................................ .19-16 19.6.7. two bus control regist ers (i2cxbc2 r).................................................................................... 19-17 19.6.8. expansion cs register (i2cxecsr)......................................................................................... 19-18 19.6.9. bus clock frequency regi ster (i2cxbcfr) .............................................................................. 19-20 19.7. operation...................................................................................................................... .................... 19-21 19.7.1. start c ondition ................................................................................................................ .......... 19-21 19.7.2. stop c ondition ................................................................................................................. ......... 19-22 19.7.3. addressing ..................................................................................................................... .......... 19-23 19.7.4. synchronous arbitr ation of scl............................................................................................... 19 -24 19.7.5. arbitration.................................................................................................................... ............ 19-25 19.7.6. acknowledge/negative acknowledge ...................................................................................... 19-26 19.7.7. bus error...................................................................................................................... ............. 19-27 19.7.8. initializa tion ................................................................................................................. ............ 19-28 19.7.9. one byte transfer from master to slave..................................................................................... 19-2 9 19.7.10. one byte transfer from slave to master..................................................................................... 19-3 0 19.7.11. recover from bus error ......................................................................................................... ... 19-31 19.7.12. interrupt process and wait request operation to master device................................................. 19-32 19.8. notice......................................................................................................................... ...................... 19-32 19.9. flow charts .................................................................................................................... .................. 19-34
xx MB86R01 lsi product specifications fujitsu semiconductor confidential 20. serial peripheral in terface (spi ) .................................................................. 20-1 20.1. outline........................................................................................................................ ........................ 20-1 20.2. feature........................................................................................................................ ........................ 20-1 20.3. block diagram .................................................................................................................. .................. 20-2 20.4. supply clock................................................................................................................... .................... 20-2 20.5. transition state ............................................................................................................... .................... 20-3 20.6. register ....................................................................................................................... ....................... 20-4 20.6.1. register list .................................................................................................................. .............. 20-4 20.6.2. spi control regi ster (spicr) ................................................................................................... ... 20-5 20.6.3. spi slave control re gister (spiscr)........................................................................................... 2 0-7 20.6.4. spi data regist er (spidr) ...................................................................................................... .. 20-10 20.6.5. spi status register (spisr).................................................................................................... ... 20-11 20.7. setup proced ure flow ........................................................................................................... ............ 20-12 21. can interface (can)...................................................................................... 21-1 21.1. outline........................................................................................................................ ........................ 21-1 21.2. block diagram .................................................................................................................. .................. 21-1 21.3. supply clock................................................................................................................... .................... 21-2 21.4. register ....................................................................................................................... ....................... 21-2 22. medialb inte rface.......................................................................................... 22-1 22.1. outline........................................................................................................................ ........................ 22-1 22.2. block diagram .................................................................................................................. .................. 22-1 22.3. supply clock................................................................................................................... .................... 22-2 22.4. register ....................................................................................................................... ....................... 22-2 23. usb host cont roller .................................................................................... 23-1 23.1. outline........................................................................................................................ ........................ 23-1 23.2. spec limita tion ................................................................................................................ ................... 23-1 23.3. feature........................................................................................................................ ........................ 23-2 23.4. block diagram .................................................................................................................. .................. 23-3 23.5. supply clock................................................................................................................... .................... 23-4 23.6. register ....................................................................................................................... ....................... 23-4 23.6.1. register list .................................................................................................................. .............. 23-4 23.6.2. ehci operationa l regist ers..................................................................................................... .. 23-6 23.6.2.1. hccapbase (capability register ).................................................................................. 23-6 23.6.2.2. hcsparams (structural pa rameter register) ................................................................. 23-7 23.6.2.3. hccparams (capability para meter regist er) ................................................................ 23-8 23.6.2.4. usbcmd (usb command register)................................................................................ 23-9 23.6.2.5. usbsts (usb status register)....................................................................................... 23-11 23.6.2.6. usbintr (usb interrupt en able regist er) .................................................................... 23-13 23.6.2.7. frindex (usb frame in dex register).......................................................................... 23-14 23.6.2.8. ctrldssegment (4g segment se lector regist er) .................................................... 23-14 23.6.2.9. periodiclistbase (periodic frame list base address register) ............................. 23-15 23.6.2.10. asynclistaddr (asynchronous li st address regi ster) ........................................... 23-15 23.6.2.11. configflag (configured flag regist er)..................................................................... 23-16 23.6.2.12. portsc_1 (port status/con trol register 1).................................................................... 23-17
xxi MB86R01 lsi product specifications fujitsu semiconductor confidential 23.6.2.13. insnreg00 (programmable microframe base value register)..................................... 23-20 23.6.2.14. insnreg01 (programmable packet buffer out/in threshold register) ..................... 23-20 23.6.2.15. insnreg02 (programmable packet buffer depth register).......................................... 23-22 23.6.2.16. insnreg03 (time-available offset register) ............................................................... 23-23 23.6.2.17. insnreg04 (debug register) ........................................................................................ 23-23 23.6.2.18. insnreg05 (utmi control st atus register)................................................................. 23-24 23.6.3. ohci operational registers .................................................................................................... 2 3-25 23.6.3.1. hcrevision (revisio n register) ....................................................................................... 23-25 23.6.3.2. hccontrol (control register)........................................................................................... 23-26 23.6.3.3. hccommandstatus (command/st atus register).............................................................. 23-27 23.6.3.4. hcinterruptstatus (interrupt status regist er) ................................................................... 23-28 23.6.3.5. hcinterruptenable (interrupt enable register) ................................................................ 23-29 23.6.3.6. hcinterruptdisable (interrupt disable regi ster) .............................................................. 23-30 23.6.3.7. hchcca (hcca register).............................................................................................. 23-31 23.6.3.8. hcperiodcurrented (periodic cu rrent ed register)....................................................... 23-31 23.6.3.9. hccontrolheaded (control h ead ed register).............................................................. 23-32 23.6.3.10. hccontrolcurrented (control cu rrent ed register) ...................................................... 23-32 23.6.3.11. hcbulkheaded (bulk head ed register) ...................................................................... 23-33 23.6.3.12. hcbulkcurrented (bulk curr ent ed regist er)............................................................... 23-33 23.6.3.13. hcdonehead (done head register) ................................................................................ 23-34 23.6.3.14. hcfminterval (frame inte rval register) .......................................................................... 23-34 23.6.3.15. hcfmremaining (frame rema ining register)................................................................ 23-35 23.6.3.16. hcfmnumber (frame number register)......................................................................... 23-35 23.6.3.17. hcperiodicstart (periodic start regist er)......................................................................... 23-36 23.6.3.18. hclsthreshold (ls thres hold register)......................................................................... 23-36 23.6.3.19. hcrhdescriptora (root hub desc riptor a regi ster) ...................................................... 23-37 23.6.3.20. hcrhdescriptorb (root hub desc riptor b regi ster) ...................................................... 23-38 23.6.3.21. hcrhstatus (root hub st atus register)........................................................................... 23-39 23.6.3.22. hcrhportstatus[1] (root hub port st atus/control regi ster 1)........................................ 23-40 23.6.4. other registers................................................................................................................ ......... 23-43 23.6.4.1. linkmodesetting (link mode setting regist er).............................................................. 23-43 23.6.4.2. phymodesetting1 (phy mode setting 1 regist er) ........................................................ 23-44 23.6.4.3. phymodesetting2 (phy mode setting 2 regist er) ........................................................ 23-44 24. usb function c ontroller ................................................................................ 24-1 24.1. outline........................................................................................................................ ........................ 24-1 24.2. feature........................................................................................................................ ........................ 24-1 24.3. block diagram .................................................................................................................. .................. 24-2 24.4. supply clock................................................................................................................... .................... 24-3 24.5. register ....................................................................................................................... ....................... 24-3 24.5.1. register list .................................................................................................................. .............. 24-3 24.5.2. usb function cpu access contro l register (u fcpac) .......................................................... 24-5 24.5.3. usb function device control register (ufdvc) ..................................................................... 24-6 24.5.4. usb function device status register (ufdvs)........................................................................ 24-8 24.5.5. usb function endpoint interrupt co ntrol register (ufepic)................................................ 24-10 24.5.6. usb function endpoint interrupt st atus register (ufepis)................................................... 24-11 24.5.7. usb function endpoint dma cont rol register (u fepdc) ................................................... 24-12 24.5.8. usb function endpoint dma stat us register (u fepds) ...................................................... 24-13 24.5.9. usb function time stamp re gister (uftstamp) ................................................................ 24-13 24.5.10. ufeptcsel register............................................................................................................. ... 24-14 24.5.11. usb function endpoint1 terminal co unt register (u feptc1) ............................................. 24-14
xxii MB86R01 lsi product specifications fujitsu semiconductor confidential 24.5.12. usb function endpoint2 terminal co unt register (u feptc2) ............................................. 24-15 24.5.13. usb function endpoint0 rx size register (ufeprs0).......................................................... 24-15 24.5.14. usb function endpoint1 rx size register (ufeprs1).......................................................... 24-16 24.5.15. usb function endpoint2 rx size register (ufeprs2).......................................................... 24-16 24.5.16. usb function endpoint3 rx size register (ufeprs3).......................................................... 24-17 24.5.17. ufcuscnt regist er .............................................................................................................. .... 24-18 24.5.18. ufcalb re gister................................................................................................................ .... 24-19 24.5.19. ufeplpbk regist er.............................................................................................................. ... 24-20 24.5.20. ufintfaltnum register.......................................................................................................... .. 24-21 24.5.21. usb function endpoint0 contro l register (u fepc0) ............................................................ 24-22 24.5.22. usb function endpoint0 status register (ufeps0) ............................................................... 24-24 24.5.23. usb function endpoint1 contro l register (u fepc1) ............................................................ 24-26 24.5.24. usb function endpoint1 status register (ufeps1) ............................................................... 24-29 24.5.25. usb function endpoint2 contro l register (u fepc2) ............................................................ 24-31 24.5.26. usb function endpoint2 status register (ufeps2) ............................................................... 24-34 24.5.27. usb function endpoint3 contro l register (u fepc3) ............................................................ 24-36 24.5.28. usb function endpoint3 status register (ufeps3) ............................................................... 24-39 24.5.29. usb function endpoint0 in buffer register (ufe pib0) ....................................................... 24-41 24.5.30. usb function endpoint1 in buffer register (ufe pib1) ....................................................... 24-41 24.5.31. usb function endpoint2 in buffer register (ufe pib2) ....................................................... 24-41 24.5.32. usb function endpoint3 in buffer register (ufe pib3) ....................................................... 24-42 24.5.33. usb function endpoint0 out buffer register (ufepob0) .................................................. 24-42 24.5.34. usb function endpoint1 out buffer register (ufepob1) .................................................. 24-42 24.5.35. usb function endpoint2 out buffer register (ufepob2) .................................................. 24-43 24.5.36. ufconfig re gisters............................................................................................................. ..... 24-44 24.5.37. usb function endpoint1 dma control/s tatus register (u fepdc1) .................................... 24-47 24.5.38. usb function endpoint2 dma control/s tatus register (u fepdc2) .................................... 24-49 24.5.39. usb function endpoint1 dma addres s register (ufepda1) .............................................. 24-50 24.5.40. usb function endpoint2 dma addres s register (ufepda2) .............................................. 24-51 24.5.41. usb function endpoint1 dma size register (ufepds1) ..................................................... 24-51 24.5.42. usb function endpoint2 dma size register (ufepds2) ..................................................... 24-52 24.6. operation...................................................................................................................... .................... 24-53 24.6.1. endpoint co mpositio n ........................................................................................................... ... 24-53 24.6.2. reset se quence ................................................................................................................. ........ 24-54 24.6.3. to start communication with releasing disconnect of the ufdvc register within 6ms after internal utmi system reset is released ......................................................... 24-55 24.6.4. to release disconnect after shifting the state to suspend without releasing disconnect for 6ms or more after intern al utmi system rese t is releas ed.............................. 24-56 24.6.5. cpubuswidth and cpubyt eoder settin g.................................................................................. 24-57 24.6.6. cpubyteoder setting value and usb transfer byte order......................................................... 24-57 24.6.7. access method to function link endpoi nt buffer (slave interface).................................... 24-58 24.6.8. function link data transfer flow .............................................................................................. 2 4-60 24.6.8.1. setup stage in control transf er (standard command) .................................................... 24-60 24.6.8.2. setup stage in control transfer (class command, vender command, and a part of standard command (get_descriptor/set_descri ptor/synch_frame)) ................................... 24-61 24.6.8.3. status stage in control transfer (standard command) .................................................. 24-62 24.6.8.4. status stage in control transfer (class command, vender command, and a part of standard command (get_descriptor/set_descri ptor/synch_frame)) ................................... 24-63 24.6.8.5. control (data stage)/bulk out transfer........................................................................ 24-65 24.6.8.6. control (data stage)/bulk/in terrupt in transfer............................................................. 24-67
xxiii MB86R01 lsi product specifications fujitsu semiconductor confidential 24.6.9. reception's basic operation (dat a reading by slav e i/f)........................................................... 24-69 24.6.10. reception operati on and status................................................................................................. 24-70 24.6.11. basic transmission operation (dat a writing by the sl ave i/f) ................................................... 24-71 24.6.12. transmission operation and status............................................................................................ 24 -72 24.6.13. notice of control tr ansfer process............................................................................................ 2 4-73 24.6.14. dmac operation (data transfer by master in terface) .............................................................. 24-74 24.6.14.1. 2 modes in dma mode .................................................................................................... 24-76 24.6.14.2. dma inte rface.................................................................................................................. 24-76 24.6.15. dma mode setting procedure .................................................................................................. 24- 77 24.6.16. null packet transmi ssion/reception .......................................................................................... 24- 81 24.6.17. spr mode and spdd mode ..................................................................................................... 24-8 2 24.6.17.1. spr mode....................................................................................................................... .. 24-82 24.6.17.2. spdd mode...................................................................................................................... 24-83 24.6.17.3. mode and dma interface timing ..................................................................................... 24-84 24.6.18. operation timing of empt y* status bit .................................................................................. 24-87 24.6.19. pull-up re sist or ............................................................................................................... ......... 24-88 24.6.20. analog power supply control and an alogue power down control ............................................ 24-89 24.6.21. control for when configuration se tting value (wvalue) receives "0" setconfigurati on command...................................................................................................... 24-90 24.6.22. total count transfer setting value and transfer volume setting value of external dmac......... 24-91 24.6.23. interrupt factor (except usb bus reset) phenomenon after us b bus reset .............................. 24-92 25. ide host controlle r (ide66) ........................................................................... 25-1 25.1. outline........................................................................................................................ ........................ 25-1 25.2. feature........................................................................................................................ ........................ 25-1 25.3. block diagram .................................................................................................................. .................. 25-2 25.4. related pin .................................................................................................................... ..................... 25-3 25.5. supply clock................................................................................................................... .................... 25-3 25.6. register ....................................................................................................................... ....................... 25-4 25.6.1. register list .................................................................................................................. .............. 25-4 25.6.2. cs0 data register (cs0dat) ..................................................................................................... .25-7 25.6.3. cs0 error register (cs0er)..................................................................................................... ... 25-7 25.6.4. cs0 features regi ster (cs0ft) .................................................................................................. .25-7 25.6.5. cs0 sector count re gister (cs0sc) ............................................................................................ 25 -8 25.6.6. cs0 sector number regi ster (cs0sn)......................................................................................... 25-8 25.6.7. cs0 cylinder low regi ster (cs0cl) ........................................................................................... 25- 8 25.6.8. cs0 cylinder high regi ster (cs0ch).......................................................................................... 25- 9 25.6.9. cs0 device/head regi ster (cs0dh)............................................................................................ 25- 9 25.6.10. cs0 status register (cs0st).................................................................................................... ... 25-9 25.6.11. cs0 command register (cs0cmd).......................................................................................... 25-10 25.6.12. cs1 alternate status re gister (cs1as)...................................................................................... 25-1 0 25.6.13. cs1 device control regist er (cs1 dc) ..................................................................................... 25-10 25.6.14. data register (idedat) ......................................................................................................... .. 25-11 25.6.15. pio timing control regist er (ideptcr)................................................................................... 25-11 25.6.16. pio address setup regi ster (idepasr) .................................................................................... 25-12 25.6.17. ide command register ........................................................................................................... .. 25-13 25.6.18. ide status register (ideistr) ................................................................................................. 2 5-14 25.6.19. interrupt enable regi ster (ideiner) ........................................................................................ 25-1 4 25.6.20. interrupt status regi ster (ideinsr) ......................................................................................... 25- 15 25.6.21. fifo command register (idefcmr) ...................................................................................... 25-15 25.6.22. fifo status regist er (idefstr) .............................................................................................. 25- 16
xxiv MB86R01 lsi product specifications fujitsu semiconductor confidential 25.6.23. transmission fifo count re gister (id etfcr)........................................................................ 25-16 25.6.24. reception fifo count regi ster (iderf cr)............................................................................. 25-17 25.6.25. udma timing control regi ster (ideutcr) ............................................................................ 25-17 25.6.26. udma command register (ideucmr) .................................................................................. 25-18 25.6.27. udma status register (ideustr) .......................................................................................... 25-19 25.6.28. rxfifo rest count compar e value (ide rrcc)....................................................................... 25-19 25.6.29. ultra dma timing contro l 1 (ideutc1)................................................................................. 25-20 25.6.30. ultra dma timing contro l 2 (ideutc2)................................................................................. 25-21 25.6.31. ultra dma timing contro l 3 (ideutc3)................................................................................. 25-22 25.6.32. dma status register (idestatus) ......................................................................................... 25-22 25.6.33. interrupt register (ideint) .................................................................................................... .. 25-23 25.6.34. interrupt mask register (ideintmsk) .................................................................................... 25-24 25.6.35. pio access control register (idepioctl)............................................................................... 25-25 25.6.36. dma control register (idedmactl) .................................................................................... 25-26 25.6.37. dma transfer control regi ster (idedmatc) .......................................................................... 25-27 25.6.38. dma source address regist er (idedmasad) ........................................................................ 25-28 25.6.39. dma destination address regi ster (idedmadad) ................................................................ 25-28 25.7. ide operation.................................................................................................................. ................. 25-29 25.7.1. active time and r ecovery time ................................................................................................. 2 5-29 25.7.2. example setting of pio mode register...................................................................................... 25-30 25.7.3. example setting of ultra dm a mode register.......................................................................... 25-31 25.8. function ....................................................................................................................... .................... 25-32 26. ccnt ............................................................................................................. 26-1 26.1. outline........................................................................................................................ ........................ 26-1 26.2. feature........................................................................................................................ ........................ 26-1 26.3. block diagram .................................................................................................................. .................. 26-2 26.4. supply clock................................................................................................................... .................... 26-2 26.5. register ....................................................................................................................... ....................... 26-3 26.5.1. register list .................................................................................................................. .............. 26-3 26.5.2. chip id register (ccid) ........................................................................................................ ... 26-5 26.5.3. software reset re gister (csrst) ................................................................................................ 26-6 26.5.4. interrupt status register (cist)............................................................................................... .... 26-7 26.5.5. interrupt status mask register cistm ................................................................................. 26-9 26.5.6. gpio interrupt status regi ster (cgpio_ist) ........................................................................... 26-11 26.5.7. gpio interrupt status mask register (cgpio_istm) .............................................................. 26-11 26.5.8. gpio interrupt polarity setti ng register (cgpio_ip)............................................................... 26-12 26.5.9. gpio interrupt mode setting register (cgpio_im) ................................................................. 26-12 26.5.10. axi bus wait cycle setting re gister (caxi_bw)..................................................................... 26-13 26.5.11. axi polarity setting regi ster (caxi_ps) ................................................................................. 26-14 26.5.12. multiplex mode setting regi ster (cmux_md)........................................................................ 26-16 26.5.13. external pin status regi ster (cex_pin_st)............................................................................. 26-17 26.5.14. medialb setting regist er (cmlb) ........................................................................................... 26-18 26.5.15. usb set regist er (cusb)........................................................................................................ .. 26-20 26.5.16. byte swap switching re gister (cbs c)...................................................................................... 26-21 26.5.17. ddr2 controller reset contro l register (cdcrc) .................................................................... 26-23 26.5.18. software reset register 0 for macro (cmsr0).......................................................................... 26-24 26.5.19. software reset register 1 for macro (cmsr1).......................................................................... 26-26 27. external interrupt co ntroller (e xirc) ........................................................... 27-1
xxv MB86R01 lsi product specifications fujitsu semiconductor confidential 27.1. outline........................................................................................................................ ........................ 27-1 27.2. feature........................................................................................................................ ........................ 27-1 27.3. block diagram .................................................................................................................. .................. 27-2 27.4. supply clock................................................................................................................... .................... 27-2 27.5. register ....................................................................................................................... ....................... 27-3 27.5.1. register list .................................................................................................................. .............. 27-3 27.5.2. external interrupt enable register (eienb)................................................................................ 27-5 27.5.3. external interrupt request register (eireq)............................................................................... 27-6 27.5.4. external interrupt level register (eilvl) ................................................................................... 27- 7 27.6. operation...................................................................................................................... ...................... 27-8 27.7. operation procedure............................................................................................................ ............... 27-8 27.8. instruction for use ............................................................................................................ .................. 27-8 28. sd memory contro ller (sdm c) ..................................................................... 28-1
1-1 MB86R01 lsi product specifications fujitsu semiconductor confidential outline 1. outline this chapter describes feature, block diagram, and function of MB86R01. 1.1. feature MB86R01 is lsi product for the graphics applications with arm limited's cpu arm926ej-s and fujitsu's gdc mb86296 as its core. this product cont ains peripheral i/o resources, such as in-vehicle lan, hdd, and usb; therefore only a single chip of MB86R01 controls main graphics application system which usually requires 2 chips (cpu and gdc.) MB86R01 has following features: ? cmos 90nm technology ? package: pbga484 ? power-supply voltage: (io: 3.3 0.3v, core: 1.2 0.1v, ddr2: 1.8 0.1v) ? operation frequency: 333mhz (cpu), 83mhz (ahb), 41.5mhz (apb) ? cpu core ? arm926ej-s ? 16kb instruction cache/16kb data cache ? 16kb itcm/16kb dtcm ? etm9cs single and jtag ice interface ? java acceleration (jazelle technology) ? bus architecture ? multi-layer ahb bus architecture ? interrupt ? built-in sram ? clock/reset control function ? remap/boot control function ? 16 bit external bus interface with decoding engine ? 32 bit ddr2 memory interface (target: 166mhz: 333mbps) ? graphics display controller ? 2d/3d rendering engine of fujitsu mb86296 ? rgb66 video output 1ch (extensible to rgb888 with using option i/o) ? itu rbt-656 video capture 1ch (extensible to rgb666 with using option i/o) ? usb 2.0 host (hs/fs protocols) 1ch ? ide66 (ata/atapi-5) 1ch ? sd memory controller (sdio/cprm: unsupported) 1ch ? 10 bit a/d converter (1ms/s) 2ch ? i 2 c (i/o voltage: 3.3v) 2ch ? uart 3ch (extensible up to 6ch with using option i/o) ? 32/16 bit timer 2ch ? dmac 8ch option i/o (with pin multiplex) ? rgb666 video output is extensible to 2ch ? video capture is extensible to 2ch ? medialb (most50) 1ch is addable ? can (i/o voltage: 3.3v) 2ch is addable ? usb 2.0 function (hs/fs protocols) is switchable (usb 2.0 function and usb 2.0 host are accessed exclusively)
1-2 MB86R01 lsi product specifications fujitsu semiconductor confidential outline ? gpio is addable up to 24 ? spi 1ch is addable ? pwm 2ch is addable ? i2s is addable up to 3ch ? the number of uart channel is extensible up to 6ch ? the data width in the external bus interface is extensible to 32 bit
1-3 MB86R01 lsi product specifications fujitsu semiconductor confidential outline 1.2. block diagram figure 1-1 shows block diagram of MB86R01. crg m1-0 m1-1 s1-00 m1-2 s1-01 master no. slave no. dmac 8ch s1-04 rbc gpio 24ch extirc 4ch uart 4 32bit timer 2ch i-tcm 16kb etm9cssingle s1-12 s1-05 s1-02 usb2.0 host m1-4 sram 32kb s1-10 medialb ide66 s1-08 ccpb s1-11 boot rom 32kb uart 2 s1-15 d i i2s_1 sdmc i2s_0 jtag_sel chip_jtag s2-00 s1-13 s1-14 irc irc 2 s1-07 usb2.0 function phy m1-5 usb2.0 function dmac s2-02 s1-03 disp ddr2 controller mbus2axi mbus2axi disp cap cap draw & geo host if ahb2axi s2-03 m1-6 ide66 dmac m2-0 m1-7 s1-09 s2-01 m1-8 wrapper external bus i/f hbus2axi sram 32kb s1-06 i2s_2 s2-04 can 2 pwm 2 uart 2 i2c 2 adc 4 adc 2 i2c 2 can 2 pwm 2ch spi 1 ccnt uart 4 uart 2 wrapper d-tcm 16kb i-cache 16kb d-cache 16kb jtag if figure 1-1 block diagram of MB86R01 cpu core cpu core block of arm926ej-s is connected to each i/o through ahb bus in lsi. instruction (i)/data (d) function as a separate bus ma ster for harvard architecture. gdc_top mb86296 compatible gdc has 2 functions: ahb slav e function which writes required display list for drawing to gdc with having cpu or dma controller as master, and axi master function which reads display list arranged in ddr2 memory with having gdc as master. axi bus this bus bridges main memory and internal re source. following 4 bus masters are connected. ? ahb1: each bus master of ahb bus such as cpu and dma controller ? hbus: host if on gdc ? draw & geo: draw (2d/3d drawing) and geo (geometry engine) on gdc ? mbus: disp (display controller) and cap (video capture) on gdc
1-4 MB86R01 lsi product specifications fujitsu semiconductor confidential outline ahb1 bus following resources are connected. ? cpu core: bus masters of instruction (i)/data (d) ? gdc: gdc register part ? ahb2axi: axi port for main memory access ? ccpb: encrypted rom decoding block ? external bus i/f: external bus in terface (connected through ccpb) ? sram: general purpose internal sram 32kb 2 ? dmac: general purpose dma 8ch it operates as bus master at data transfer ? boot rom: built-in boot rom ? i2s_0/1/2: serial audio controller 3ch ? usb 2.0 function dmac: usb function dmac it operates as bus master at data transfer ? usb 2.0 host: it operates as usb 2.0 ehci, usb 1.1 ohci bus masters ? ide66/ide66dmac: register part of ide host controller and built-in dmac the dmac part operates as bus master at data transfer ? mlb: medialb controller ? ahb2 ? apbbrg0/1/2: ahb-apb bridge circuit 3ch ahb2 bus ? ccpb: encrypted rom decoding block ? usb 2.0 function: usb 2.0 function controller's register part ? usb 2.0 host: usb 2.0 host controller's register part ? sdmc: sd memory controller ? ddr2 controller: ddr2 controller's register part apb_top_0 this block bridges between apbbrg0 bus and the ah b1 bus, and following low-speed peripheral resources are connected. ? interrupt controller (irc) 2ch ? external interrupt controller (extirc) ? clock reset generator (crg) ? uart (ch0 and ch1) 2ch ? remap boot controller (rbc) ? 32 bit general-purpose timer (32 bit timer) 2ch apb_top_1 this block bridges between apbbrg1 bus and ahb1 bus, and following low-sp eed peripheral resources are connected. ? i 2 c controller 2ch ? can controller 2ch ? uart (ch2 and ch3) 2ch ? a/d converter (adc) 2ch apb_top_2 this block bridges between apbbrg2 bus and ahb1 bus, and following low-sp eed peripheral resources are connected. ? pwm controller (pwm) ? spi controller (spi) ? chip control module (ccnt) ? uart (ch4 and ch5) 2ch
1-5 MB86R01 lsi product specifications fujitsu semiconductor confidential outline 1.3. function list function list of MB86R01 is shown below. table 1-1 MB86R01 function list function outline cpu core ? arm926ej-s tm processor core ? core operation frequency: 333mhz ? 16kb instruction cache ? 16kb data cache ? tightly-coupled memory for 16kb instruction (itcm) ? tightly-coupled memory for 16kb data (dtcm) ? etm9cs single and jtag ice debugging interface ? java acceleration (jazelle technology) bus architecture ? multilayer ahb bus architecture ? speeding up data transfer between main memo ry and each bus master with 64 bit axi bus interrupt ? high-speed interrupt 1ch (software interrupt) ? normal interrupt 64ch (external interrupt 4ch + built-in internal interrupt 60ch) ? up to 16 interrupt levels are settable by channel clock ? pll multiplication: selectable from 15 ~ 49 ? operation frequency: 333mhz (cpu), 83mhz (ahb), 41.5mhz (apb) ? low power consumption mode (clock to arm and module is stoppable) reset ? hardware reset, software reset, and watchdog reset remap ? rom area is able to be mapping to built-in sram area external bus interface ? three chip select signals ? provided 32m byte address space in each chip select ? supported 16/32 bit width sram/flash rom connection ? programmable wei ght controller ? encrypted rom compound engine ddr2 controller ? supported ddr2sdram (ddr2-400) ? connectable capacity: 256 ~ 512m bit 2 or 256 ~ 512m bit 1 ? i/o width: selectable from 16/ 32 bit ? max. transfer rate: 166mhz/333mbps built-in sram ? mounted general purpose sram of 32kb 2 (32 bit bus) dmac ? ahb connection 8ch ? transfer mode: block, burst, and demand timer ? 32/16 bit programmable 2 channels gpio(*2) ? max. 24 is usable ? interrupt function pwm(*2) ? built-in 2 channels ? duty ratio and phase are configurable a/d converter ? 10 bit successive approxima tion type a/d converter 2ch ? sampling rate: 648ks/s (max. sampling plate) ? nonlinearity error: 2.0lsb (max.)
1-6 MB86R01 lsi product specifications fujitsu semiconductor confidential outline function outline gdc (*1) ? display controller rgb666 or rgb888 output max. resolution is 1024 768 max. 6 layered display max. 2 screen output ? digital video capture function bt.601, bt.656, and rgb666 max. 2 inputs ? geometry engine (mb86296 compa tible display list is usable) ? 2d/3d drawing function (mb86296 comp atible display list is usable) i 2 s (*2) ? audio output 3ch (l/r) /audio input 3ch (l/r) ? supported three-wire serial (i2s, msb-justified) and serial pcm data transfer interface ? master/slave operations are selectable ? resolution capability: max. 32 bit/sample uart (*2) ? max. 6 channels (dedicated channel: 3ch, option: 3ch) ? 1 channel: capable of input/output cts/rts signals ? 8 bit pre-scaler for baud rate clock generation ? enabled dma transfer i2c ? 3.3v pin 2ch ? supported standard mode (max. 100kbps)/high-speed mode (max. 400kbps) spi (*2) ? full duplex/synchronous transmission ? transfer data length: 1 bit unit (max . 32 bit) (programmable setting) can (*2) ? mounted bosch c_can module 2ch ? conformed to can protocol version 2.0 part a and b ? i/o voltage: 3.3v medialb (*2) ? 16 channels ? medialb clock speed: 256fs/512fs/1024fs ? built-in 9k bit channel buffer usb (*2) ? usb 2.0 compliant host/function controller 1ch (pin multiplex) ? hs/fs protocol support (supported vbus and isochronous transfer) ide (*2) ? supported ata/atapi-5 ? equipped 1 channel ? supported primary ide channel ? equipped transmission fifo buffer (512 byte 2) and reception fifo buffer (512 byte 2) for the ultra dma transfer ? unsupported single word dma and multiword dma sd memory ? conformed to sd memory card physical layer specification 1.0 ? equipped 1 channel ? supported sd memory card and multimedia card ? unsupported spi mode, sd io mode, and cprm ccnt ? mode selection of multiplex pin group 2 and 4 ? software reset control ? axi interconnection control (priority and wait setting) jtag ? conformed to ieieee1149.1 (ieee standard test access port and boundary-scan architecture) ? supported jtag ice connection *1: num b er of layer of simultaneous display and number of outpu t display as well as capture input for displaying in high resolution may be restricted due to data su pply capacity of graphics memory (ddr2 controller). *2: a part of external pin functions of this lsi is multip lexed. max. number of usable channel is limited by pin multiplex function setting.
1-7 MB86R01 lsi product specifications fujitsu semiconductor confidential outline 1.4. package dimension package dimension of MB86R01 is shown below. figure 1-2 bga-484p-m07 package dimension
1-8 MB86R01 lsi product specifications fujitsu semiconductor confidential outline 1.5. pin assignment pin assignment of MB86R01 is shown below. (top view) 1234567891011121314151617181920212223242526 a 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 b 2 101 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 75 c 3 102 193 276 275 274 273 272 271 270 269 268 267 266 265 264 263 262 261 260 259 258 257 256 169 74 d 4 103 194 277 352 351 350 349 348 347 346 345 344 343 342 341 340 339 338 337 336 335 334 255 168 73 e 5 104 195 278 353 420 419 418 417 416 415 414 413 412 411 410 409 408 407 406 405 404 333 254 167 72 f 6 105 196 279 354 403 332 253 166 71 g 7 106 197 280 355 402 331 252 165 70 h 8 107 198 281 356 401 330 251 164 69 j 9 108 199 282 357 400 329 250 163 68 k 10 109 200 283 358 421 448 447 446 445 444 443 442 399 328 249 162 67 l 11 110 201 284 359 422 449 468 467 466 465 464 441 398 327 248 161 66 m 12 111 202 285 360 423 450 469 480 479 478 463 440 397 326 247 160 65 n 13 112 203 286 361 424 451 470 481 484 477 462 439 396 325 246 159 64 p 14 113 204 287 362 425 452 471 482 483 476 461 438 395 324 245 158 63 r 15 114 205 288 363 426 453 472 473 474 475 460 437 394 323 244 157 62 t 16 115 206 289 364 427 454 455 456 457 458 459 436 393 322 243 156 61 u 17 116 207 290 365 428 429 430 431 432 433 434 435 392 321 242 155 60 v 18 117 208 291 366 391 320 241 154 59 w 19 118 209 292 367 390 319 240 153 58 y 20 119 210 293 368 389 318 239 152 57 aa 21 120 211 294 369 388 317 238 151 56 ab 22 121 212 295 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 316 237 150 55 ac 23 122 213 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 236 149 54 ad 24 123 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 148 53 ae 25 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 52 af 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 figure 1-3 MB86R01 pin assignment (pin number)
1-9 MB86R01 lsi product specifications fujitsu semiconductor confidential outline (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 a vss vss dclko0 vss dclkin0 doutg0 [6] doutg0 [2] doutb0 [4] xsrst trace data[3] xrst pllvss pllvdd tdo vss clk mem xrd vss mem ea[20] mem ea[16] mem ea[12] mem ea[8] mem ea[4] mem ea[1] vss vss b vss de0 hsync0 vdde doutr0 [4] doutg0 [7] doutg0 [3] doutb0 [5] xtrst trace ctl trace data[0] tms vinithi cripm3 vdde mem xcs[4] mem xwr[1] mem ea[23] mem ea[19] mem ea[15] mem ea[11] mem ea[7] mem ea[3] mem ed[15] mem ed[14] vss c doutb1 [2] gv0 vsync0 doutr0 [7] doutr0 [5] doutr0 [2] doutg0 [4] doutb0 [6] doutb0 [2] trace clk trace data[1] jtagsel tck cripm2 cripm0 mem xcs[2] mem xwr[0] mem ea[22] mem ea[18] mem ea[14] mem ea[ 10] mem ea[6] mem ea[2] mem ed[13] mem ed[12] mem ed[11] d doutb1 [6] doutb1 [5] doutb1 [4] doutb1 [3] doutr0 [6] doutr0 [3] doutg0 [5] doutb0 [7] doutb0 [3] rtck trace data[2] p lltdtrs t tdi cripm1 mem rdy mem xcs[0] mem ea[24] mem ea[21] mem ea[17] mem ea[13] mem ea[9] mem ea[5] mem ed[10] mem ed[9] mem ed[8] mem ed[7] e doutg1 [4] doutg1 [3] doutg1 [2] doutb1 [7] vdde vss vss vdde vdde vddi vddi vss vss vdde vdde vddi vddi vss vss vdde vdde v ddi mem ed[6] mem ed[5] mem ed[4] mem ed[3] f doutr1 [2] doutg1 [7] doutg1 [6] doutg1 [5] vdde vddi mem ed[2] mem ed[1] mem ed[0] vss g dclkin 1 doutr1 [5] doutr1 [4] doutr1 [3] vddi vss mdq[30] mdm[3] mdq[31] mdqs p[3] h vss vdde doutr1 [7] doutr1 [6] vddi vss mdq[25] mdq[28] mdq[24] mdqs n[3] j dclko1 gv1 vsync1 hsync1 vss ddrvde mdq[27] mdq[26] mdq[29] vss k vin0 [5] vin0 [6] vin0 [7] de1 vss vddi vdde vdde vddi vddi vdde vdde vddi ddrvde mdm[2] mdq[23] vr ef1 mdqs p[2] l vin0 [1] vin0 [2] vin0 [3] vin0 [4] vdde vddi vss vss vss vss vss vss vddi dq22 mdq[20] mdq[17] mdq[16] mdqs n[2] m cclk0 vdde vin vsync0 vin0 [0] vdde vdde vss vss vss vss vss vss ddrvde vss mdq[19] mdq[18] mdq[21] vss n vss vinfid0 vin hsync0 vddi vddi vdde vss vss vss vss vss vss ddrvde vddi odt vss ddrvde mckp p usb avsp usb avdp usb avsf1 usb_ avsb usb avdb vddi vss vss vss vss vss vss vddi vddi ocd vss ddrvde mckn r usb hsdp usb fsdp usb avdf1 usb avsf2 usb ext12k vddi vss vss vss vss vss vss vddi vss mdq[14] mdm[1] mdq[15] vss t usb hsdm usb fsdm usb avsf2 usb avsf2 usb avsf2 vdde vss vss vss vss vss vss ddrvde ddrvde mdq[12] mdq[9] mdq[8] mdqs p[1] u usb avsf2 usb avsf2 usb avdf2 vss vddi vdde vddi vddi vdde vdde vddi vddi ddrvde ddrvde mdq[11] mdq[10] mdq[13] mdqs n[1] v usb cryck48 usb mode vin1 [7] vss vddi mdq[6] mdm[0] mdq[7] vref0 vss w vin1 [6 ] vin1 [5] vin1 [4] vin1 [3] vdde vss mdq[4] mdq[1] mdq[0 mdqs p[0] y vss vin1 [2] vin1 [1] vin1 [0] vdde vss mdq[3] mdq[5] mdq[2] mdqs n[0] aa cclk1 vdde vin vsync1 vin hsync1 vss ddrvde mcas mras mcke vss ab vinfid1 i2s sdo2 i2s sdi2 i2s ws2 vss vdde vdde vddi vddi vss vss vdde ad vrl0 ad vrl1 vss vss vss vdde vdde vddi vddi ddrvde mcs mwe mba[0] mba[1] ac i2s sck2 pwm_o1 ide diordy ide dintrq ide dd[15] ide dd[11] ide dd[7] ide dd[3] ide da[2] ide xdiow mpx mode_1 [0] test mode[0] ad vr0 ad vr1 vdde uart sin2 sd clk sd dat[3] vpd int_a [2] ddrtype odtcon t ma[0] ma[2] ma[10] ma[1] ad i2s eclk2 pwm_o0 ide xcblid ide ddmarq ide dd[14] ide dd[10] ide dd[6] ide dd[2] ide da[1] ide xdior mpx mode_1 [1] pll bypass ad vin0 ad vin1 vdde uart sout2 sd cmd sd dat[2] usb prtpwr i2c sda0 int_a [1] test mode[2] ma[9] ma[6] ma[5] ma[3] ae vss vss ide xdasp ide xddmac k ide dd[13] ide dd[9] ide dd[5] ide dd[1] ide da[0] ide xdcs[0] mpx mode_5 [0] bigend ad vrh0 ad vrh1 uart xrts0 uart xcts0 uart sout1 sd dat[1] sd xmcd i2c scl0 int_a [3] mcke start ma[13] ma[4] ma[11] ma[7] af vss vss ide xiocs16 ide dreset ide dd[12] ide dd[8] ide dd[4] id e dd[0] ide csel ide xdcs[1] mpx mode_5 [1] test mode[1] ad avd ad avs uart sout0 uart sin0 uart sin1 sd dat[0] sd wp i2c scl1 i2c sda1 int_a [0] ma[8] ma[12] vss vss figure 1-4 MB86R01 pin assignment (pin name)
1-10 MB86R01 lsi product specifications fujitsu semiconductor confidential outline table 1-2 pin assignment table pin no jedec pin name pin no jedec pin name pin no jedec pin name pin no jedec pin name pin no jedec pin name 1 a1 vss 101 b2 de0 201 l3 vin0[3] 301 ac9 ide_da[2] 401 h22 vss 2 b1 vss 102 c2 gv0 202 m3 vinvsync0 302 ac10 ide_xdiow 402 g22 vss 3 c1 doutb1[2] 103 d2 doutb1[5] 203 n3 vinhsync0 303 ac11 mpx_mode_1[0] 403 f22 vddi 4 d1 doutb1[6] 104 e2 doutg1[3] 204 p3 usb_avsf1 304 ac12 testmode[0] 404 e2 2 vddi 5 e1 doutg1[4] 105 f2 doutg1[7] 205 r3 usb_avdf1 305 ac13 ad_vr0 405 e21 vdde 6 f1 doutr1[2] 106 g2 doutr1[5] 206 t3 usb_avsf2 306 ac14 ad_vr1 406 e20 vdde 7 g1 dclkin1 107 h2 vdde 207 u3 usb_avdf2 307 ac15 vdde 407 e19 vss 8 h1 vss 108 j2 gv1 208 v3 vin1[7] 308 ac16 uart_sin2 408 e18 vss 9 j1 dclko1 109 k2 vin0[6] 209 w3 vin1[4] 309 ac17 sd_clk 409 e17 vddi 10 k1 vin0[5] 110 l2 vin0[2] 210 y3 vin1[1] 310 ac18 sd_dat[3] 410 e16 vddi 11 l1 vin0[1] 111 m2 vdde 211 aa3 vinvsync1 311 ac19 vpd 411 e15 vdde 12 m1 cclk0 112 n2 vinfid0 212 ab3 i2s_sdi2 312 ac20 int_a[2] 412 e14 vdde 13 n1 vss 113 p2 usb_avdp 213 ac3 ide_diordy 313 ac21 ddrtype 413 e13 vss 14 p1 usb_avsp 114 r2 usb_fsdp 214 ad3 ide_xcblid 314 ac22 odtcont 414 e12 vs s 15 r1 usb_hsdp 115 t2 usb_fsdm 215 ad4 ide_ddmarq 315 ac23 ma[0] 415 e11 vddi 16 t1 usb_hsdm 116 u2 usb_avsf2 216 ad5 ide_dd[14] 316 ab23 mcs 416 e10 vddi 17 u1 usb_avsf2 117 v2 usb_mode 217 ad6 ide_dd[10] 317 aa23 mcas 417 e9 vdde 18 v1 usb_cryck48 118 w2 vin1[5] 218 ad7 ide_dd[6] 318 y23 mdq[3] 418 e8 vdde 19 w1 vin1[6] 119 y2 vin1[2] 219 ad8 ide_dd[2] 319 w23 mdq[4] 419 e7 vss 20 y1 vss 120 aa2 vdde 220 ad9 ide_da[1] 320 v23 mdm[0] 420 e6 vss 21 aa1 cclk1 121 ab2 i2s_sdo2 221 ad10 ide_xdior 321 u23 mdq[11] 421 k10 vddi 22 ab1 vinfid1 122 ac2 pwm_o1 222 ad11 mpx_mode_1[1] 322 t23 mdq[12] 422 l10 vddi 23 ac1 i2s_sck2 123 ad2 pwm_o0 223 ad12 pllbypass 323 r23 mdq[14] 423 m10 vdd e 24 ad1 i2s_eclk2 124 ae2 vss 224 ad13 ad_vin0 324 p23 ocd 424 n10 vdde 25 ae1 vss 125 ae3 ide_xdasp 225 ad14 ad_vin1 325 n23 odt 425 p10 vddi 26 af1 vss 126 ae4 ide_xddmack 226 ad15 vdde 326 m23 mdq[19] 426 r10 vddi 27 af2 vss 127 ae5 ide_dd[13] 227 ad16 uart_sout2 327 l23 mdq[20] 427 t10 vdd e 28 af3 ide_xiocs16 128 ae6 ide_dd[9] 228 ad17 sd_cmd 328 k23 mdm[2] 428 u10 v dde 29 af4 ide_xdreset 129 ae7 ide_dd[5] 229 ad18 sd_dat[2] 329 j23 mdq[27] 429 u11 vddi 30 af5 ide_dd[12] 130 ae8 ide_dd[1] 230 ad19 usb_prtpwr 330 h23 mdq[25] 430 u12 vddi 31 af6 ide_dd[8] 131 ae9 ide_da[0] 231 ad20 i2c_sda0 331 g23 mdq[30] 431 u13 vdde 32 af7 ide_dd[4] 132 ae10 ide_xdcs[0] 232 ad21 int_a[1] 332 f23 mem_ed[2] 4 32 u14 vdde 33 af8 ide_dd[0] 133 ae11 mpx_mode_5[0] 233 ad22 testmode[2] 333 e23 mem_e d[6] 433 u15 vddi 34 af9 ide_csel 134 ae12 bigend 234 ad23 ma[9] 334 d23 mem_ed[10] 434 u16 vdd i 35 af10 ide_xdcs[1] 135 ae13 ad_vrh0 235 ad24 ma[6] 335 d22 mem_ea[5] 435 u1 7 ddrvde 36 af11 mpx_mode_5[1] 136 ae14 ad_vrh1 236 ac24 ma[2] 336 d21 mem_ea[9] 436 t17 ddrvde 37 af12 testmode[1] 137 ae15 uart_xrts0 237 ab24 mwe 337 d20 mem_ea[13] 437 r17 vddi 38 af13 ad_avd 138 ae16 uart_xcts0 238 aa24 mras 338 d19 mem_ea[17] 438 p17 v ddi 39 af14 ad_avs 139 ae17 uart_sout1 239 y24 mdq[5] 339 d18 mem_ea[21] 439 n17 ddrvde 40 af15 uart_sout0 140 ae18 sd_dat[1] 240 w24 mdq[1] 340 d17 mem_ea[24] 440 m17 ddrvde 41 af16 uart_sin0 141 ae19 sd_xmcd 241 v24 mdq[7] 341 d16 mem_xcs[0] 441 l17 vddi 42 af17 uart_sin1 142 ae20 i2c_scl0 242 u24 mdq[10] 342 d15 mem_rdy 442 k17 v ddi 43 af18 sd_dat[0] 143 ae21 int_a[3] 243 t24 mdq[9] 343 d14 cripm1 443 k16 vdd e 44 af19 sd_wp 144 ae22 mcke_start 244 r24 mdm[1] 344 d13 tdi 444 k15 vdde 45 af20 i2c_scl1 145 ae23 ma[13] 245 p24 vss 345 d12 plltdtrst 445 k14 vddi 46 af21 i2c_sda1 146 ae24 ma[4] 246 n24 vss 346 d11 tracedata[2] 446 k13 vddi 47 af22 int_a[0] 147 ae25 ma[11] 247 m24 mdq[18] 347 d10 rtck 447 k12 vdde 48 af23 ma[8] 148 ad25 ma[5] 248 l24 mdq[17] 348 d9 doutb0[3] 448 k11 vdde 49 af24 ma[12] 149 ac25 ma[10] 249 k24 mdq[23] 349 d8 doutb0[7] 449 l11 vss 50 af25 vss 150 ab25 mba[0] 250 j24 mdq[26] 350 d7 doutg0[5] 450 m11 vss 51 af26 vss 151 aa25 mcke 251 h24 mdq[28] 351 d6 doutr0[3] 451 n11 vss 52 ae26 ma[7] 152 y25 mdq[2] 252 g24 mdm[3] 352 d5 doutr0[6] 452 p11 vss 53 ad26 ma[3] 153 w25 mdq[0] 253 f24 mem_ed[1] 353 e5 vdde 453 r11 vss 54 ac26 ma[1] 154 v25 vref0 254 e24 mem_ed[5] 354 f5 vdde 454 t11 vss 55 ab26 mba[1] 155 u25 mdq[13] 255 d24 mem_ed[9] 355 g5 vddi 455 t12 vss 56 aa26 vss 156 t25 mdq[8] 256 c24 mem_ed[13] 356 h5 vddi 456 t13 vss 57 y26 mdqsn[0] 157 r25 mdq[15] 257 c23 mem_ea[2] 357 j5 vss 457 t14 vss 58 w26 mdqsp[0] 158 p25 ddrvde 258 c22 mem_ea[6] 358 k5 vss 458 t15 vss 59 v26 vss 159 n25 ddrvde 259 c21 mem_ea[10] 359 l5 vdde 459 t16 vss 60 u26 mdqsn[1] 160 m25 mdq[21] 260 c20 mem_ea[14] 360 m5 vdde 460 r16 vss 61 t26 mdqsp[1] 161 l25 mdq[16] 261 c19 mem_ea[18] 361 n5 vddi 461 p16 vss 62 r26 vss 162 k25 vref1 262 c18 mem_ea[22] 362 p5 usb_avdb 462 n16 vss 63 p26 mckn 163 j25 mdq[29] 263 c17 mem_xwr[0] 363 r5 usb_ext12k 463 m16 vss 64 n26 mckp 164 h25 mdq[24] 264 c16 mem_xcs[2] 364 t5 usb_avsf2 464 l16 vss 65 m26 vss 165 g25 mdq[31] 265 c15 cripm0 365 u5 vddi 465 l15 vss 66 l26 mdqsn[2] 166 f25 mem_ed[0] 266 c14 cripm2 366 v5 vddi 466 l14 vss 67 k26 mdqsp[2] 167 e25 mem_ed[4] 267 c13 tck 367 w5 vdde 467 l13 vss 68 j26 vss 168 d25 mem_ed[8] 268 c12 jtagsel 368 y5 vdde 468 l12 vss 69 h26 mdqsn[3] 169 c25 mem_ed[12] 269 c11 tracedata[1] 369 aa5 vss 469 m12 v ss 70 g26 mdqsp[3] 170 b25 mem_ed[14] 270 c10 traceclk 370 ab5 vss 470 n12 vss 71 f26 vss 171 b24 mem_ed[15] 271 c9 doutb0[2] 371 ab6 vdde 471 p12 vss 72 e26 mem_ed[3] 172 b23 mem_ea[3] 272 c8 doutb0[6] 372 ab7 vdde 472 r12 vss 73 d26 mem_ed[7] 173 b22 mem_ea[7] 273 c7 doutg0[4] 373 ab8 vddi 473 r13 vss 74 c26 mem_ed[11] 174 b21 mem_ea[11] 274 c6 doutr0[2] 374 ab9 vddi 474 r14 vs s 75 b26 vss 175 b20 mem_ea[15] 275 c5 doutr0[5] 375 ab10 vss 475 r15 vss 76 a26 vss 176 b19 mem_ea[19] 276 c4 doutr0[7] 376 ab11 vss 476 p15 vss 77 a25 vss 177 b18 mem_ea[23] 277 d4 doutb1[3] 377 ab12 vdde 477 n15 vss 78 a24 mem_ea[1] 178 b17 mem_xwr[1] 278 e4 doutb1[7] 378 ab13 ad_vrl0 478 m1 5vss 79 a23 mem_ea[4] 179 b16 mem_xcs[4] 279 f4 doutg1[5] 379 ab14 ad_vrl1 479 m1 4vss 80 a22 mem_ea[8] 180 b15 vdde 280 g4 doutr1[3] 380 ab15 vss 480 m13 vss 81 a21 mem_ea[12] 181 b14 cripm3 281 h4 doutr1[6] 381 ab16 vss 481 n13 vss 82 a20 mem_ea[16] 182 b13 vinithi 282 j4 hsync1 382 ab17 vss 482 p13 vss 83 a19 mem_ea[20] 183 b12 tms 283 k4 de1 383 ab18 vdde 483 p14 vss 84 a18 vss 184 b11 tracedata[0] 284 l4 vin0[4] 384 ab19 vdde 484 n14 vss 85 a17 mem_xrd 185 b10 tracectl 285 m4 vin0[0] 385 ab20 vddi 86 a16 clk 186 b9 xtrst 286 n4 vddi 386 ab21 vddi 87 a15 vss 187 b8 doutb0[5] 287 p4 usb_avsb 387 ab22 ddrvde 88 a14 tdo 188 b7 doutg0[3] 288 r4 usb_avsf2 388 aa22 ddrvde 89 a13 pllvdd 189 b6 doutg0[7] 289 t4 usb_avsf2 389 y22 vss 90 a12 pllvss 190 b5 doutr0[4] 290 u4 vss 390 w22 vss 91 a11 xrst 191 b4 vdde 291 v4 vss 391 v22 mdq[6] 92 a10 tracedata[3] 192 b3 hsync0 292 w4 vin1[3] 392 u22 ddrvde 93 a9 xsrst 193 c3 vsync0 293 y4 vin1[0] 393 t22 ddrvde 94 a8 doutb0[4] 194 d3 doutb1[4] 294 aa4 vinhsync1 394 r22 vss 95 a7 doutg0[2] 195 e3 doutg1[2] 295 ab4 i2s_ws2 395 p22 vddi 96 a6 doutg0[6] 196 f3 doutg1[6] 296 ac4 ide_dintrq 396 n22 vddi 97 a5 dclkin0 197 g3 doutr1[4] 297 ac5 ide_dd[15] 397 m22 vss 98 a4 vss 198 h3 doutr1[7] 298 ac6 ide_dd[11] 398 l22 mdq[22] 99 a3 dclko0 199 j3 vsync1 299 ac7 ide_dd[7] 399 k22 ddrvde 100 a2 vss 200 k3 vin0[7] 300 ac8 ide_dd[3] 400 j22 ddrvde
1-11 MB86R01 lsi product specifications fujitsu semiconductor confidential outline 1.6. pin function external pin function of MB86R01 is described below. 1.6.1. pin multiplex this lsi adopts pin multiplex function, and a part of external pin function is multiplexed. the external pin function is categorized into following five groups. each group is able to set the external pin function individually; therefore, the function can be flexibly set depending on the peripheral i/o resource to be used. 1. pin multiplex group #1 (setting pin: mpx_mode_1[1:0]) ? mode 0: pin related to display1 ? mode 1: pin related to external bus interface ? mode 2: pin related to i2s0, gpio, and display0 data width extension 2. pin multiplex group #2 (setting register: cmux_md.mpx_mode_2[2:0]) ? mode 0: pin related to cap1, cap0 synchronizing signal, pwm, and i2s2 ? mode 1: pin related to cap1 (nrgb666) ? mode 2: pin related to gpio, can, i2s1, medialb, and i2s2 ? mode 3: pin related to gpio, can, i2s1, medialb, and spi ? mode 4: pin related to gpio, can, i2s1, medialb, and i2s2 (input) 3. pin multiplex group #3 (setting pin: usb_mode) ? mode 0: pin related to usb2.0 host ? mode 1: pin related to usb2.0 function 4. pin multiplex group #4 (setting register: cmux_md.mpx_mode_4[1:0]) ? mode 0: pin related to ide66 ? mode 1: pin related to i2s1, can, gpio, and pwm 5. pin multiplex group #5 (setting pin: mpx_mode_5[1:0]) ? mode 0: pin related to etm ? mode 1: pin related to uart3, uart4, and uart5 ? mode 2: pin related to uart3, uart4, and pwm note: ? be sure to set each group of the pin mu ltiplex to any of the modes after power-on. ? mode should be changed when each pin is not in operation. ? pwm, i2s1, and can pins may be duplicated and allocated to external pin depending on group combination; in this case, use either of them. for unused pin, follow the procedure in 1.6.27, unused pin with pin multiplex function in the duplex case.
1-12 MB86R01 lsi product specifications fujitsu semiconductor confidential outline pin multiplex group #1 (setting pin: mpx_mode_1 [1:0]) table 1-3 pin function of pi n multiplex group #1 by mode mode 0 mode 1 mode 2 pin no. jedec pin related to display1 pin related to external bus interface pin related to i2s0 pin related to gpio pin related to display0 pin related to external bus interface 198 h3 doutr1[7] mem_ed[31] i2s_eclk0 - - - 281 h4 doutr1[6] mem_ed[30] i2s_sck0 - - - 106 g2 doutr1[5] mem_ed[29] i2s_ws0 - - - 197 g3 doutr1[4] mem_ed[28] i2s_sdi0 - - - 280 g4 doutr1[3] mem_ed[27] i2s_sdo0 - - - 6 f1 doutr1[2] mem_ed[26] - gpio_pd[12] - - 105 f2 doutg1[7] mem_ed[25] - gpio_pd[11] - - 196 f3 doutg1[6] mem_ed[24] - gpio_pd[10] - - 279 f4 doutg1[5] mem_ed[23] - gpio_pd[9] - - 5 e1 doutg1[4] mem_ed[22] - gpio_pd[8] - - 104 e2 doutg1[3] mem_ed[21] - gpio_pd[7] - - 195 e3 doutg1[2] mem_ed[20] - gpio_pd[6] - - 278 e4 doutb1[7] mem_ed[19] - - doutr0[1] - 4 d1 doutb1[6] mem_ed[18] - - doutr0[0] - 103 d2 doutb1[5] mem_ed[17] - - doutg0[1] - 194 d3 doutb1[4] mem_ed[16] - - doutg0[0] - 277 d4 doutb1[3] mem_xwr[3] - - doutb0[1] - 3 c1 doutb1[2] mem_xwr[2] - - doutb0[0] - 283 k4 de1 xdack[7] - - - xdack[7] 282 j4 hsync1 dreq[6] - - - dreq[6] 199 j3 vsync1 xdack[6] - - - xdack[6] 108 j2 gv1 dreq[7] - - - dreq[7] pin multiplex group #1 mode setting this mode is set with external pin, mpx_mode_1[1:0]. table 1-4 mode setting of pin multiplex group #1 mpx_mode_1[1] pin mpx_mode_1[0] pin pin multiplex group #1 mode "l" "l" mode 0 "l" "h" mode 1 "h" "l" mode 2 "h" "h" mode 0
1-13 MB86R01 lsi product specifications fujitsu semiconductor confidential outline pin multiplex group #2 (setting register: pin mpx select.mpx_mode_2 [2:0]) table 1-5 pin function of pi n multiplex group #2 by mode mode0 mode1 mode2 mode3 mode4 pin no. jedec pin related to cap0/1 pin related to pwm pin related to i2s2 pin related to cap1 (nrgb666) pin related to gpio pin related to can pin related to i2s1/2 pin related to medialb pin related to gpio pin related to can pin related to i2s1 pin related to medialb pin related to spi pin related to gpio pin related to can pin related to i2s1/2 pin related to medialb 208 v3 vin1[7] - - ri1[7] gpio_pd[5] - - - gpio_pd[5] - - - - gpio_pd[5] - - - 19 w1 vin1[6] - - ri1[6] gpio_pd[4] - - - gpio_pd[4] - - - - gpio_pd[4] - - - 118 w2 vin1[5] - - ri1[5] - can_tx0 - - - can_tx0 - - - - can_tx0 - - 209 w3 vin1[4] - - ri1[4] - can_rx0 - - - can_rx0 - - - - can_rx0 - - 292 w4 vin1[3] - - ri1[3] - can_tx1 - - - can_tx1 - - - - can_tx1 - - 119 y2 vin1[2] - - ri1[2] - can_rx1 - - - can_rx1 - - - - can_rx1 - - 210 y3 vin1[1] - - gi1[7] - - i2s_sck1 - - - i2s_sck1 - - - - i2s_sck1 - 293 y4 vin1[0] - - gi1[6] - - i2s_ws1 - - - i2s_ws1 - - - - i2s_ws1 - 211 aa3 vinvsync1 - - vinvsync1 - - i2s_eclk1 - - - i2s_eclk1 - - - - i2s_eclk1 - 294 aa4 vinhsync1 - - vinhsync1 - - i2s_sdi1 - - - i2s_sdi1 - - - - i2s_sdi1 - 22 ab1 vinfid1 - - vinfid1 - - i2s_sdo1 - - - i2s_sdo1 - - - - i2s_sdo1 - 202 m3 vinvsync0 - - gi1[5] - - - mlb_data - - - mlb_data - - - - mlb_data 203 n3 vinhsync0 - - gi1[4] - - - mlb_sig - - - mlb_sig - - - - mlb_sig 112 n2 vinfid0 - - gi1[3] - - - mlb_clk - - - mlb_clk - - - - mlb_clk 123 ad2 - pwm_o0 - gi1[2] gpio_pd[3] - - - gpio_pd[3] - - - - gpio_pd[3] - - - 122 ac2 - pwm_o1 - bi1[7] gpio_pd[2] - - - gpio_pd[2] - - - - gpio_pd[2] - - - 121 ab2 - - i2s_sdo2 bi1[6] - - i2s_sdo2 - - - - - spi_do gpio_pd[1] - - - 24 ad1 - - i2s_eclk2 bi1[5] - - i2s_eclk2 - - - - - reserved (input/output) gpio_pd[0] - - - 23 ac1 - - i2s_sck2 bi1[4] - - i2s_sck2 - - - - - spi_sck - - i2s_sck2 - 295 ab4 - - i2s_ws2 bi1[3] - - i2s_ws2 - - - - - spi_ss - - i2s_ws2 - 212 ab3 - - i2s_sdi2 bi1[2] - - i2s_sdi2 - - - - - spi_di - - i2s_sdi2 - pin multiplex group #2 mode setting this mode is set with mpx_mode_2 bit (bit 2-0) in the multiplex mode setting register (cmux_md.) table 1-6 mode setting of pin multiplex group #2 mpx_mode_2 (bit 2-0) of the cmux_md register pin multiplex group #2 mode 000 mode 0 001 mode 1 010 mode 2 011 mode 3 100 mode 4 101 ? 110 reserved 111 (initial value)
1-14 MB86R01 lsi product specifications fujitsu semiconductor confidential outline pin multiplex group #3 (setting pin: usb_mode) table 1-7 pin function of pi n multiplex group #3 by mode mode 0 mode 1 pin no. jedec pin related to usb 2.0 host pin related to usb 2.0 function 114 r2 usb_fsdp usb_fsdp 115 t2 usb_fsdm usb_fsdm 15 r1 usb_hsdp usb_hsdp 16 t1 usb_hsdm usb_hsdm 18 v1 usb_cryck48 usb_cryck48 230 ad19 usb_prtpwr usb_prtpwr pin multiplex group #3 mode setting this mode is set with external pin, usb_mode. table 1-8 mode setting of pin multiplex group #3 usb_mode pin pin multiplex group #3 mode "l" mode 0 "h" mode 1
1-15 MB86R01 lsi product specifications fujitsu semiconductor confidential outline pin multiplex group #4 (setting register: pin_mpx_select.mpx_mode_4 [1:0]) table 1-9 pin function of pi n multiplex group #4 by mode mode 0 mode 1 pin no. jedec pin related to ide pin related to i2s1 pin related to can pin related to gpio pin related to pwm unused pin (input/output) 29 af4 ide_xdreset - - - - reserved (output) 28 af3 ide_xiocs16 i2s_sdi1 - - - - 125 ae3 ide_xdasp i2s_ws1 - - - - 215 ad4 ide_ddmarq i2s_eclk1 - - - - 296 ac4 ide_dintrq i2s_sdo1 - - - - 214 ad3 ide_xcblid i2s_sck1 - - - - 297 ac5 ide_dd[15] - can_tx0 - - - 216 ad5 ide_dd[14] - can_rx0 - - - 127 ae5 ide_dd[13] - can_tx1 - - - 30 af5 ide_dd[12] - can_rx1 - - - 298 ac6 ide_dd[11] - - gpio_pd[23] - - 217 ad6 ide_dd[10] - - gpio_pd[22] - - 128 ae6 ide_dd[9] - - gpio_pd[21] - - 31 af6 ide_dd[8] - - gpio_pd[20] - - 299 ac7 ide_dd[7] - - gpio_pd[19] - - 218 ad7 ide_dd[6] - - gpio_pd[18] - - 129 ae7 ide_dd[5] - - gpio_pd[17] - - 32 af7 ide_dd[4] - - gpio_pd[16] - - 300 ac8 ide_dd[3] - - gpio_pd[15] - - 219 ad8 ide_dd[2] - - gpio_pd[14] - - 130 ae8 ide_dd[1] - - gpio_pd[13] - - 33 af8 ide_dd[0] - - - - reserved (input/output) 213 ac3 ide_diordy - - - - reserved (input) 301 ac9 ide_da[2] - - - - reserved (output) 220 ad9 ide_da[1] - - - pwm_o1 - 131 ae9 ide_da[0] - - - pwm_o0 - 35 af10 ide_xdcs[1] - - - - reserved (output) 132 ae10 ide_xdcs[0] - - - - reserved (output) 221 ad10 ide_xdior - - - - reserved (output) 302 ac10 ide_xdiow - - - - reserved (output) 34 af9 ide_csel - - - - reserved (output) 126 ae4 ide_xddmac k - - - - reserved (output) pin multiplex group #4 mode setting this mode is set with mpx_mode_4 bit (bit 5-4) in the multiplex mode setting register (cmux_md.) table 1-10 mode setting of pin multiplex group #4 mpx_mode_4 (bit 5-4) of the cmux_md register pin multiplex group #4 mode 00 mode 0 01 mode 1 10 reserved 11 (initial value)
1-16 MB86R01 lsi product specifications fujitsu semiconductor confidential outline pin multiplex group #5 (setting pin: mpx_mode_5 [1:0]) table 1-11 pin function of pin multiplex group #5 by mode mode 0 mode 1 mode 2 pin no. jedec pin related to etm pin related to uart3/4/5 pin related to uart3/4 pin related to pwm 270 c10 traceclk uart_sin3 uart_sin3 - 185 b10 tracectl uart_sout3 uart_sout3 - 92 a10 tracedata[3] uart_sin4 uart_sin4 - 346 d11 tracedata[2] uart_sout4 uart_sout4 - 269 c11 tracedata[1] uart_sin5 - pwm_o1 184 b11 tracedata[0] uart_sout5 - pwm_o0 pin multiplex group #5 mode setting this mode is set with external pin, mpx_mode_5[1:0]. table 1-12 mode setting of pin multiplex group #5 mpx_mode_5[1] pin mpx_mode_5[0] pin pin multiplex group #5 mode "l" "l" mode 0 "l" "h" mode 1 "h" "l" mode 2 "h" "h" mode 0
1-17 MB86R01 lsi product specifications fujitsu semiconductor confidential outline 1.6.2. pin function format pin function list is shown in the following format. pin name i/o polarity analog /digital type status of pin after reset description meaning of item and sign pin name name of external pin. i/o input/output signal's distinction based on this lsi. ? i: pin that can be used as input ? o: pin that can be used as output ? io: pin that can be used as input and output (interactive pin) polarity active polarity of external pin's input/output signals ? p: "h" active pin (positive logic) ? n: "l" active pin (negative logic) ? pn: "h" and "l" active pins analog/digital signal type of external pin ? a: analog signal ? d: digital signal type input/output circuit type of external pin. ? clk: ? pod: pseudo open drain ? pu: pull up ? pd: pull down ? st: schmitt type ? tri: tri-state pin status after reset pin status after external pin reset ? h: "h" level ? l: "l" level ? hiz: high impedance ? x: "h" level or "l" level ? a: clock output description outline of external pin function
1-18 MB86R01 lsi product specifications fujitsu semiconductor confidential outline 1.6.3. external bus interface related pin table 1-13 external bus int erface related pin's function pin name i/o polarity analog /digital type status of pin after reset description mem_xcs[4] o n d - h chip select 4 mem_xcs[2] o n d - h chip select 2 mem_xcs[0] o n d - h chip select 0 mem_xrd o n d - h read strobe mem_xwr[3:2] o n d - h write strobe mem_xwr[3] mem_ed[31:24], mem_xwr[2] mem_ed[23:16] (optional pin) mem_xwr[1:0] o n d - h write strobe mem_xwr[1] mem_ed[15:8] mem_xwr[0] mem_ed[7:0] mem_rdy i p d - - ready input for slow device mem_ea[24:1] o - d - l address bus mem_ed[31:16] io - d - hiz bi-directional data bus (optional pin) mem_ed[15:0] io - d - hiz bi-directional data bus dreq[7:6] i - d - - external dma request xdack[7:6] o p d - l external dma acknowledge 1.6.4. ide66 related pin table 1-14 ide66 related pin function pin name i/o polarity analog /digital type status of pin after reset description ide_xdreset o n d - h ide reset ide_dd[15:0] io - d pd l ide device data ide_xdcs[1:0] o n d - h ide chip select ide_da[2:0] o p d - l ide device address ide_xdior o n d - h ide device i/o read ide_xdiow o n d - h ide device i/o write ide_diordy i p d - - ide i/o channel ready ide_ddmarq i p d - - ide device dma request ide_xddmack o n d - h ide device dma acknowledge ide_csel o p d - l ide cable select ide_xiocs16 i n d - - ide 16 bit i/o ide_xdasp i n d pd - ide device active ide_dintrq i p d pd - ide interrupt ide_xcblid i n d pd - ide cable id
1-19 MB86R01 lsi product specifications fujitsu semiconductor confidential outline 1.6.5. sd memory controller related pin table 1-15 sd memory controller related pin's function pin name i/o polarity analog /digital type status of pin after reset description sd_clk o n d - l media clock sd_cmd io - d - hiz media command sd_dat[3:0] io - d - hiz media data sd_wp i p d - - media write protection sd_xmcd i n d - - media card detection 1.6.6. usb 2.0 host/function related pin table 1-16 usb 2.0 host/function related pin's function pin name i/o polarity analog /digital type status of pin after reset description usb_fsdp io - a - - d+ for fs usb_fsdm io - a - - d- for fs usb_hsdp io - a - - d+ for hs usb_hsdm io - a - - d- for hs usb_cryck48 i - d clk - clock used for usb communication usb_prtpwr o - d - l usb port power control usb_ext12k o - a - - external resistance pin this should be connected to usb_avsb through 12k resistance. usb_avsp i - a - - pll ground usb_avsb i - a - - reference voltage ground usb_avdp i - a - - pll power supply usb_avdb i - a - - reference voltage power supply usb_avsf1 i - a - - driver/receiver ground 1 usb_avdf1 i - a - - driver/receiver power supply 1 usb_avsf2 i - a - - driver/receiver ground 2 usb_avdf2 i - a - - driver/receiver power supply 2 1.6.7. external interrupt controller related pin table 1-17 external interrupt controller related pin's function pin name i/o polarity analog /digital type status of pin after reset description int_a[3:0] i pn d - - asynchronous external interrupt requests
1-20 MB86R01 lsi product specifications fujitsu semiconductor confidential outline 1.6.8. uart related pin table 1-18 uart re lated pin's function pin name i/o polarity analog /digital type status of pin after reset explanation uart_sin0 i p d - - input data signal uart_sout0 o p d - h output data signal uart_xcts0 i n d - - clear to send uart_xrts0 o n d - h request to send uart_sin1 i p d - - input data signal uart_sout1 o p d - h output data signal uart_sin2 i p d - - input data signal uart_sout2 o p d - h output data signal uart_sin3 i p d - - input data signal (optional) uart_sout3 o p d - h output data signal (optional) uart_sin4 i p d - - input data signal (optional) uart_sout4 o p d - h output data signal (optional) uart_sin5 i p d - - input data signal (optional) uart_sout5 o p d - h output data signal (optional) 1.6.9. can related pin table 1-19 can related pin's function pin name i/o polarity analog /digital type status of pin after reset explanation can_tx0 o - d pd h transmission (optional) can_rx0 i - d pd - reception (optional) can_tx1 o - d pd h transmission (optional) can_rx1 i - d pd - reception (optional)
1-21 MB86R01 lsi product specifications fujitsu semiconductor confidential outline 1.6.10. i2s related pin table 1-20 i2s related pin's function pin name i/o polarity analog /digital type status of pin after reset explanation i2s_eclk0 i - d - - external clock (optional) i2s_sck0 io - d - hiz clock (optional) i2s_ws0 io pn d - hiz sync (optional) i2s_sdi0 i p d - - input data signal (optional) i2s_sdo0 o p d - hiz output data signal (optional) i2s_eclk1 i - d - - external clock (optional) i2s_sck1 io - d pd l clock (optional) i2s_ws1 io pn d pd l sync(optional) i2s_sdi1 i p d - - input data signal (optional) i2s_sdo1 o p d pd l output data signal (optional) i2s_eclk2 i - d pd - external clock (optional) i2s_sck2 io - d pd l clock (optional) i2s_ws2 io pn d pd l sync (optional) i2s_sdi2 i p d - - input data signal (optional) i2s_sdo2 o p d pd l output data signal (optional) 1.6.11. i 2 c related pin table 1-21 i 2 c related pin's function pin name i/o polarity analog /digital type status of pin after reset explanation i2c_scl0 io - d pod hiz i2c clock i2c_sda0 io - d pod hiz i2c data i2c_scl1 io - d pod hiz i2c clock i2c_sda1 io - d pod hiz i2c data 1.6.12. spi related pin table 1-22 spi related pin's function pin name i/o polarity analog /digital type status of pin after reset explanation spi_do o p d pd l serial data output (optional) spi_di i p d - - serial data input (optional) spi_sck o - d pd l serial clock (optional) spi_ss o pn d pd l slave select (optional)
1-22 MB86R01 lsi product specifications fujitsu semiconductor confidential outline 1.6.13. pwm related pin table 1-23 pwmrelated pin's function pin name i/o polarity analog /digital type status of pin after reset explanation pwm_o0 o - d pd (*1) l pwm out 0 (optional) pwm_o1 o - d pd (*1) l pwm out 1 (optional) *1: only pwm pin of the pin multiplex group #2 is with pull-down resistance 1.6.14. a/d converter related pin table 1-24 a/d converte r related pin's function pin name i/o polarity analog /digital type status of pin after reset explanation ad_vin0 i - a - - a/d analog input ad_vrh0 i - a - - reference voltage "h" input ad_vrl0 i - a - - refere nce voltage "l" input ad_avd i - a - - analog power supply ad_vr0 o - a - - reference output ad_vin1 i - a - - a/d analog input ad_vrh1 i - a - - reference voltage "h" input ad_vrl1 i - a - - refere nce voltage "l" input ad_avs i - a - - analog ground ad_vr1 o - a - - reference output
1-23 MB86R01 lsi product specifications fujitsu semiconductor confidential outline 1.6.15. ddr2 related pin table 1-25 ddr2 related pin's function pin name i/o polarity analog /digital type status of pin after reset explanation ma[13:0] o p d - h address mba[1:0] o p d - h bank address mdq[31:0] io p d - h data (*5) mdm[3:0] o p d - hiz data mask (*6) mdqsp[3:0] io p d - hi z data strobe (*5) mdqsn[3:0] io n d - hi z data strobe (*5) mckp o p d clk l clock output mckn o n d clk h clock output mcke o p d - l clock enable mcs o n d - l chip select mras o n d - h row address strobe mcas o n d - h column address strobe mwe o n d - h write enable ddrvde i - a - - sstl_18 1.8v power supply vref1 i - a - - reference voltage input (ddrvde/2) vref0 i - a - - reference voltage input (ddrvde/2) ocd i - a - - off chip driver reference voltage input (*1) odt i - a - - on-die terminati on reference voltage input (*2) odtcont o p d - l on-die termination control (*3) mcke_start i p d - - set a state of mcke in reset 0: low (*4) 1: high (reserved) ddrtype i p d - - pull up pin to vdde via high resistance *1: pull up the pin to ddrvde (1.8v power supply), via 200 resistance. *2: pcb impedance z = 100 or 50 : pull up pin to ddrvde (1.8v power supply), via 180 resistance. pcb impedance z = 150 or 75 : pull up pin to ddrvde (1.8v power supply), via 240 resistance. *3: it connects it with the odt pin of ddr2sdram. *4: pull down pin to v ss, via high resistance. *5: this is process of unused pin at 16 bit mode . pull down the pin to vss via high resistance. unused pins at 16 bi t mode are as follows: "mdq[31:16], mdqsp[3:2], mdqsn[3:2]" *6: this is process of mdm[3:2] at 16 bit mode. be sure to open this pin.
1-24 MB86R01 lsi product specifications fujitsu semiconductor confidential outline 1.6.16. display related pin table 1-26 display related pin's function pin name i/o polarity analog /digital type status of pin after reset explanation hsync0 io - d - hiz video output interface horizontal sync output horizontal sync input in external sync mode vsync0 io - d - hiz video output interface vertical sync output vertical sync input in external sync mode gv0 o - d - l video output interface graphics/video switch dclkin0 i - d clk - video output interface dot clock input dclko0 o - d clk x video outpu t interface dot clock output de0 o - d - x de/csync doutr0[7:2] o - d - x digita l rgb output0 datar[7:2] doutr0[1:0] o - d - x digital rgb output0 datar[1:0] (optional) doutg0[7:2] o - d - x digita l rgb output0 datag[7:2] doutg0[1:0] o - d - x digital rgb output0 datag[1:0] (optional) doutb0[7:2] o - d - x digita l rgb output0 datab[7:2] doutb0[1:0] o - d - x digital rgb output0 datab[1:0] (optional) hsync1 io - d - hiz video output interface horizontal sync output horizontal sync input in external sync mode vsync1 io - d - hiz video output interface vertical sync output vertical sync input in external sync mode gv1 o - d - l video output interface graphics/video switch dclkin1 i - d clk - video output interface dot clock input dclko1 o - d clk x video outpu t interface dot clock output de1 o - d - x de/csync doutr1[7:2] o - d - x digita l rgb output1 datar[7:2] doutg1[7:2] o - d - x digita l rgb output1 datag[7:2] doutb1[7:2] o - d - x digita l rgb output1 datab[7:2]
1-25 MB86R01 lsi product specifications fujitsu semiconductor confidential outline 1.6.17. video capture related pin table 1-27 video capture related pin's function pin name i/o polarity analog /digital type status of pin after reset description vin0[7:0] i - d - - video capture data[7:0] vinvsync0 i - d pd - video capture vertical sync input vinhsync0 i - d pd - video capture horizontal sync input vinfid0 i - d - - video input fi eld identification signal 0 in odd field cclk0 i - d clk - video capture input clock vin1[7:0] i - d pd - video capture data[7:0] vinvsync1 i - d - - video capture vertical sync input vinhsync1 i - d - - video capture horizontal sync input vinfid1 i - d pd - video input fi eld identification signal 0 in odd field cclk1 i - d clk - video capture input clock ri1[7:2] i - d pd - nrgb666 capture datar[7:2] (optional) gi1[7:2] i - d pd (*1) - nrgb666 capture datag[7:2] (optional) bi1[7:2] i - d pd (*2) - nrgb666 capture datab[7:2] (optional) *1: gi1[3] is not applicable. *2: bi1[2] is not applicable. 1.6.18. system related pin table 1-28 system related pin's function pin name i/o polarity analog /digital type status of pin after reset description clk i - d clk - input clock xrst i n d st - system reset cripm[3:0] i - d - - pllmode setting vinithi i - d - - boot high address pllbypass i - d - - pll bypass mode setting bigend i - d - - lsi endian setting low: little endian high: big endian pllvss i - a - - pll ground plltdtrst i - d - - test pin pull up the pin to vdde, via high resistance pllvdd i - a - - pll power supply
1-26 MB86R01 lsi product specifications fujitsu semiconductor confidential outline 1.6.19. jtag related pin table 1-29 jtag related pin's function pin name i/o polarity analog /digital type status of pin after reset description tck i - d st, pu - test clock xtrst i n d st, pu - test reset tms i n d pu - test mode tdi i - d pu - test data input tdo o - d tri hiz test data output 1.6.20. ice related pin table 1-30 ice related pin's function pin name i/o polarity analog /digital type status of pin after reset description rtck o - d - h return test clock xsrst io n d st, pu h system reset 1.6.21. multiplex setting related pin table 1-31 multiplex sett ing related pin's function pin name i/o polarity analog /digital type status of pin after reset description jtagsel i - d - - jtag selection 1: dft, 0: normal pull it down to vss, via high resistance mpx_mode_5[1:0] i - d - - external pin multiplex mode 5 mpx_mode_1[1:0] i - d - - external pin multiplex mode 1 usb_mode i - d - - usb selection 0: host, 1: function testmode[2:0] i - d - - test mode selection pin pull it down to vss, via high resistance vpd i - d - - test mode selection pin pull it down to vss, via high resistance
1-27 MB86R01 lsi product specifications fujitsu semiconductor confidential outline 1.6.22. etm related pin table 1-32 etm related pin's function pin name i/o polarity analog /digital type status of pin after reset description traceclk o - d - l exported clock for tracedata[3:0] and tracectl they are valid on bath edges of traceclk for max. integrity. tracectl o - d - h trace control signal used by the trace tool such as realview supplied by arm limited. tracedata[3:0] o - d - lhhh trace da ta used by the trace tool such as realview supplied by arm limited. 1.6.23. power supply related pin table 1-33 power supply related pin's function pin name i/o polarity analog /digital type status of pin after reset description vss i - d - - ground vdde i - d - - external pin power supply vddi i - d - - internal power supply 1.6.24. medialb related pin table 1-34 medialb related pin's function pin name i/o polarity analog /digital type status of pin after reset description mlb_data io p d pd hiz data (optional) (*1) mlb_sig io p d pd hiz control (optional) (*1) mlb_clk i - d clk - clock (optional) (*1) *1: medialb pin of this lsi uses 3.3[v] i/o; therefore, wh en connecting bus's voltage is not 3.3[v], level conversion at external side is needed. 1.6.25. gpio related pin table 1-35 gpio related pin's function pin name i/o polarity analog /digital type status of pin after reset description gpio_pd[23:0] io - d pd (*1) hiz general purpose i/o port (optional) *1: gpio_pd[12:6] is not applicable.
1-28 MB86R01 lsi product specifications fujitsu semiconductor confidential outline 1.6.26. unused pin proceed following proces ses for unused pin. table 1-36 MB86R01 unused pin's process pin no. jedec pin name process 3 c1 doutb1[2], mem_xwr[2], doutb0[0] 4 d1 doutb1[6], mem_ed[18], doutr0[0] pull up to vdde or pull down to vss through high resistance. 5 e1 doutg1[4], mem_ed[22], gpio_pd[8] 6 f1 doutr1[2], mem_ed[26], gpio_pd[12] 7 g1 dclkin1 9 j1 dclko1 keep the pin open. 10 k1 vin0[5] pull up to vdde or pull down to vss through high resistance. 11 l1 vin0[1] 12 m1 cclk0 14 p1 usb_avsp connect to vss. 15 r1 usb_hsdp pull down to vss through 10k ? resistance. 16 t1 usb_hsdm 17 u1 usb_avsf2 connect to vss. 18 v1 usb_cryck48 pull up to vdde or pull down to vss through high resistance. 19 w1 vin1[6], ri1[6], gpio_pd[4] keep the pin open. 21 aa1 cclk1 pull up to vdde or pull down to vss through high resistance. 22 ab1 vinfid1, i2s_sdo1 keep the pin open. 23 ac1 i2s_sck2, bi1[4], spi_sck 24 ad1 i2s_eclk2, bi1[5], reserved (input/output), gpio_pd[0] 28 af3 ide_xiocs16, i2s_sdi1 pull up to vdde or pull down to vss through high resistance. 29 af4 ide_xdreset, reserved (output) keep the pin open. 30 af5 ide_dd[12], can_rx1 31 af6 ide_dd[8], gpio_pd[20] 32 af7 ide_dd[4], gpio_pd[16] 33 af8 ide_dd[0], reserved (input/output) 34 af9 ide_csel, reserved (output) 35 af10 ide_xdcs[1], reserved (output) 36 af11 mpx_mode_5[1] pull up to vdde or pull down to vss through high resistance. 38 af13 ad_avd connect to vss. 39 af14 ad_avs 40 af15 uart_sout0 keep the pin open. 41 af16 uart_sin0 pull up to vdde or pull down to vss through high resistance. 42 af17 uart_sin1 43 af18 sd_dat[0] 44 af19 sd_wp
1-29 MB86R01 lsi product specifications fujitsu semiconductor confidential outline pin no. jedec pin name process 45 af20 i2c_scl1 pull up to vdde or pull down to vss through high resistance. 46 af21 i2c_sda1 47 af22 int_a[0] 48 af23 ma[8] keep the pin open. 49 af24 ma[12] 52 ae26 ma[7] 53 ad26 ma[3] 54 ac26 ma[1] 55 ab26 mba[1] 57 y26 mdqsn[0] pull down to vss through high resistance. 58 w26 mdqsp[0] 60 u26 mdqsn[1] 61 t26 mdqsp[1] 63 p26 mckn keep the pin open. 64 n26 mckp 66 l26 mdqsn[2] pull down to vss through high resistance. 67 k26 mdqsp[2] 69 h26 mdqsn[3] 70 g26 mdqsp[3] 72 e26 mem_ed[3] pull up to vdde or pull down to vss through high resistance. 73 d26 mem_ed[7] 74 c26 mem_ed[11] 78 a24 mem_ea[1] 79 a23 mem_ea[4] 80 a22 mem_ea[8] 81 a21 mem_ea[12] 82 a20 mem_ea[16] 83 a19 mem_ea[20] 85 a17 mem_xrd 88 a14 tdo keep the pin open. 92 a10 tracedata[3], uart_sin4 pull up to vdde or pull down to vss through high resistance. 94 a8 doutb0[4] keep the pin open. 95 a7 doutg0[2] 96 a6 doutg0[6] 97 a5 dclkin0 pull up to vdde or pull down to vss through high resistance. 99 a3 dclko0 keep the pin open. 101 b2 de0 102 c2 gv0 103 d2 doutb1[5], mem_ed[17], doutg0[1] pull up to vdde or pull down to vss through high resistance. 104 e2 doutg1[3], mem_ed[21], gpio_pd[7] 105 f2 doutg1[7], mem_ed[25], gpio_pd[11]
1-30 MB86R01 lsi product specifications fujitsu semiconductor confidential outline pin no. jedec pin name process 106 g2 doutr1[5], mem_ed[29], i2s_ws0 pull up to vdde or pull down to vss through high resistance. 108 j2 gv1, dreq[7] 109 k2 vin0[6] 110 l2 vin0[2] 112 n2 vinfid0, gi1[3], mlb_clk 113 p2 usb_avdp connect to vddi. 114 r2 usb_fsdp 115 t2 usb_fsdm pull down to vss through 10k ? resistance. 116 u2 usb_avsf2 connect to vss. 117 v2 usb_mode pull up to vdde or pull down to vss through high resistance. 118 w2 vin1[5], ri1[5], can_tx0 keep the pin open. 119 y2 vin1[2], ri1[2], can_rx1 121 ab2 i2s_sdo2, bi1[6], spi_do, gpio_pd[1] 122 ac2 pwm_o1, bi1[7], gpio_pd[2] 123 ad2 pwm_o0, gi1[2], gpio_pd[3] 125 ae3 ide_xdasp, i2s_ws1 126 ae4 ide_xddmack, reserved (output) 127 ae5 ide_dd[13], can_tx1 128 ae6 ide_dd[9], gpio_pd[21] 129 ae7 ide_dd[5], gpio_pd[17] 130 ae8 ide_dd[1], gpio_pd[13] 131 ae9 ide_da[0], pwm_o0 132 ae10 ide_xdcs[0], reserved (output) 133 ae11 mpx_mode_5[0] pull up to vdde or pull down to vss through high resistance. 135 ae13 ad_vrh0 connect to vss. 136 ae14 ad_vrh1 137 ae15 uart_xrts0 keep the pin open. 138 ae16 uart_xcts0 pull up to vdde or pull down to vss through high resistance. 139 ae17 uart_sout1 keep the pin open. 140 ae18 sd_dat[1] pull up to vdde or pull down to vss through high resistance. 141 ae19 sd_xmcd 142 ae20 i2c_scl0 143 ae21 int_a[3] 144 ae22 mcke_start pull down to vss through high resistance. 145 ae23 ma[13] keep the pin open. 146 ae24 ma[4] 147 ae25 ma[11] 148 ad25 ma[5] 149 ac25 ma[10] 150 ab25 mba[0] 151 aa25 mcke
1-31 MB86R01 lsi product specifications fujitsu semiconductor confidential outline pin no. jedec pin name process 152 y25 mdq[2] pull down to vss through high resistance. 153 w25 mdq[0] 154 v25 vref0 connect to ddr vde/2[v]reference voltage. 155 u25 mdq[13] pull down to vss through high resistance. 156 t25 mdq[8] 157 r25 mdq[15] 160 m25 mdq[21] 161 l25 mdq[16] 162 k25 vref1 connect to ddr vde/2[v]reference voltage. 163 j25 mdq[29] pull down to vss through high resistance. 164 h25 mdq[24] 165 g25 mdq[31] 166 f25 mem_ed[0] 167 e25 mem_ed[4] pull up to vdde or pull down to vss through high resistance. 168 d25 mem_ed[8] 169 c25 mem_ed[12] 170 b25 mem_ed[14] 171 b24 mem_ed[15] 172 b23 mem_ea[3] 173 b22 mem_ea[7] 174 b21 mem_ea[11] 175 b20 mem_ea[15] 176 b19 mem_ea[19] 177 b18 mem_ea[23] 178 b17 mem_xwr[1] 179 b16 mem_xcs[4] 183 b12 tms 184 b11 tracedata[0], uart_sout5, pwm_o0 185 b10 tracectl, uart_sout3 keep the pin open. 187 b8 doutb0[5] 188 b7 doutg0[3] 189 b6 doutg0[7] 190 b5 doutr0[4] 192 b3 hsync0 193 c3 vsync0 pull up to vdde or pull down to vss through high resistance. 194 d3 doutb1[4], mem_ed[16], doutg0[0] 195 e3 doutg1[2], mem_ed[20], gpio_pd[6] 196 f3 doutg1[6], mem_ed[24], gpio_pd[10] 197 g3 doutr1[4], mem_ed[28], i2s_sdi0 198 h3 doutr1[7], mem_ed[31], i2s_eclk0 199 j3 vsync1, xdack[6] 200 k3 vin0[7] 201 l3 vin0[3]
1-32 MB86R01 lsi product specifications fujitsu semiconductor confidential outline pin no. jedec pin name process 202 m3 vinvsync0, gi1[5], mlb_data keep the pin open. 203 n3 vinhsync0, gi1[4], mlb_sig 204 p3 usb_avsf1 connect to vss. 205 r3 usb_avdf1 connect to vdde. 206 t3 usb_avsf2 connect to vss. 207 u3 usb_avdf2 connect to vddi. 208 v3 vin1[7], ri1[7], gpio_pd[5] 209 w3 vin1[4], ri1[4], can_rx0 keep the pin open. 210 y3 vin1[1], gi1[7], i2s_sck1 211 aa3 vinvsync1, i2s_eclk1 pull up to vdde or pull down to vss through high resistance. 212 ab3 i2s_sdi2, bi1[2], spi_di 213 ac3 ide_diordy, reserved (input) 214 ad3 ide_xcblid, i2s_sck1 keep the pin open. 215 ad4 ide_ddmarq, i2s_eclk1 pull up to vdde or pull down to vss through high resistance. 216 ad5 ide_dd[14], can_rx0 keep the pin open. 217 ad6 ide_dd[10], gpio_pd[22] 218 ad7 ide_dd[6], gpio_pd[18] 219 ad8 ide_dd[2], gpio_pd[14] 220 ad9 ide_da[1], pwm_o1 221 ad10 ide_xdior, reserved (output) 222 ad11 mpx_mode_1[1] pull up to vdde or pull down to vss through high resistance. 224 ad13 ad_vin0 connect to vss. 225 ad14 ad_vin1 227 ad16 uart_sout2 keep the pin open. 228 ad17 sd_cmd pull up to vdde or pull down to vss through high resistance. 229 ad18 sd_dat[2] 230 ad19 usb_prtpwr keep the pin open. 231 ad20 i2c_sda0 pull up to vdde or pull down to vss through high resistance. 232 ad21 int_a[1] 234 ad23 ma[9] keep the pin open. 235 ad24 ma[6] 236 ac24 ma[2] 237 ab24 mwe 238 aa24 mras 239 y24 mdq[5] pull down to vss through high resistance. 240 w24 mdq[1] 241 v24 mdq[7] 242 u24 mdq[10] 243 t24 mdq[9] 244 r24 mdm[1] 247 m24 mdq[18]
1-33 MB86R01 lsi product specifications fujitsu semiconductor confidential outline pin no. jedec pin name process 248 l24 mdq[17] pull down to vss through high resistance. 249 k24 mdq[23] 250 j24 mdq[26] 251 h24 mdq[28] 252 g24 mdm[3] 253 f24 mem_ed[1] pull up to vdde or pull down to vss through high resistance. 254 e24 mem_ed[5] 255 d24 mem_ed[9] 256 c24 mem_ed[13] 257 c23 mem_ea[2] 258 c22 mem_ea[6] 259 c21 mem_ea[10] 260 c20 mem_ea[14] 261 c19 mem_ea[18] 262 c18 mem_ea[22] 263 c17 mem_xwr[0] 264 c16 mem_xcs[2] 267 c13 tck 269 c11 tracedata[1], uart_sin5, pwm_o1 270 c10 traceclk, uart_sin3 271 c9 doutb0[2] keep the pin open. 272 c8 doutb0[6] 273 c7 doutg0[4] 274 c6 doutr0[2] 275 c5 doutr0[5] 276 c4 doutr0[7] 277 d4 doutb1[3], mem_xwr[3], doutb0[1] pull up to vdde or pull down to vss through high resistance. 278 e4 doutb1[7], mem_ed[19], doutr0[1] 279 f4 doutg1[5], mem_ed[23], gpio_pd[9] 280 g4 doutr1[3], mem_ed[27], i2s_sdo0 281 h4 doutr1[6], mem_ed[30], i2s_sck0 282 j4 hsync1, dreq[6] 283 k4 de1, xdack[7] keep the pin open. 284 l4 vin0[4] pull up to vdde or pull down to vss through high resistance. 285 m4 vin0[0] 287 p4 usb_avsb 288 r4 usb_avsf2 289 t4 usb_avsf2 connect to vss. 292 w4 vin1[3], ri1[3], can_tx1 keep the pin open. 293 y4 vin1[0], gi1[6], i2s_ws1 294 aa4 vinhsync1, i2s_sdi1 pull up to vdde or pull down to vss through high resistance.
1-34 MB86R01 lsi product specifications fujitsu semiconductor confidential outline pin no. jedec pin name process 295 ab4 i2s_ws2, bi1[3], spi_ss keep the pin open. 296 ac4 ide_dintrq, i2s_sdo1 297 ac5 ide_dd[15], can_tx0 298 ac6 ide_dd[11], gpio_pd[23] 299 ac7 ide_dd[7], gpio_pd[19] keep the pin open. 300 ac8 ide_dd[3], gpio_pd[15] 301 ac9 ide_da[2], reserved (output) 302 ac10 ide_xdiow, reserved (output) 303 ac11 mpx_mode_1[0] pull up to vdde or pull down to vss through high resistance. 305 ac13 ad_vr0 connect to vss. 306 ac14 ad_vr1 308 ac16 uart_sin2 pull up to vdde or pull down to vss through high resistance. 309 ac17 sd_clk keep the pin open. 310 ac18 sd_dat[3] pull up to vdde or pull down to vss through high resistance. 312 ac20 int_a[2] 313 ac21 ddrtype pull up to vdde through high resistance. 314 ac22 odtcont keep the pin open. 315 ac23 ma[0] 316 ab23 mcs 317 aa23 mcas 318 y23 mdq[3] pull down to vss through high resistance. 319 w23 mdq[4] 320 v23 mdm[0] 321 u23 mdq[11] 322 t23 mdq[12] 323 r23 mdq[14] 324 p23 ocd keep the pin open. 325 n23 odt 326 m23 mdq[19] pull down to vss through high resistance. 327 l23 mdq[20] 328 k23 mdm[2] 329 j23 mdq[27] 330 h23 mdq[25] 331 g23 mdq[30] 332 f23 mem_ed[2] pull up to vdde or pull down to vss through high resistance. 333 e23 mem_ed[6] 334 d23 mem_ed[10] 335 d22 mem_ea[5] 336 d21 mem_ea[9] 337 d20 mem_ea[13] 338 d19 mem_ea[17]
1-35 MB86R01 lsi product specifications fujitsu semiconductor confidential outline pin no. jedec pin name process 339 d18 mem_ea[21] pull up to vdde or pull down to vss through high resistance. 340 d17 mem_ea[24] 341 d16 mem_xcs[0] 342 d15 mem_rdy 344 d13 tdi 346 d11 tracedata[2], uart_sout4 347 d10 rtck keep the pin open. 348 d9 doutb0[3] 349 d8 doutb0[7] 350 d7 doutg0[5] 351 d6 doutr0[3] 352 d5 doutr0[6] 362 p5 usb_avdb connect to vdde. 363 r5 usb_ext12k pull down to vss through 10k ? resistance. 364 t5 usb_avsf2 connect to vss. 378 ab13 ad_vrl0 379 ab14 ad_vrl1 391 v22 mdq[6] pull down to vss through high resistance. 398 l22 mdq[22]
1-36 MB86R01 lsi product specifications fujitsu semiconductor confidential outline 1.6.27. unused pin in the duplex case with pin multiplex function pwm, i2s1, and can pins may be duplicated and allocated to external pin depending on pin multiplex function's group combination. in this case, follow the procedure below. table 1-37 unused pin process in the duplex case with pin multiplex function pin no. jedec pin multiplex group: pin name process 122 ac2 pin multiplex group #2:pwm_o1 keep the pin open. 123 ad2 pin multiplex group #2:pwm_o0 220 ad9 pin multiplex group #4:pwm_o1 131 ae9 pin multiplex group #4:pwm_o0 269 c11 pin multiplex group #5:pwm_o1 pull down to vss through high resistance. 184 b11 pin multiplex group #5:pwm_o0 118 w2 pin multiplex group #2:can_tx0 keep the pin open. 292 w4 pin multiplex group #2:can_tx1 209 w3 pin multiplex group #2:can_rx0 119 y2 pin multiplex group #2:can_rx1 297 ac5 pin multiplex group #4:can_tx0 127 ae5 pin multiplex group #4:can_tx1 216 ad5 pin multiplex group #4:can_rx0 30 af5 pin multiplex group #4:can_rx1 210 y3 pin multiplex group #2:i2s_sck1 293 y4 pin multiplex group #2:i2s_ws1 211 aa3 pin multiplex group #2:i2s_eclk1 pull down to vss through high resistance. 294 aa4 pin multiplex group #2:i2s_sdi1 22 ab1 pin multiplex group #2:i2s_sdo1 keep the pin open. 28 af3 pin multiplex group #4:i2s_sdi1 pull down to vss through high resistance. 125 ae3 pin multiplex group #4:i2s_ws1 keep the pin open. 215 ad4 pin multiplex group #4:i2s_eclk1 pull down to vss through high resistance. 214 ad3 pin multiplex group #4:i2s_sck1 keep the pin open. 296 ac4 pin multiplex group #4:i2s_sdo1
2-1 MB86R01 lsi product specifications fujitsu semiconductor confidential system configuration 2. system configuration figure 2-1 shows system configuration for which this lsi is used to in-vehicle navigation. gdc gdc sd sd p-ata p-ata hdd arm926ej-s arm926ej-s sd card lcd #1 lcd #2 uart uart audio codec jtag jtag can can buttons 16550 ice adc adc usb host/function usb host/function usb host i/f usb adapter usb host can device i2s i2s i2c i2c spi spi gpio gpio speaker #1 speaker #2 microphone most medialb medialb audio codec MB86R01 ddr2 if ddr2 if ddr2sdram extbus extbus nor flash pwm pwm usb device bt656 dvd figure 2-1 sample of MB86R01 system configuration
3-1 memory map MB86R01 lsi product specifications fujitsu semiconductor confidential 3. memory map this chapter shows memory map and register map of MB86R01. 3.1. memory map of lsi figure 3-1 shows MB86R01 memory map. as the memory map indicates, boot operation jumps to user code, external boot rom (1000_0000 h ) through built-in boot rom (0000_0000 h. ) (setting 1000_0000 h to program counter (pc).) after the jump, set remap boot controller to remap internal boot rom area (0000_0000 h ~ 0000_8000 h ) to internal sram_0, then proceed interrupt v ector area setting and each register setting.
3-2 memory map MB86R01 lsi product specifications fujitsu semiconductor confidential ffff_ffff h fffe_a000 h fff8_3000 h ffff_ff00 h fffe _9000 h fff8_2000 h ffff_fe00 h fffe _8000 h fff8_1000 h ffff_8000 h fffe _7000 h fff8_0000 h ffff_0000 h fffe _6000 h fff7_1000 h fffe_a000 h fffe _5000 h fff7_0000 h fffa_0000 h fffe _4000 h fff6_1000 h fff8_3000 h fffe _2000 h fff6_0000 h ffee_0000 h fffe _1000 h fff5_8000 h fffe _0000 h fff5_7000 h f300_1000 h fffd_0000 h fff5_6000 h f1fc_0000 h fffc_8000 h fff5_5000 h fffc_0000 h fff5_4000 h fffb _1000 h fff5_3000 h fffb _0000 h fff5_2000 h fffa _1000 h fff5_1000 h fffa _0000 h fff5_0000 h fff4_5000 h fff4_4000 h fff4_3000 h graphics/memory related register f300_1000 h memory map fff4_2000 h 6000_0000 h f300_0000 h fff4_1000 h f200_0000 h fff4_0000 h 4000_0000 h f1ff_8000 h fff2_1000 h 3000_8000 h f1ff_0000 h fff2_0000 h 3000_0000 h f1fe_0000 h fff1_1000 h 1200_0000 h 1100_0000 h f1fd_a000 h fff1_0000 h 1000_0000 h external boot rom (cs4) 0200_0000 h external bus area f1fd_8000 h fff0_1000 h 0101_0000 h f1fd_2000 h fff0_0000 h 0100_8000 h f1fd_0000 h ffef_1000 h 0100_0000 h f1fc_0000 h ffef_0000 h 0000_8000 h ffee_1000 h 0000_0000 h 0000_0000 h ffee_0000 h after remap ( *1 ) memory (rom/ram) area ( *2 ) io (register by function module) area usb2.0 function dmac built-in boot rom (32kb, mirror) rbc built-in sram_0 (32kb, mirror) general-purpose peripheral register area (reserved) extended peripheral register area (reserved) ccpb_peu external ram area (ddr2 main memory) built-in sram_0 (32kb) (reserved) built-in boot rom (32kb, mirror) (reserved) irc0 mirror) (reserved) (reserved) usb2.0 host phycnt built-in sram_1 (32kb) (reserved) (reserved) (reserved) gdc register drawbase gdc register texturebase gdc register capture1base (reserved) memory map of extended graphics/memory related register area (reserved) memory map of lsi gpio irc0 crg_9 memory map of general-purpose peripheral register area peripheral register area gdc register geometrybase gdc register capture0base (reserved) built-in boot rom[ (32kb) gdc register display1base gdc register display0base gdc register hostbase external irc uart1 uart0 timer hdmac ccpb_ceu external bus i/f register irc1 (reserved) usb1.1 ohci host usb2.0 ehci host (reserved) (reserved) mlb (reserved) i2c_1 i2c_0 can_1 can_0 adc_1 adc_0 uart3 uart2 (reserved) uart5 (reserved) sd i/f uart4 ccnt pwm spi (reserved) i2s_0 ddr2 controller register (reserved) (reserved) i2s_2 (reserved) i2s_1 ( reserved) ide66 mirro mirro mirro (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*2) (*1) (*1) (*1) (*1) (*1) (*1) (*1) (*1) (*1) (*2) (*2) (*2) (*2) (*2) (*2) (*2) figure 3-1 memory map
3-3 memory map MB86R01 lsi product specifications fujitsu semiconductor confidential 3.2. register access basically, register in MB86R01 should be accessed by word length except some registers. table 3-1 shows valid access data length of each register. t able 3-1 valid access data length of register module register name valid data length dmacr byte (8 bit) address follows endian dmac dmaca, dmacb, dmacsa, dmacda word ( 32 bit)/half-word (16 bit)/byte (8 bit) uart rfr, tfr, dll word (32 bit)/byte (8 bit) when these registers are acce ssed by byte long, address follows endian gpio pdr0, pdr1, pdr2 word (32 bit) / byte (8 bit). when these registers are acce ssed by byte long, address follows endian ddr2 controller all registers of ddr2 controller half-word (16 bit) address follows endian sdmc all registers of sdmc byte (8 bit) address follows endian others all registers other than the above word (32 bit)
3-4 memory map MB86R01 lsi product specifications fujitsu semiconductor confidential 3.3. register map table 3-2 MB86R01 register map module name address register name explanation gdc f1fc_0000 h - f1ff_ffff h refer another document, MB86R01 gdc specifications for gdc register no module f200_0000 h - f2ff_ffff h reserved access prohibited ddr2 controller f300_0000 h dric initialization control register f300_0002 h dric1 initialization control command register 1 f300_0004 h dric2 initialization control command register 2 f300_0006 h drca address control register f300_0008 h drcm mode control register f300_000a h drcst1 timing setting register 1 f300_000c h drcst2 timing setting register 2 f300_000e h drcr refresh control register f300_0010 h - f300_001f h reserved access prohibited f300_0020 h drcf fifo control register f300_0022 h - f300_002f h reserved access prohibited f300_0030 h drasr axi operation setting register f300_0032 h - f300_004f h reserved access prohibited f300_0050 h drimsd if setting register f300_0052 h - f300_005f h reserved access prohibited f300_0060 h dros odt setting register f300_0062 h reserved access prohibited f300_0064 h dribsodt1 io odt1 setting register f300_0066 h dribsocd io ocd setting register f300_0068 h dribsocd2 io ocd2 setting register f300_006a h - f300_006f h reserved access prohibited f300_0070 h droaba odt bias auto adjustment register f300_0072 h - f300_0083 h reserved access prohibited f300_0084 h drobs odt bias selection register f300_0086 h - f300_008f h reserved access prohibited f300_0090 h drimr1 io monitor register 1 f300_0092 h drimr2 io monitor register 2 f300_0094 h drimr3 io monitor register 3 f300_0096 h drimr4 io monitor register 4 f300_0098 h droisr1 ocd impedanc e setting register 1 f300_009a h droisr2 ocd impedanc e setting register 2 f300_009c h - f300_0fff h reserved access prohibited no module f300_1000 h - ffed_ffff h reserved access prohibited i2s_0 ffee_0000 h i2s0rxfdat i2s_0 reception fifo data register ffee_0004 h i2s0txfdat i2s_0 transmission fifo data register
3-5 memory map MB86R01 lsi product specifications fujitsu semiconductor confidential module name address register name explanation i2s_0 ffee_0008 h i2s0cntreg i2s_0 control register ffee_000c h i2s0mcr0reg i2s_0 channel control register 0 ffee_0010 h i2s0mcr1reg i2s_0 channel control register 1 ffee_0014 h i2s0mcr2reg i2s_0 channel control register 2 ffee_0018 h i2s0oprreg i2s_0 operation control register ffee_001c h i2s0srst i2s_0 software reset register ffee_0020 h i2s0intcnt i2s_0 interrupt control register ffee_0024 h i2s0status i2s_0 status register ffee_0028 h i2s0dmaact i2s_0 dma start register ffee_002c h - ffee_0fff h reserved access prohibited no module ffee_1000 h - ffee_ffff h reserved access prohibited i2s_1 ffef_0000 h i2s1rxfdat i2s_1 reception fifo data register ffef_0004 h i2s1txfdat i2s_1 transmission fifo data register ffef_0008 h i2s1cntreg i2s_1 control register ffef_000c h i2s1mcr0reg i2s_1 channel control register 0 ffef_0010 h i2s1mcr1reg i2s_1 channel control register 1 ffef_0014 h i2s1mcr2reg i2s_1 channel control register 2 ffef_0018 h i2s1oprreg i2s_1 operation control register ffef_001c h i2s1srst i2s_1 software reset register ffef_0020 h i2s1intcnt i2s_1 interrupt control register ffef_0024 h i2s1status i2s_1 status register ffef_0028 h i2s1dmaact i2s_1 dma start register ffef_002c h - ffef_0fff h reserved access prohibited no module ffef_1000 h - ffef_ffff h reserved access prohibited i2s_2 fff0_0000 h i2s2rxfdat i2s_2 reception fifo data register fff0_0004 h i2s2txfdat i2s_2 transmission fifo data register fff0_0008 h i2s2cntreg i2s_2 control register fff0_000c h i2s2mcr0reg i2s_2 channel control register 0 fff0_0010 h i2s2mcr1reg i2s_2 channel control register 1 fff0_0014 h i2s2mcr2reg i2s_2 channel control register 2 fff0_0018 h i2s2oprreg i2s_2 operation control register fff0_001c h i2s2srst i2s_2 software reset register fff0_0020 h i2s2intcnt i2s_2 interrupt control register fff0_0024 h i2s2status i2s_2 status register fff0_0028 h i2s2dmaact i2s_2 dma start register fff0_002c h - fff0_0fff h reserved access prohibited no module fff0_1000 h - fff0_ffff h reserved access prohibited sdmc fff1_0000 h - fff1_0fff h another specifications another specifications no module fff1_1000 h - fff1_ffff h reserved access prohibited ide host controller fff2_0000 h cs0dat cs0 data register fff2_0004 h cs0er/cs0ft cs0 error/features register fff2_0008 h cs0sc cs0 sector count register fff2_000c h cs0sn cs0 sector number register
3-6 memory map MB86R01 lsi product specifications fujitsu semiconductor confidential module name address register name explanation ide host controller fff2_0010 h cs0cl cs0 cylinder low register fff2_0014 h cs0ch cs0 cylinder high register fff2_0018 h cs0dh cs0 device head register fff2_001c h cs0st/cs0cmd cs0 status/command register fff2_0020 h - fff2_0037 h reserved access prohibited fff2_0038 h cs1as/cs1dc cs1 alternate status/device control register fff2_003c h reserved access prohibited fff2_0040 h idedata data register fff2_0044 h - fff2_0047 h reserved access prohibited fff2_0048 h ideptcr pio timing control register fff2_004c h idepasr pio address setup register fff2_0050 h ideicmr ide command register fff2_0054 h ideistr ide status register fff2_0058 h ideiner interrupt enable register fff2_005c h ideinsr interrupt status register fff2_0060 h idefcmr fifo command register fff2_0064 h idefstr fifo status register fff2_0068 h idetfcr transmission fifo count register fff2_006c h reserved access prohibited fff2_0070 h iderfcr reception fifo count register fff2_0074 h - fff2_00c7 h reserved access prohibited fff2_00c8 h ideutcr udma timing control register fff2_00cd h - fff2_00cf h reserved access prohibited fff2_00d0 h ideucmr udma command register fff2_00d4 h ideustr udma status register fff2_00d8 h - fff2_014f h reserved access prohibited fff2_0150 h iderrcc rxfifo rest count compare value fff2_0154 h ideutc1 ultra dma timing control 1 fff2_0158 h ideutc2 ultra dma timing control 2 fff2_015c h ideutc3 ultra dma timing control 3 fff2_0160 h - fff2_01ff h reserved access prohibited fff2_0200 h idestatus dma status register fff2_0204 h ideint interrupt register fff2_0208 h ideintmsk interrupt mask register fff2_020c h idepioctl pio access control register fff2_0210 h idedmactl dma control register fff2_0214 h idedmatc dma transfer control register fff2_0218 h idedmasad dma source address register fff2_021c h idedmadad dma destination address register fff2_0220 h - fff2_0fff h reserved access prohibited no module fff2_1000 h - fff3_ffff h reserved access prohibited spi fff4_0000 h spicr spi control register fff4_0004 h spiscr spi slave control register
3-7 memory map MB86R01 lsi product specifications fujitsu semiconductor confidential module name address register name explanation spi fff4_0008 h spidr spi data register fff4_000c h spisr spi status register fff4_0010 h - fff4_0fff h reserved access prohibited pwm fff4_1000 h pwm0bcr pwm ch0 base clock register fff4_1004 h pwm0tpr pwm ch0 pul se width register fff4_1008 h pwm0pr pwm ch0 phase register fff4_100c h pwm0dr pwm ch0 duty register fff4_1010 h pwm0cr pwm ch0 status register fff4_1014 h pwm0sr pwm ch0 start register fff4_1018 h pwm0ccr pwm ch0 current count register fff4_101c h pwm0ir pwm ch0 interrupt register fff4_1020 h - fff4_10ff h reserved access prohibited fff4_1100 h pwm1bcr pwm ch1 base clock register fff4_1104 h pwm1tpr pwm ch1 pul se width register fff4_1108 h pwm1pr pwm ch1 phase register fff4_110c h pwm1dr pwm ch1 duty register fff4_1110 h pwm1cr pwm ch1 status register fff4_1114 h pwm1sr pwm ch1 start register fff4_1118 h pwm1ccr pwm ch1 current count register fff4_111c h pwm1ir pwm ch1 interrupt register fff4_1120 h - fff4_1fff h reserved access prohibited ccnt fff4_2000 h ccid chip id register fff4_2004 h csrst software reset register fff4_2008 h - fff4_200f h reserved access prohibited fff4_2010 h cist interrupt status register fff4_2014 h cistm interrupt status mask register fff4_2018 h cgpio_ist gpio interrupt status register fff4_201c h cgpio_istm gpio interrupt status mask register fff4_2020 h cgpio_ip gpio interrupt polarity setting register fff4_2024 h cgpio_im gpio interrupt mode setting register fff4_2028 h caxi_bw axi bus wait cycle setting register fff4_202c h caxi_ps axi priority setting register fff4_2030 h cmux_md multiplex mode setting register fff4_2024 h cex_pin_st external pin status register fff4_2038 h cmlb medialb setting register fff4_203c h reserved access prohibited fff4_2040 h cusb usb setting register fff4_2044 h - fff4_20e7 h reserved access prohibited fff4_20e8 h cbsc byte swap switching register fff4_20ec h cdcrc ddr2 controller reset control register fff4_20f0 h cmsr0 software reset register 0 for macro fff4_20f4 h cmsr1 software reset register 1 for macro fff4_20f8 h - fff4_2fff h reserved access prohibited uart4 fff4_3000 h urt4rfr transmission fifo regi ster (read only at dlab = 0) when it accesses rfr by byte long in the big endian mode, address becomes fff4_3003 h .
3-8 memory map MB86R01 lsi product specifications fujitsu semiconductor confidential module name address register name explanation uart4 fff4_3000 h urt4tfr transmission fifo regist er (write only at dlab = 0) when it accesses tfr by byte long in the big endian mode, address becomes fff4_3003 h . urt4dll dividing frequency value (lower byte at dlab = 1) when it accesses dll by byte long in the big endian mode, address becomes fff4_3003 h . urt4ier dlab = 0: inte rrupt enable register fff4_3004 h urt4dlm dlab = 1: dividing frequency value (upper byte) urt4iir interrupt id register (read only) fff4_3008 h urt4fcr fifo control register (write only) fff4_300c h urt4lcr line control register fff4_3010 h urt4mcr modem control register fff4_3014 h urt4lsr line status register fff4_3018 h urt4msr modem status register fff4_301c h - fff4_3fff h reserved access prohibited uart5 urt5rfr transmission fifo re gister (read only at dlab = 0) when it accesses rfr by byte long in the big endian mode, address becomes fff4_4003h. urt5tfr transmission fifo regist er (write only at dlab = 0) when it accesses tfr by byte long in the big endian mode, address becomes fff4_4003 h . fff4_4000 h urt5dll dividing frequency value (lower byte at dlab = 1) when it accesses dll by byte long in the big endian mode, address becomes fff4_4003 h . urt5ier dlab = 0: interrupt enable register. fff4_4004 h urt5dlm dlab = 1: dividing frequency value (upper byte) urt5iir interrupt id register (read only) fff4_4008 h urt5fcr fifo control register (write only) fff4_400c h urt5lcr line control register fff4_4010 h urt5mcr modem control register fff4_4014 h urt5lsr line status register fff4_4018 h urt5msr modem status register fff4_401c h - fff4_4fff h reserved access prohibited no module fff4_5000 h - fff4_ffff h reserved access prohibited uart2 fff5_0000 h urt2rfr transmission fifo regi ster (read only at dlab = 0) when it accesses rfr by byte long in the big endian mode, address becomes fff5_0003 h . urt2tfr transmission fifo regi ster (write only at dlab = 0) when it accesses tfr by byte long in the big endian mode, address becomes fff5_0003 h . urt2dll dividing frequency value (lower byte at dlab = 1) when it accesses dll by byte long in the big endian mode, address becomes fff5_0003 h . urt2ier dlab = 0: interrupt enable register. fff5_0004 h urt2dlm dlab = 1: dividing frequency value (upper byte) urt2iir interrupt id register (read only) fff5_0008 h urt2fcr fifo control register (write only) fff5_000c h urt2lcr line control register fff5_0010 h urt2mcr modem control register fff5_0014 h urt2lsr line status register fff5_0018 h urt2msr modem status register
3-9 memory map MB86R01 lsi product specifications fujitsu semiconductor confidential module name address register name explanation uart2 fff5_001c h - fff5_0fff h reserved access prohibited uart3 urt3rfr transmission fifo re gister (read only at dlab = 0) when it accesses rfr by byte long in the big endian mode, address becomes fff5_1003 h . urt3tfr transmission fifo regist er (write only at dlab = 0) when it accesses tfr by byte long in the big endian mode, address becomes fff5_1003 h . fff5_1000 h urt3dll dividing frequency value (lower byte at dlab = 1) when it accesses dll by byte long in the big endian mode, address becomes fff5_1003 h . urt3ier dlab = 0: interrupt enable register. fff5_1004 h urt3dlm dlab = 1: dividing frequency value (upper byte) urt3iir interrupt id register (read only) fff5_1008 h urt3fcr fifo control register (write only) fff5_100c h urt3lcr line control register fff5_1010 h urt3mcr modem control register fff5_1014 h urt3lsr line status register fff5_1018 h urt3msr modem status register fff5_101c h - fff5_1fff h reserved access prohibited adc_0 fff5_2000 h adc0data data register fff5_2004 h reserved access prohibited fff5_2008 h adc0xpd power down control register fff5_200c h reserved access prohibited fff5_2010 h adc0cksel clock selection register fff5_2014 h adc0status status register fff5_2018 h - fff5_2fff h reserved access prohibited adc_1 fff5_3000 h adc1data data register fff5_3004 h reserved access prohibited fff5_3008 h adc1xpd power down control register fff5_300c h reserved access prohibited fff5_3010 h adc1cksel clock selection register fff5_3014 h adc1status status register fff5_3018 h - fff5_3fff h reserved access prohibited can_0 fff5_4000 h - fff5_4fff h another specifications another specifications can_1 fff5_5000 h - fff5_5fff h another specifications another specifications i 2 c_0 fff5_6000 h i2c0bsr i2c bus status register ch0 fff5_6004 h i2c0bcr i2c bus control register ch0 fff5_6008 h i2c0ccr i2c clock control register ch0 fff5_600c h i2c0adr i2c address register ch0 fff5_6010 h i2c0dar i2c data register ch0 fff5_6014 h i2c0ecsr i2c extension cs register ch0 fff5_6018 h i2c0bcfr i2c bus clock frequency register ch0 fff5_601c h i2c0bc2r i2c bus control 2 registers ch0 fff5_6020 h - fff5_6fff h reserved access prohibited i 2 c_1 fff5_7000 h i2c1bsr i2c bus status register ch1 fff5_7004 h i2c1bcr i2c bus control register ch1
3-10 memory map MB86R01 lsi product specifications fujitsu semiconductor confidential module name address register name explanation i 2 c_1 fff5_7008 h i2c1ccr i2c clock control register ch1 fff5_700c h i2c1adr i2c address register ch1 fff5_7010 h i2c1dar i2c data register ch1 fff5_7014 h i2c1ecsr i2c extension cs register ch1 fff5_7018 h i2c1bcfr i2c bus clock frequency register ch1 fff5_701c h i2c1bc2r i2c bus control 2 registers ch1 fff5_7020 h - fff5_7fff h reserved access prohibited no module fff5_8000 h - fff5_ffff h reserved access prohibited medialb fff6_0000 h - fff6_0fff h another specifications another specifications no module fff6_1000 h - fff6_ffff h reserved access prohibited fff7_0000 h ufcpac usb function cpu access control register usb 2.0 function dmac fff7_0004 h ufdvc usb function device control register fff7_0008 h ufdvs usb function device status register fff7_000c h ufepic usb function endpoint interrupt control register fff7_0010 h ufepis usb function endpoint interrupt status register fff7_0014 h ufepdc usb function endpoint dma control register fff7_0018 h ufepds usb function endpoint dma status register fff7_001c h uftstamp usb function time stamp register fff7_0020 h ufeptcsel ufeptcsel register fff7_0024 h ufeptc1 usb function endpoint 1 terminal count register fff7_0028 h ufeptc2 usb function endpoint 2 terminal count register fff7_002c h - fff7_006c h reserved access prohibited fff7_0070 h ufeprs0 usb function endpoint 0 rx size register fff7_0074 h reserved access prohibited fff7_0078 h ufeprs1 usb function endpoint 1 rx size register fff7_007c h reserved access prohibited fff7_0080 h ufeprs2 usb function endpoint 2 rx size register fff7_0084 h reserved access prohibited fff7_0088 h ufeprs3 usb function endpoint 3 rx size register fff7_008c h - fff7_00ef h reserved access prohibited fff7_00f0 h ufcuscnt ufcuscnt register fff7_00f4 h ufcalb ufcalb register fff7_00f8 h ufeplpbk ufeplpbk register fff7_00fc h ufintfaltnum ufintfaltnum register fff7_0100 h ufepc0 usb function endpoint 0 control register fff7_0104 h ufeps0 usb function endpoint 0 status register fff7_0108 h ufepc1 usb function endpoint 1 control register fff7_010c h ufeps1 usb function endpoint 1 status register fff7_0110 h ufepc2 usb function endpoint 2 control register fff7_0114 h ufeps2 usb function endpoint 2 status register fff7_0118 h ufepc3 usb function endpoint 3 control register fff7_011c h ufeps3 usb function endpoint 3 status register fff7_0120 h - fff7_017f h reserved access prohibited fff7_0180 h ufepib0 usb function endpoint 0 in buffer register
3-11 memory map MB86R01 lsi product specifications fujitsu semiconductor confidential module name address register name explanation usb 2.0 function dmac fff7_0184 h ufepib1 usb function endpoint 1 in buffer register fff7_0188 h ufepib2 usb function endpoint 2 in buffer register fff7_018c h ufepib3 usb function endpoint 3 in buffer register fff7_0190 h - fff7_01bf h reserved access prohibited fff7_01c0 h ufepob0 usb function endpoint 0 out buffer register fff7_01c4 h ufepob1 usb function endpoint 1 out buffer register fff7_01c8 h ufepob2 usb function endpoint 2 out buffer register fff7_01cc h - fff7_01ff h reserved access prohibited fff7_0200 h - fff7_0213 h ufconfig ufconfig registers fff7_0214 h - fff7_0403 h reserved access prohibited fff7_0404 h ufepdc1 usb function endpoint 1 dma control/status register fff7_0408 h ufepdc2 usb function endpoint 2 dma control/status register fff7_040c h - fff7_0410 h reserved access prohibited fff7_0414 h ufepda1 usb function endpoint 1 dma address register fff7_0418 h ufepda2 usb function endpoint 2 dma address register fff7_041c h - fff7_0420 h reserved access prohibited fff7_0424 h ufepds1 usb function endpoint 1 dma size register fff7_0428 h ufepds2 usb function endpoint 2 dma size register fff7_042c h - fff7_0fff h reserved access prohibited no module fff7_1000 h - fff7_ffff h reserved access prohibited fff8_0000 h hccapbase capabi lity register usb 2.0 ehci host fff8_0004 h hcsparams structural parameter register fff8_0008 h hccparams capability parameter register fff8_000c h reserved access prohibited fff8_0010 h usbcmd usb command register fff8_0014 h usbsts usb status register fff8_0018 h usbintr usb interrupt enable register fff8_001c h frindex usb frame index register fff8_0020 h ctrldssegment 4g segm ent selector register fff8_0024 h periodiclistbase peri odic frame list base address register fff8_0028 h asnclistaddr asynchronous list address register fff8_002c h - fff8_004f h reserved access prohibited fff8_0050 h configflag configured flag register fff8_0054 h portsc_1 port status/control register fff8_0058 h - fff8_008f h reserved access prohibited fff8_0090 h insnreg00 programmable micro frame base value register fff8_0094 h insnreg01 programmable packet buffer out/in threshold register fff8_0098 h insnreg02 programmable pack et buffer depth register fff8_009c h insnreg03 break memory transfer register fff8_00a0 h insnreg04 debug register fff8_00a4 h insnreg05 utmi control status register
3-12 memory map MB86R01 lsi product specifications fujitsu semiconductor confidential module name address register name explanation usb 2.0 ehci host fff8_00a8 h - fff8_0fff h reserved access prohibited usb 2.0 ohci host fff8_1000 h hcrevision revision register fff8_1004 h hccontrol control register fff8_1008 h hccommandstatus comma nd/status register fff8_100c h hcinterruptstatus interrupt status register fff8_1010 h hcinterruptenable interrupt enable register fff8_1014 h hcinterruptdisable inte rrupt disable register fff8_1018 h hchcca hcca register fff8_101c h hcperiodcurrented peri od current ed register fff8_1020 h hccontrolheaded control head ed register fff8_1024 h hccontrolcurrented cont rol current ed register fff8_1028 h hcbulkheaded bulk head ed register fff8_102c h hcbulkcurrented bulk current ed register fff8_1030 h hcdonehead done head register fff8_1034 h hcfminterval frame interval register fff8_1038 h hcfmremaining frame remaining register fff8_103c h hcfmnumber frame number register fff8_1040 h hcperiodicstart peri odic start register fff8_1044 h hclsthreshold ls threshold register fff8_1048 h hcrhdescriptora root hub descriptor a register fff8_104c h hcrhdescriptorb root hub descriptor b register fff8_1050 h hcrhstatus root hub status register fff8_1054 h hcrhportstatus[1] root hub port status/control register 1 fff8_1058 h - fff8_1fff h reserved access prohibited fff8_2000 h linkmodesetting link m ode setting register usb 2.0 host phycnt fff8_2004 h phy mode setting1 phy m ode setting 1 register fff8_2008 h phy mode setting2 phy m ode setting 2 register fff8_200c h - fff8_2fff h reserved access prohibited no module fff8_3000 h - fff9_ffff h reserved access prohibited ccpb_peu fffa_0000 h - fffa_0fff h another specifications another specifications no module fffa_1000 h - fffa_ffff h reserved access prohibited fffb_0000 h ir1irqf irq flag register fffb_0004 h ir1irqm irq mask register interrupt controller 1 (irc1) fffb_0008 h ir1ilm interrupt level mask register fffb_000c h ir1icrmn icr monitoring register fffb_0010 h - fffb_0018 h reserved access prohibited fffb_001c h ir1tbr table base register fffb_0020 h ir1vct interrupt vector register fffb_0024 h - fffb_002c h reserved access prohibited fffb_0030 h ir1icr0 interrupt control register 00 fffb_0034 h ir1icr1 interrupt control register 01 fffb_0038 h ir1icr2 interrupt control register 02 fffb_003c h ir1icr3 interrupt control register 03
3-13 memory map MB86R01 lsi product specifications fujitsu semiconductor confidential module name address register name explanation interrupt controller 1 (irc1) fffb_0040 h ir1icr4 interrupt control register 04 fffb_0044 h ir1icr5 interrupt control register 05 fffb_0048 h ir1icr6 interrupt control register 06 fffb_004c h ir1icr7 interrupt control register 07 fffb_0050 h ir1icr8 interrupt control register 08 fffb_0054 h ir1icr9 interrupt control register 09 fffb_0058 h ir1icr10 interrupt control register 10 fffb_005c h ir1icr11 interrupt control register 11 fffb_0060 h ir1icr12 interrupt control register 12 fffb_0064 h ir1icr13 interrupt control register 13 fffb_0068 h ir1icr14 interrupt control register 14 fffb_006c h ir1icr15 interrupt control register 15 fffb_0070 h ir1icr16 interrupt control register 16 fffb_0074 h ir1icr17 interrupt control register 17 fffb_0078 h ir1icr18 interrupt control register 18 fffb_007c h ir1icr19 interrupt control register 19 fffb_0080 h ir1icr20 interrupt control register 20 fffb_0084 h ir1icr21 interrupt control register 21 fffb_0088 h ir1icr22 interrupt control register 22 fffb_008c h ir1icr23 interrupt control register 23 fffb_0090 h ir1icr24 interrupt control register 24 fffb_0094 h ir1icr25 interrupt control register 25 fffb_0098 h ir1icr26 interrupt control register 26 fffb_009c h ir1icr27 interrupt control register 27 fffb_00a0 h ir1icr28 interrupt control register 28 fffb_00a4 h ir1icr29 interrupt control register 29 fffb_00a8 h ir1icr30 interrupt control register 30 fffb_00ac h ir1icr31 interrupt control register 31 fffb_00b0 h - fffb_ffff h reserved access prohibited external bus interface (external bus i/f) fffc_0000 h mcfmode0 sram/flash-mode register 0 fffc_0004 h mcfmode1 sram/flash-mode register 1 (access prohibited) fffc_0008 h mcfmode2 sram/flash-mode register 2 fffc_000c h mcfmode3 sram/flash-mode register 3 (access prohibited) fffc_0010 h mcfmode4 sram/flash-mode register 4 fffc_0014 h mcfmode5 sram/flash-mode register 5 (access prohibited) fffc_0018 h mcfmode6 sram/flash-mode register 6 (access prohibited) fffc_001c h mcfmode7 sram/flash-mode register 7 (access prohibited) fffc_0020 h mcftim0 sram/flash timing register 0 fffc_0024 h mcftim1 sram/flash timing register 1 (access prohibited) fffc_0028 h mcftim2 sram/flash timing register 2 fffc_002c h mcftim3 sram/flash timing register 3 (access prohibited) fffc_0030 h mcftim4 sram/flash timing register 4 fffc_0034 h mcftim5 sram/flash timing register 5 (access prohibited) fffc_0038 h mcftim6 sram/flash timing register 6 (access prohibited) fffc_003c h mcftim7 sram/flash timing register 7 (access prohibited)
3-14 memory map MB86R01 lsi product specifications fujitsu semiconductor confidential module name address register name explanation external bus interface (external bus i/f) fffc_0040 h mcfarea0 sram/flash area register 0 fffc_0044 h mcfarea1 sram/flash area register 1 fffc_0048 h mcfarea2 sram/flash area register 2 fffc_004c h mcfarea3 sram/flash area register 3 fffc_0050 h mcfarea4 sram/flash area register 4 fffc_0054 h mcfarea5 sram/flash area register 5 fffc_0058 h mcfarea6 sram/flash area register 6 fffc_005c h mcfarea7 sram/flash area register 7 fffc_0060 h - fffc_01fc h reserved access prohibited fffc_0200 h mcerr memory controller error register fffc_0204 h - fffc_7fff h reserved access prohibited ccpb_ceu fffc_8000 h - fffc_ffff h another specifications another specifications dmac fffd_0000 h dmacr dmac configuration register fffd_0004 h - fffd_000f h reserved access prohibited fffd_0010 h dmaca0 dmac0 configuration a register fffd_0014 h dmacb0 dmac0 configuration b register fffd_0018 h dmacsa0 dmac0 source address register fffd_001c h dmacda0 dmac0 destination address register fffd_0020 h dmaca1 dmac1 configuration a register fffd_0024 h dmacb1 dmac1 configuration b register fffd_0028 h dmacsa1 dmac1 source address register fffd_002c h dmacda1 dmac1 destination address register fffd_0030 h dmaca2 dmac2 configuration a register fffd_0034 h dmacb2 dmac2 configuration b register fffd_0038 h dmacsa2 dmac2 source address register fffd_003c h dmacda2 dmac2 destination address register fffd_0040 h dmaca3 dmac3 configuration a register fffd_0044 h dmacb3 dmac3 configuration b register fffd_0048 h dmacsa3 dmac3 source address register fffd_004c h dmacda3 dmac3 destination address register fffd_0050 h dmaca4 dmac4 configuration a register fffd_0054 h dmacb4 dmac4 configuration b register fffd_0058 h dmacsa4 dmac4 source address register fffd_005c h dmacda4 dmac4 destination address register fffd_0060 h dmaca5 dmac5 configuration a register fffd_0064 h dmacb5 dmac5 configuration b register fffd_0068 h dmacsa5 dmac5 source address register fffd_006c h dmacda5 dmac5 destination address register fffd_0070 h dmaca6 dmac6 configuration a register fffd_0074 h dmacb6 dmac6 configuration b register fffd_0078 h dmacsa6 dmac6 source address register fffd_007c h dmacda6 dmac6 destination address register fffd_0080 h dmaca7 dmac7 configuration a register fffd_0084 h dmacb7 dmac7 configuration b register
3-15 memory map MB86R01 lsi product specifications fujitsu semiconductor confidential module name address register name explanation dmac fffd_0088 h dmacsa7 dmac7 source address register fffd_008c h dmacda7 dmac7 destination address register fffd_0090 h - fffd_ffff h reserved access prohibited timer fffe_0000 h tmr0ld timer 1 load value fffe_0004 h tmr0val timer 1 current value fffe_0008 h tmr0ctl timer 1 control register fffe_000c h tmr0ic timer 1 interrupt clear register fffe_0010 h tmr0ris timer 1 interrupt status fffe_0014 h tmr0mis interrupt status to which timer 1 masks fffe_0018 h tmr0bgl timer 1 background load value fffe_001c h reserved access prohibited fffe_0020 h tmr1ld timer 2 load value fffe_0024 h tmr1val timer 2 current value fffe_0028 h tmr1ctl timer 2 control registers fffe_002c h tmr1ic timer 2 interrupt clear register fffe_0030 h tmr1ris timer 2 interrupt status fffe_0034 h tmr1mis interrupt status to which timer 2 masks fffe_0038 h tmr1bgl timer 2 background load value fffe_003c h - fffe_0fff h reserved access prohibited uart0 fffe_1000 h urt0rfr reception fifo register (read only at dlab = 0) when it accesses rfr by byte long in the big endian mode, address becomes fffe_1003 h . urt0tfr transmission fifo regi ster (write only at dlab = 0) when it accesses tfr by byte long in the big endian mode, address becomes fffe_1003 h . urt0dll dividing frequency value (lower byte at dlab = 1) when it accesses dll by byte long in the big endian mode, address becomes fffe_1003 h . urt0ier dlab = 0: inte rrupt enable register fffe_1004 h urt0dlm dlab = 1: dividing frequency value (upper byte) urt0iir interrupt id register (read only) fffe_1008 h urt0fcr fifo control register (write only) fffe_100c h urt0lcr line control register fffe_1010 h urt0mcr modem control register fffe_1014 h urt0lsr line status register fffe_1018 h urt0msr modem status register fffe_101c h - fffe_1fff h reserved access prohibited uart1 fffe_2000 h urt1rfr transmission fifo regi ster (read only at dlab = 0) when it accesses rfr by byte long in the big endian mode, address becomes fffe_2003 h . urt1tfr transmission fifo regi ster (write only at dlab = 0) when it accesses tfr by byte long in the big endian mode, address becomes fffe_2003 h . urt1dll dividing frequency value (lower byte at dlab = 1) when it accesses dll by byte long in the big endian mode, address becomes fffe_2003 h . urt1ier dlab = 0: interrupt enable register. fffe_2004 h urt1dlm dlab = 1: dividing frequency value (upper byte) urt1iir interrupt id register (read only) fffe_2008 h urt1fcr fifo control register (write only)
3-16 memory map MB86R01 lsi product specifications fujitsu semiconductor confidential module name address register name explanation uart1 fffe_200c h urt1lcr line control register fffe_2010 h urt1mcr modem control register fffe_2014 h urt1lsr line status register fffe_2018 h urt1msr modem status register fffe_201c h - fffe_3fff h reserved access prohibited external interrupt controller (exirc) fffe_4000 h eienb external interrupt enable register fffe_4004 h eireq external interrupt request register fffe_4008 h eilvl external interrupt level register fffe_401c h - fffe_47ff h reserved access prohibited no module fffe_4800 h - fffe_5fff h reserved access prohibited remap boot controller (rbc) fffe_6000 h reserved access prohibited fffe_6004 h rbremap remap control register fffe_6008 h rbviha vinithi control register a fffe_600c h rbitra initram control register a fffe_6010 h - fffe_6fff h reserved access prohibited clock reset generator (crg) fffe_7000 h crpr pll control register fffe_7004 h reserved access prohibited fffe_7008 h crwr watchdog timer control register fffe_700c h crsr reset/standby control register fffe_7010 h crda clock division control register a fffe_7014 h crdb clock division control register b fffe_7018 h crha ahb(a) bus clock gate control register fffe_701c h crpa apb(a) bus clock gate control register fffe_7020 h crpb apb(b) bus clock gate control register fffe_7024 h crhb ahb(b) bus clock gate control register fffe_7028 h cram arm core clock ga te control register fffe_702c h - fffe_7fff h reserved access prohibited interrupt controller 0 (irc0) fffe_8000 h ir0irqf irq flag register fffe_8004 h ir0irqm irq mask register fffe_8008 h ir0ilm interrupt level mask register fffe_800c h ir0icrmn icr monitoring register fffe_8010 h reserved access prohibited fffe_8014 h ir0swir0 software interrupt control register 0 fffe_8018 h ir0swir1 software interrupt control register 1 fffe_801c h ir0tbr table base register fffe_8020 h ir0vct interrupt vector register fffe_8024 h reserved access prohibited fffe_8028 h reserved access prohibited fffe_802c h reserved access prohibited fffe_8030 h ir0icr0 interrupt control register 00 fffe_8034 h ir0icr1 interrupt control register 01
3-17 memory map MB86R01 lsi product specifications fujitsu semiconductor confidential module name address register name explanation interrupt controller 0 (irc0) fffe_8038 h ir0icr2 interrupt control register 02 fffe_803c h ir0icr3 interrupt control register 03 fffe_8040 h ir0icr4 interrupt control register 04 fffe_8044 h ir0icr5 interrupt control register 05 fffe_8048 h ir0icr6 interrupt control register 06 fffe_804c h ir0icr7 interrupt control register 07 fffe_8050 h ir0icr8 interrupt control register 08 fffe_8054 h ir0icr9 interrupt control register 09 fffe_8058 h ir0icr10 interrupt control register 10 fffe_805c h ir0icr11 interrupt control register 11 fffe_8060 h ir0icr12 interrupt control register 12 fffe_8064 h ir0icr13 interrupt control register 13 fffe_8068 h ir0icr14 interrupt control register 14 fffe_806c h ir0icr15 interrupt control register 15 fffe_8070 h ir0icr16 interrupt control register 16 fffe_8074 h ir0icr17 interrupt control register 17 fffe_8078 h ir0icr18 interrupt control register 18 fffe_807c h ir0icr19 interrupt control register 19 fffe_8080 h ir0icr20 interrupt control register 20 fffe_8084 h ir0icr21 interrupt control register 21 fffe_8088 h ir0icr22 interrupt control register 22 fffe_808c h ir0icr23 interrupt control register 23 fffe_8090 h ir0icr24 interrupt control register 24 fffe_8094 h ir0icr25 interrupt control register 25 fffe_8098 h ir0icr26 interrupt control register 26 fffe_809c h ir0icr27 interrupt control register 27 fffe_80a0 h ir0icr28 interrupt control register 28 fffe_80a4 h ir0icr29 interrupt control register 29 fffe_80a8 h ir0icr30 interrupt control register 30 fffe_80ac h ir0icr31 interrupt control register 31 fffe_80b0 h - fffe_8fff h reserved access prohibited gpio fffe_9000 h gpdr0 port data register 0 when it accesses pdr0 by byte long in the big endian mode, address becomes fffe_9003 h . fffe_9004 h gpdr1 port data register 1 when it accesses pdr1 by byte long in the big endian mode, address becomes fffe_9007 h . fffe_9008 h gpdr2 port data register 2 when it accesses pdr2 by byte long in the big endian mode, address becomes fffe_900b h . fffe_900c h reserved access prohibited fffe_9010 h gpddr0 data direction register 0 fffe_9014 h gpddr1 data direction register 1 fffe_9018 h gpddr2 data direction register 2 fffe_901c h - fffe_9fff h reserved access prohibited no module fffe_a000 h - fffe_ffff h reserved access prohibited ffff_0000 h - ffff_fdff h not register area for external area.
3-18 memory map MB86R01 lsi product specifications fujitsu semiconductor confidential module name address register name explanation interrupt controller 0 (mirror) (irc0 mirror) ffff_fe00 h ir0irqf irq flag register ffff_fe04 h ir0irqm irq mask register ffff_fe08 h ir0ilm interrupt level mask register ffff_fe0c h ir0icrmn icr monitoring register ffff_fe10 h reserved access prohibited ffff_fe14 h ir0dicr0 software interrupt control register 0 ffff_fe18 h ir0dicr1 software interrupt control register 1 ffff_fe1c h ir0tbr table base register ffff_fe20 h ir0vct interrupt vector register ffff_fe24 h - ffff_fe2f h reserved access prohibited ffff_fe30 h ir0icr0 interrupt control register 00 ffff_fe34 h ir0icr1 interrupt control register 01 ffff_fe38 h ir0icr2 interrupt control register 02 ffff_fe3c h ir0icr3 interrupt control register 03 ffff_fe40 h ir0icr4 interrupt control register 04 ffff_fe44 h ir0icr5 interrupt control register 05 ffff_fe48 h ir0icr6 interrupt control register 06 ffff_fe4c h ir0icr7 interrupt control register 07 ffff_fe50 h ir0icr8 interrupt control register 08 ffff_fe54 h ir0icr9 interrupt control register 09 ffff_fe58 h ir0icr10 interrupt control register 10 ffff_fe5c h ir0icr11 interrupt control register 11 ffff_fe60 h ir0icr12 interrupt control register 12 ffff_fe64 h ir0icr13 interrupt control register 13 ffff_fe68 h ir0icr14 interrupt control register 14 ffff_fe6c h ir0icr15 interrupt control register 15 ffff_fe70 h ir0icr16 interrupt control register 16 ffff_fe74 h ir0icr17 interrupt control register 17 ffff_fe78 h ir0icr18 interrupt control register 18 ffff_fe7c h ir0icr19 interrupt control register 19 ffff_fe80 h ir0icr20 interrupt control register 20 ffff_fe84 h ir0icr21 interrupt control register 21 ffff_fe88 h ir0icr22 interrupt control register 22 ffff_fe8c h ir0icr23 interrupt control register 23 ffff_fe90 h ir0icr24 interrupt control register 24 ffff_fe94 h ir0icr25 interrupt control register 25 ffff_fe98 h ir0icr26 interrupt control register 26 ffff_fe9c h ir0icr27 interrupt control register 27 ffff_fea0 h ir0icr28 interrupt control register 28 ffff_fea4 h ir0icr29 interrupt control register 29 ffff_fea8 h ir0icr30 interrupt control register 30 ffff_feac h ir0icr31 interrupt control register 31 ffff_feb0 h - ffff_feff h reserved access prohibited
4-1 MB86R01 lsi product specifications fujitsu semiconductor confidential cpu (arm926ej-s core part) 4. cpu (arm926ej-s core part) this chapter describes cpu (arm926ej-s core part) of MB86R01. 4.1. outline arm926ej-s core part chiefly includes functional blocks such as arm926ej-s, tcm (tightly coupled memory), and etm9cs single. 4.2. feature arm926ej-s core part has following features: ? five stage pipeline (fetch, decode, execution, memory, and write) ? harvard architecture ? 16kb instruction cache/16kb data cache ? 16kb instruction tcm (itc m)/16kb data tcm (dtcm) ? java acceleration (jazelle technology) ? coprocessor interface ? supported mmu (memory management unit) ? built-in etm9cs single for real-time trace ? corresponded to big endian and little endian 4.3. block diagram figure 4-1 shows arm926ej-s core part?s block diagram. arm926ej-s core block 16kb instruction tcm 16kb data tcm jtag sync. circuit a rm926ej-s etm9cs single configuration 16kb data cache 16kb instruction cache jtag signal ahb i/f trace signal (4bit tracepkt) instruction ahb data ahb figure 4-1 block diagram of arm926ej-s core part
4-2 MB86R01 lsi product specifications fujitsu semiconductor confidential cpu (arm926ej-s core part) 4.4. arm926ej-s and etm setting arm926ej-s cache size, both instruction and data, is set to 16kb as well as itcm and dtcm. MB86R01 has etm9cs single for r eal-time trace, and 4 bits are su pported for tracepkt port of etm9cs single. refer to related material of arm ltd. such as sh own below for detailed specification of arm926ej-s and etm9cs single. arm926ej-s arm926ej-s product overview ? arm926ej-s (r0p4/r0p5) technical reference manual (ddi0198d) ? arm9ej-s revision r1p2 technical reference manual ddi0222b) ? arm926ej-s product overview (dvi0035b) they are found in the following url. http://infocenter.arm.com/help/index.jsp etm9cs single ? coresight etm9 r0p0 technical reference manual (ddi0315a) ? etm9 revision r2p2 technical reference manual (ddi0157f) ? embedded trace macrocell architect ure specification (ihi0014n) ? coresight system design guide (dgi0012a) they are found in the following url. http://www.arm.com/documentation/trace_debug/index.html
5-1 MB86R01 lsi product specifications fujitsu semiconductor confidential clock reset generator (crg) 5. clock reset generator (crg) this chapter describes function and operation of clock reset generator (crg.) 5.1. outline crg controls clock/reset of arm926ej-s, ahb, and apb module. 5.2. feature crg has the following features: ? clock generator ? both pll clock and external input cl ock (pll by-pass mode) are operable ? pll control a- control of pll oscillation and stop b- control of pll oscillation stabilization waiting time ? clock gear control ? clock frequency of arm core, axi, ahb, and apb can be changed respectively ? supply/stop control of clock to arm core, axi, ahb, and apb module ? reset generator ? generation of internal reset from external reset ? generation of software reset ? input/output control of xsrst signal for jtag ice ? generation of xtrst (tap controller?s reset) signal ? others ? watchdog timer function ? corresponding to stop mode which halts all clocks of MB86R01
5-2 MB86R01 lsi product specifications fujitsu semiconductor confidential clock reset generator (crg) 5.3. block diagram figure 5-1 shows block diagram of clock reset generator (crg.) crg_9 clock divider (cr_dvs) clock divider (cr_dvs) apb bus apb i/f (cr_reg) ahb control watch of arm grant states (cr_gnt) time base timer (cr_tbt) controller of clock dividing (cr_div) clock generator (cr_mck) pll macro watchdog timer (cr_wdt) clock divider (cr_dvs) reset generator (cr_rst) clock arm/axi/ ahb/apb clock arm/axi/ ahb/apb reset figure 5-1 block diagram of clock reset generator (crg) table 5-1 shows function of the block included in crg. table 5-1 individu al block function block function cr_rst generation of reset signal cr_mck pll control/bypass cr_gnt arm?s grant status watch cr_div generation of clock frequency dividing and clock enable signal cr_dvs selection of clock frequency divi ding and non clock frequency dividing cr_tbt count of following items: ? pll oscillation stabilization waiting time ? pll reset?s pulse width ? watchdog timer?s clear timing ? software reset?s pulse width cr_reg control register cr_wdt watchdog timer
5-3 MB86R01 lsi product specifications fujitsu semiconductor confidential clock reset generator (crg) 5.4. register this section describes crg register. 5.4.1. register list table 5-2 shows list of crg register. table 5-2 crg register list address base offset register name abbreviation explanation + 00 h pll control register crpr to control pll + 04 h (reserved) ? reserved area, access prohibited + 08 h watchdog timer control register crwr to control watchdog timer + 0c h reset/standby control register crsr to control reset/standby + 10 h clock frequency dividing control register a crda to control clock divider + 14 h clock frequency dividing control register b crdb to control clock divider + 18 h ahb(a) bus clock gate control register crha to control clock gate of ahb(a) bus + 1c h apb(a) bus clock gate control register crpa to control clock gate of apb(a) bus + 20 h apb(b) bus clock gate control register crpb to control clock gate of apb(b) bus + 24 h ahb(b) bus clock gate control register crhb to control clock gate of ahb(b) bus + 28 h arm core clock gate control register cram to control clock gate of arm core fffe_7000 h + 2c h ? + ff h (reserved) ? reserved area, access prohibited
5-4 MB86R01 lsi product specifications fujitsu semiconductor confidential clock reset generator (crg) description format of register following format is used for description of register?s each bit in " 5.4.2 pll control register (crpr)" to " 5.4.11 arm core clock gate control register (cram)". address base address + offset bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r/w initial value bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r/w initial value meaning of item and sign address address (base address + offset address) of the register bit bit number of the register name bit field name of the register r/w attribution of read/write of each bit field ? r0:read value is always "0" ? r1: read value is always "1" ? w0: write value is always "0", and write access of "1" is ignored ? w1: write value is always "1", and write access of "0" is ignored ? r: read ? w: write initial value each bit field?s value after reset ? 0: value is "0" ? 1: value is "1" ? x: value is undefined
5-5 MB86R01 lsi product specifications fujitsu semiconductor confidential clock reset generator (crg) 5.4.2. pll control register (crpr) this register controls pll. address fffe_7000 h + 00 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) pllrdy *1 luwmode[1:0] pllmode[4:0] r/w r0 r0 r0 r0 r0 r0 r0 r r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 *2 1 0 1 *3 1 *3 1 *3 1 *3 1 *3 *1: pllbypass *2: this follows external pin, pllbypass *3: this changes according to setting value of external pin, cripm[3:0] and pllbypass bit field no. name description 31-16 ? unused bits. write access is ignored, and read va lue of these bits is undefined. 15-9 (reserved) reserved bits. write access is ignored, and read valu e of these bits are always "0". 8 pllrdy pllready monitoring this bit monitors internal signal, pllready with external pin clk clock. the pllready signal shows overflow of the va lue selected at lummode[1:0] bit by the timer which calculates pll oscillation stabilization waiting time. 0 pllready signal is "low" (initial value) 1 pllready signal is "high" write access to this bit is ignored. note: pllrdy=1 does not guarantee that pll is locked and clock supply is ready. 7 pllbypass pll bypass mode this bit bypasses pll. 0 pll clock is used. 1 pll is bypassed note: do not change pllbypass bit and pllmode [4:0] at the same time since clock switch of both external pin clk and pll clocks need s to be changed. if they are changed at the same time, crg detects pll oscillati on frequency change and state becomes pll oscillation stabilization waiting before pll bypass mode. reference: the initial value of this bit is sett able with setting external pin, pllbypass.
5-6 MB86R01 lsi product specifications fujitsu semiconductor confidential clock reset generator (crg) bit field no. name description 6-5 luwmode[1:0] pll lockup waiting mode these bits are used to set pll oscillation stabilization wait time. 00 t clk (2 n0 - 2 m + 1) 01 t clk (2 n1 - 2 m + 1) 10 t clk (2 n2 - 2 m + 1) (initial value) 11 t clk (2 n3 - 2 m + 1) t clk : cycle time of external pin clk n0 = 11 n1 = 12 n2 = 13 n3 = 14 m = 8 the wait time depends on clk cycle time and pl l lock-up time, moreover it does not need to be changed from the initial value. 4-0 pllmode[4:0] pl l oscillation mode these bits are used to set pll oscillation mode. initial value of pllmode[4:0] bit changes according to the setting of external pin, cripm[3:0]. initial value of these bits is pllmode[4:0] = {pllbypass, cripm[3], cripm[2], cripm[1], cripm[0].} 00000 f cclk = f clk 24.5 (49 1/2) 00001 f cclk = f clk 23 (46 1/2) 00010 f cclk = f clk 18.5 (37 1/2) 00011 f cclk = f clk 10 (20 1/2) 00100 f cclk = f clk 23.5 (47 1/2) 00101 f cclk = f clk 22 (44 1/2) 00110 f cclk = f clk 18 (36 1/2) 00111 f cclk = f clk 9.5 (19 1/2) 01000 f cclk = f clk 19.5 (39 1/2) 01001 f cclk = f clk 19 (38 1/2) 01010 f cclk = f clk 15 (30 1/2) 01011 f cclk = f clk 7.5 (15 1/2) 11111 pll stops others reserved (setting prohibited) f cclk : clock frequency of cclk f clk : clock frequency of external pin clk note: do not change pllmode[4:0 ] when pllbypass bit is 0.
5-7 MB86R01 lsi product specifications fujitsu semiconductor confidential clock reset generator (crg) 5.4.3. watchdog timer control register (crwr) this register controls watchdog timer. address fffe_7000 h + 08 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) erst (reserved) tbr wdrst wdtset/ wdtclr wdtmode[1:0] r/w r0 r0 r0 r0 r0 r0 r0 r0 r/w0 r0 r0/w0* r/w1 r/w0 r/w1 r/w r/w initial value 0 0 0 0 0 0 0 0 1 0 0 0 x 0 0 0 *: do not set "1" to bit 5 bit field no. name description 31-16 ? unused bits. write access is ignored, and read va lue of these bits is undefined. 15-8 (reserved) reserved bits. write access is ignored, and read valu e of these bits are always "0". 7 erst internal reset of erstn monitoring this bit monitors internal signal of erstn. 0 erstn bit is cleared 1 it is indicated that external reset (xrst) is asserted (initial value) the initial value of this bit is set to 1 by fa lling edge of erstn, and writing "1" is ignored. this bit is set by erstn. 6 (reserved) reserved bits. write access is ignored, and read va lue of this bit is always "0". 5 (reserved) reserved bit, always write 0. read value of this bit is always "0". 4 tbr time based timer reset request this bit resets the time based timer, and its rese t signal is asserted duri ng 1 cycle of apb clock. 0 time based timer is not reset (initial value) 1 time based timer is reset writing 0 is ignored. the time base timer is always counted. therefore, reset the time base timer before starting the watchdog timer. 3 wdrst watchdog reset monitoring this bit monitors watchdog reset. 0 watchdog reset is not asserted 1 watchdog reset is asserted the initial value of this bit is und efined, and writing 1 is ignored. when watchdog is reset, this bit is set to "1".
5-8 MB86R01 lsi product specifications fujitsu semiconductor confidential clock reset generator (crg) bit field no. name description 2 wdtset /wdtclr setting and clear of watchdog timer this bit sets and clears watchdog timer which star ts count at writing "1" and clears at writing "1" from the second time. 0 the watchdog timer is not set (initial value) 1 first time: the watchdog timer starts second time and later: the watchdog timer is cleared writing 0 is ignored. 1-0 wdtmode[1:0] these bits set timing to clear watchdog timer. watchdog reset occurs at following periods when "1" is written to wdtset/wdtclr bits at the end. 00 t clk 2 n0 ~ t clk 2 (n0 + 1) (initial value) 01 t clk 2 n1 ~ t clk 2 (n1 + 1) 10 t clk 2 n2 ~ t clk 2 (n2 + 1) 11 t clk 2 n3 ~ t clk 2 (n3 + 1) t clk : cycle time of external pin clk n0 = 9 n1 = 12 n2 = 14 n3 = 16 select the bit that corresponds to the system.
5-9 MB86R01 lsi product specifications fujitsu semiconductor confidential clock reset generator (crg) 5.4.4. reset/standby control register (crsr) this register controls reset and standby. address fffe_7000 h + 0c h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) stopen (reserved) reserved srst swrst swrst req swrm ode r/w r0 r0 r0 r0 r0 r0 r0 r0 r/w r0 r0 r/w0 r/w0 r/w0 r/w1 r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 bit field no. name description 31-16 ? unused bits. write access is ignored, and read va lue of these bits is undefined. 15-8 (reserved) reserved bits. write access is ignored, and read valu e of these bits are always "0". 7 stopen stop mode enable this bit stops all bus clock operations in the standby mode. 0 bus clock operation in the standby mode does not stop (initial value) 1 all bus clock operations in the standby mode are stopped note: when changing state to stop mode, write "1" to pllbypass bit of crpr. 6-5 (reserved) reserved bits. write access is ignored, and read valu e of these bits are always "0". 4 (reserved) reserved bit. always write "0" to write access. 3 srst nsrst monitoring this bit monitors nsrs t reset from ice. 0 nsrst is not asserted 1 nsrst is asserted initial value of this bit is undefin ed, and writing "0" is ignored. when nsrst occurs, this bit is set to "1". 2 swrst software reset monitoring this bit monitors software reset. 0 software reset is not asserted 1 software reset is asserted initial value of this bit is undef ined, and writing "0" is ignored. when software reset occurs, this bit is set to "1". 1 swrstreq software reset request this bit asserts so ftware reset. 0 software reset is not requested (initial value) 1 software reset is requested writing 0 is ignored, and this bit is cleared with reset signal.
5-10 MB86R01 lsi product specifications fujitsu semiconductor confidential clock reset generator (crg) bit field no. name description 0 swrmode pulse width mode of software reset this bit sets pulse width of software reset. 0 t clk (2 n0+3 ) + t cclk 7 (initial value) 1 t clk (2 n1+3 ) + t cclk 7 t xclk : cycle time of external pin clk t cclk : cycle time of internal signal cclk n0 = 7 n1 = 12 pulse width of software reset depends on the clk cycle time and internal operation frequency setting. sele ct the bit that corresponds to the system.
5-11 MB86R01 lsi product specifications fujitsu semiconductor confidential clock reset generator (crg) 5.4.5. clock divider control register a (crda) this register controls clock divider. address fffe_7000 h + 10 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) armbdm[2:0] armadm[2:0] pbdm[2:0] padm[2:0] hadm[2:0] r/w r0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 1 0 0 0 0 1 1 0 1 1 0 1 0 bit field no. name description 31-16 ? unused bits. write access is ignored, and read va lue of these bits is undefined. 15 (reserved) reserved bit. write access is ignored, and read valu e of these bits are always "0". 14-12 armbdm[2:0] armbclk frequency dividing mode these bits set frequency divi ding ratio of armbclk. 000 f armbclk = f cclk (1/1) 001 f armbclk = f cclk (1/2) (initial value) 010 f armbclk = f cclk (1/4) 011 f armbclk = f cclk (1/8) 100 f armbclk = f cclk (1/16) others reserved (setting prohibited) f armbclk : clock frequency of armbclk f cclk : clock frequency of cclk 11-9 armadm[2:0] armaclk dividing mode these bits set frequency divi ding ratio of armaclk. 000 f armaclk = f cclk (1/1) (initial value) 001 f armaclk = f cclk (1/2) 010 f armaclk = f cclk (1/4) 011 f armaclk = f cclk (1/8) 100 f armaclk = f cclk (1/16) others reserved (setting prohibited) f armbclk : clock frequency of armaclk f cclk : clock frequency of cclk
5-12 MB86R01 lsi product specifications fujitsu semiconductor confidential clock reset generator (crg) bit field no. name description 8-6 pbdm[2:0] pbclk frequency dividing mode these bits set frequency di viding ratio of pbclk. 000 f pbclk = f cclk (1/1) 001 f pbclk = f cclk (1/2) 010 f pbclk = f cclk (1/4) 011 f pbclk = f cclk (1/8) (initial value) 100 f pbclk = f cclk (1/16) others reserved (setting prohibited) f pbclk : clock frequency of pbclk f cclk : clock frequency of cclk 5-3 padm[2:0] paclk frequency dividing mode these bits set frequency di viding ratio of paclk. 000 f paclk = f cclk (1/1) 001 f paclk = f cclk (1/2) 010 f paclk = f cclk (1/4) 011 f paclk = f cclk (1/8) (initial value) 100 f paclk = f cclk (1/16) others reserved (setting prohibited) f paclk : clock frequency of paclk f cclk : clock frequency of cclk 2-0 hadm[2:0] haclk fre quency dividing mode these bits set frequency dividing ratio of haclk. 000 f haclk = f cclk (1/1) 001 f haclk = f cclk (1/2) 010 f haclk = f cclk (1/4) (initial value) 011 f haclk = f cclk (1/8) 100 f haclk = f cclk (1/16) others reserved (setting prohibited) f haclk : clock frequency of haclk f cclk : clock frequency of cclk note: armaclk must not be slower than haclk; moreover, haclk must not be slower than paclk. f armclk >= f haclk >= f paclk
5-13 MB86R01 lsi product specifications fujitsu semiconductor confidential clock reset generator (crg) 5.4.6. clock divider control register b (crdb) this register controls clock divider. address fffe_7000 h + 14 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) hbdm[2:0] r/w r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 bit field no. name description 31-16 ? unused bits. write access is ignored, and read va lue of these bits is undefined. 15-3 (reserved) reserved bits. write access is ignored, and read valu e of these bits are always "0". 2-0 hbdm[2:0] hbclk frequency dividing mode these bits set frequency di viding ratio of hbclk. hbdm[2:0] frequency dividing ratio of hbclk 000 f hbclk = f cclk (1/1) 001 f hbclk = f cclk (1/2) (initial value) 010 f hbclk = f cclk (1/4) 011 f hbclk = f cclk (1/8) 100 f hbclk = f cclk (1/16) others reserved (setting prohibited) f hbclk : clock frequency of hbclk f cclk : clock frequency of cclk
5-14 MB86R01 lsi product specifications fujitsu semiconductor confidential clock reset generator (crg) 5.4.7. ahb (a) bus clock gate control register (crha) this register controls clock gate of ahb (a) bus. address fffe_7000 h + 18 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hagate[15:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 bit field no. name description 31-16 ? unused bits. write access is ignored, and read va lue of these bits is undefined. 15-0 hagate[15:0] haclk clock gate control these bits control haclk clock gate. hagate[n] description 0 haclkn stops 1 haclkn does not stop (initial value) haclk0: ahb1, ahb2, apbbrg0, apbbrg1, apbbrg2 haclk1: external bus i/f, ccpb haclk2: sram haclk3: hdmac haclk4: (reserved) haclk5: boot rom haclk6: (reserved) haclk7: i2s_0, i2s_1, i2s_2 haclk8: usb 2.0 func, dmac haclk9: usb 2.0 host haclk10: sd i/f haclk11: ide66, ide66 dmac haclk12: mlb haclk13: gdc haclk14: (reserved) haclk15: ddr2 controller
5-15 MB86R01 lsi product specifications fujitsu semiconductor confidential clock reset generator (crg) 5.4.8. apb (a) bus clock gate control register (crpa) this register controls clock gate of apb (a) bus. address fffe_7000 h + 1c h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pagate[15:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 bit field no. name description 31-16 ? unused bits. write access is ignored, and read va lue of these bits is undefined. 15-0 pagate[15:0] paclk clock gate control these bits control paclk clock gate. pagate[n] description 0 paclkn stops 1 paclkn does not stop (initial value) paclk0: irc paclk1: exirc paclk2: uart0, uart1 paclk3: gpio paclk4: rbc paclk5: 32 bit timer paclk6: i2c 2 (i2c_0, i2c_1) paclk7: can 2 (can_0, can_1) paclk8: uart2, uart3 paclk9: adc 2 (adc0, adc1) paclk10: pwm 2ch paclk11: spi paclk12: ccnt paclk13: uart4, uart5 paclk14: etm9cssingle apb port paclk15: (reserved)
5-16 MB86R01 lsi product specifications fujitsu semiconductor confidential clock reset generator (crg) 5.4.9. apb (b) bus clock gate control register (crpb) this register controls clock gate of apb (b) bus. address fffe_7000 h + 20 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pbgate[15:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 bit field no. name description 31-16 ? unused bits. write access is ignored, and read va lue of these bits is undefined. 15-0 pbgate[15:0] these bits control pbclk clock gate. this lsi does not use them. pbgate[n] description 0 pbclkn stops 1 pbclkn does not stop (initial value)
5-17 MB86R01 lsi product specifications fujitsu semiconductor confidential clock reset generator (crg) 5.4.10. ahb (b) bus clock gate control register (crhb) this register controls clock gate of ahb (b) bus. address fffe_7000 h + 24 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hbgate[15:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 bit field no. name description 31-16 ? unused bits. write access is ignored, and read va lue of these bits is undefined. 15-0 hbgate[15:0] hbclk clock gate control these bits control hbclk clock gate. hbgate[n] description 0 hbclkn stops 1 hbclkn does not stop (initial value) hbclk0: gdc (host if) hbclk1: gdc (draw, geo), mbus2axi (drw) hbclk2: (reserved) hbclk3: gdc (disp0), mbus2axi (disp) hbclk4: gdc (disp1) hbclk5: gdc (cap0), mbus2axi (cap) hbclk6: gdc (cap1) hbclk7: axi, ahb2axi, hbus2axi hbclk8: ddr2 controller, ddr2 i/f hbclk9: mlb hbclk10: (reserved) hbclk11: (reserved) hbclk12: (reserved) hbclk13: (reserved) hbclk14: (reserved) hbclk15: (reserved)
5-18 MB86R01 lsi product specifications fujitsu semiconductor confidential clock reset generator (crg) 5.4.11. arm core clock gate control register (cram) this register controls clock gate of arm core. address fffe_7000 h + 28 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) armbg ate (reserved) armag ate r/w r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r/w r1 r1 r1 r/w initial value 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 bit field no. name description 31-16 ? unused bits. the write access is ignored, and read value of these bits is undefined. 15-5 (reserved) reserved bits. write access is ignored, and read valu e of these bits is always "1". 4 armbgate armbclk clock gate control this bit controls armbclk clock gate. 0 armbclk stops 1 armbclk does not stop (initial value) this clock is used to atclk of etm9cs single. 3-1 (reserved) reserved bits. write access is ignored, and read valu e of these bits is always "1". 0 armagate armaclk clock gate control this bit controls armaclk clock gate. 0 armaclk stops 1 armaclk does not stop (initial value) after stopping this clock, proceed system reset to resume operation.
5-19 MB86R01 lsi product specifications fujitsu semiconductor confidential clock reset generator (crg) 5.5. operation this section descries crg operation. 5.5.1. generation of reset factor there are following five reset factors. 1. external reset (xrst pin input) the entire chip is initialized by the reset input from external pin, xrst. when external pin, pllbypass is set to "l", external reset shifts to pll oscillation stabilization waiting state. 2. software reset (reset with register control) software reset occurs with writing "1" to swrstr eq bit of the reset/standby control register (crsr). it does not change state to pll osc illation stabilization even though pllbypass bit of the pll control register (crpr) is "0" (setting that uses pll clock.) moreover, this reset does not change the crg module register, the vinithi control register of remap/boot controller (rbc), and th e initram control register. clock source of the software reset is time based tim er?s count value. it is cleared when software reset is asserted. this software reset generates the internal signal, which does not reset as crstn. 3. xsrst (reset request from debugging tool) this signal is reset request from debugging tool (e.g. multiice), and internal reset request is able to transmit to the tool through xsrst pin this module recognizes the reset signal to be the same reset request as external reset?s. 4. xtrst (built-in ice macro reset request from debugging tool) this signal is built-in ice macro reset request fr om debugging tool (e.g. multiice), and the reset signal is to request reset to built-in ice macro in arm9. although the reset signal is asserted, other peripherals are not initialized. etm9cs single is also reset by this signal.
5-20 MB86R01 lsi product specifications fujitsu semiconductor confidential clock reset generator (crg) 5. watchdog reset when wdtset/wdtclr bits of the watchdog timer control register (crwr) are set to "1" after external reset, watchdog timer starts. writing "1" to the wdtset/wdtclr bits at the second time or later clears the timer. clock source of the watchdog timer is count value of the time based timer. clear operation of time based timer affects on watchdog timer?s count value. when the timer is cleared, the watchdog timer is also cleared. selected time base timer bit wdtclr (max) wdtclr (min) watchdog reset request tcl k x 2 n tcl k x 2 (n+1) figure 5-2 timing of watchdog reset as shown in figure 5-2, watchdog reset occurs after sec ond falling edge of selected time based timer bit. during pll oscillation stabilization waiting time and arm9 debug mode (dbgack = 1), crg clears watchdog timer. moreover, it monitors standby mode of arm9 and clears watchdog timer automatically in the standby mode (standby mode = 1.) reset output signal reset signal output from the reset generator based on the reset factor is as follows. hresetn (ahb/apb bus reset) this internal reset signal initializes arm9 and ahb/apb peripherals, and it is output by external reset, software reset or xsrst reset. xsrst (reset monitoring) this signal reports to external circuit of arm?s internal reset source, moreover it is asserted the same as hresetn signal. internal xtrst (built-in ice macro reset) this signal initializes built-in macro of arm9. the macro must be reset at power-on so that this signal is output by external reset or external xtrst reset. crstn (internal reset) this signal is output by external reset or xsrst reset.
5-21 MB86R01 lsi product specifications fujitsu semiconductor confidential clock reset generator (crg) table 5-3 shows correlation between reset factor and reset output signal. table 5-3 correlation between reset factor and reset output signal reset factor reset output external reset software reset input xsrst xtrst watchdog reset hresetn asserted asserted asserted not asserted asserted output xsrst asserted asserted no t asserted not asserted asserted internal xtrst asserted not asserted not asserted asserted not asserted crstn asserted not asserted asserted not asserted asserted
5-22 MB86R01 lsi product specifications fujitsu semiconductor confidential clock reset generator (crg) 5.5.2. clock generation figure 5-3 shows clock generation chart. pll ck fb x 1 1/n 1/2 0 1/l 4 gate armadm [ 2:0 ] 1/l 1 gate hagate [ 0 ] | stop hadm[2:0] 1/l 6 gate a rmaclk haclkcr g haclkn hbclkn n = 49, 46, 37, 20, 47, 44, 36, 19, 39, 38, 30, 15 l n = 1, 2, 4, 8, 16 pllbypass cl k pllmode[4:0] hbgate [ 0 ] | stop hbdm [ 2: 0 ] 1/l 2 gate pag at e[ 0] | st op padm[2:0] 1/l 3 gate pac lkc r g pac lkn pbclkn (unused) pbgate[0] | stop pbdm[2:0] gate stop gate stop cclk 1/l 5 gate armbdm [ 2:0 ] a rmbclk display reference clock armagate | stop armbgate | stop a hb clock (a) a pb clock (a) a rm clock a hb clock (b) (axi etc.) etm cl ock cclk figure 5-3 clock generation chart
5-23 MB86R01 lsi product specifications fujitsu semiconductor confidential clock reset generator (crg) pll control oscillation stabilization waiting the clock transmission source in oscillation stabilization waiting is count value of the time based timer. clear operation of time based timer affects on its count value. when this module state is changed to pll oscilla tion stabilization waiting state as shown below, the time based timer is cleared. (1) external reset is asserted ("m" in figure 5-4 and "m" of luwmode in the 5.4.2 pll contr ol register (crpr)) pll oscillation stabilization waiting erstn pll reset clk 1/m pll clock cclk hresetn pllread y pllbypass 6 clk cycles a) external reset deasserted (xrst) b) erstn reset (crg internal signal) c) pll reset deasserted d) pll ready e) hresetn deasserted a ) b ) c ) d ) e ) xrst (m 2 + 2) clk cycles 21 or more cclk cycles figure 5-4 pll oscillation stabilizatio n waiting state after external reset (2) pll oscillation frequency is changed by pll mode ("m" in figure 5-5 and "m" of lu wmode in the 5.4.2 pll control register (crpr)) xrst pll reset clk 1/m pll clock cclk pllread y pllbypass pllmode [ 4:0 ] pll oscillation stabilization waiting a) clock source change (write pllbypass bit) b) set the pll oscillation mode (write pllmode bits) c) pll reset de-asserted d) pll ready (pllready can be monitored by pllrdy bit) e) clock source change (write pllbypass bit) c ) d ) e ) b ) a ) (m 2 + 2) clk cycles figure 5-5 pll oscillation stabilization waiting state by pll mode change
5-24 MB86R01 lsi product specifications fujitsu semiconductor confidential clock reset generator (crg) (3) returning from stop mode by external interrupt (see figure 5-9) (4) watchdog reset is asserted frequency change oscillation frequency and frequency dividing ratio (m) of pll (f clk n) are set by pllmode[4:0] bit of the pll control register (crpr), and the frequency is able to be changed during the operation (see table 5-4.) do not change pllmode[4:0] when pllbypass bit of the pll control register (crpr) is 0. initial value at start up is determined by external pin, pllbypass and cripm[3:0]. to specify pllstop with the initial value, fix external pin, pllbypass to "1" as well. table 5-4 setting example of i nput frequency and multiple number 43210 0000049 13.5mhz 661.5mhz 330.8mhz 330.8mhz 165.4mhz 82.7mhz 165.4mhz 41.3mhz 0000146 14.3mhz 658.7mhz 329.4mhz 329.4mhz 164.7mhz 82.3mhz 164.7mhz 41.2mhz 0001037 17.7mhz 656.0mhz 328.0mhz 328.0mhz 164.0mhz 82.0mhz 164.0mhz 41.0mhz 0001120 33.3mhz 666.6mhz 333.3mhz 333.3mhz 166.7mhz 83.3mhz 166.7mhz 41.7mhz 0010047 13.5mhz 634.5mhz 317.3mhz 317.3mhz 158.6mhz 79.3mhz 158.6mhz 39.7mhz 0010144 14.3mhz 630.1mhz 315.0mhz 315.0mhz 157.5mhz 78.8mhz 157.5mhz 39.4mhz 0011036 17.7mhz 638.3mhz 319.1mhz 319.1mhz 159.6mhz 79.8mhz 159.6mhz 39.9mhz 0011119 33.3mhz 633.3mhz 316.6mhz 316.6mhz 158.3mhz 79.2mhz 158.3mhz 39.6mhz 0100039 13.5mhz 526.5mhz 263.3mhz 263.3mhz 131.6mhz 65.8mhz 131.6mhz 32.9mhz 0 0 0 1 0 37 14.3mhz 529.8mhz 264.9mhz 264.9mhz 132.5mhz 66.2mhz 132.5mhz 33.1mhz 0 1 0 1 0 30 17.7mhz 531.9mhz 266.0mhz 266.0mhz 133.0mhz 66.5mhz 133.0mhz 33.2mhz 0101115 33.3mhz 500.0mhz 250.0mhz 250.0mhz 125.0mhz 62.5mhz 125.0mhz 31.2mhz 11111 haclkn hbclkn paclkn pll output /display reference clock cclk armaclk armbclk initial setting: {pllbypass, cripm[3:0]} at operation: pllmode[4:0] operation frequency multiple number pll stop 333m 320m 266m input frequency clk pllbypass main clock (cclk) of this module is able to be switched dynamically between pll clock and external input clock (clk) by pllbypass bit of the pll control register (crpr.) clk 1/m pll clock cclk pllready pllbypass a ) a) clock source change (write pllbypass bit (write 0)) b) clock source change (write pllbypass bit (write 1)) b ) clock switchin g clock switchin g figure 5-6 clock switch between pll clock and external clock
5-25 MB86R01 lsi product specifications fujitsu semiconductor confidential clock reset generator (crg) clock gear crg corresponds to the clock gear function with clock enable signal. cclk a ramdm a rmaclken a rmaclk hadm haclken haclk 000 001 001 010 padm paclken paclk 010 figure 5-7 clock gear standby mode (standby and stop) arm9 and crg correspond to following two standby modes. (1) standby mode arm926ej-s core corresponds to standby mode that is called "wait for interrupt mode" with cp15. the standbywfi signal is asserted and internal clock gate is closed not to supply input clock to sub module during the standby mode (refer to arm926ej-s technical reference manual, "12.1.1 dynamic power management (wait for interrupt mode)".) this crg does not equip function to stop armclk in the standby mode. a rmclk clock reset generator a rm926ej-s clk clock gate standbywfi internal cl oc k figure 5-8 standbywfi mode (arm926ej-s) (2) stop mode when standbywfi (arm926ej-s) signal is set to "1" with stopen = 1, the state changes to stop mode through standby mode (at stopen = 1, this module?s standbywfi signal is "1".) in this mode, crg stops all clocks and pll oscillation; moreover, the stop mode is released with external rest or external interrupt. figure 5-9 shows stop mode operation. no te: when state is changed to the stop mode, "1" should be written to pllbypass bit of the pll control register (crpr.) although pll proceeds oscillation stabilization waiting at stop mo de release, clock is not switched to pll clock until pllbypass bit becomes "0"; in addition, pll oscillation stabilization waiting state is skipped when pllmode[4:0] is 5?b11111.
5-26 MB86R01 lsi product specifications fujitsu semiconductor confidential clock reset generator (crg) clk stop mode stopen standbywfi paclk0_stp stop wakeup cclk a rma(b)clk haclk paclk pllbypass pllrdy pll clock pll reset pll oscillation stabilization waiting * stop = clk clock is able to stop while the value is "1? figure 5-9 stop mode
6-1 MB86R01 lsi product specifications fujitsu semiconductor confidential remap boot controller (rbc) 6. remap boot controller (rbc) this chapter describes function and operation of remap boot controller (rbc.) 6.1. outline rbc is apb slave module. it provides system boot operation control and controls remap sequence of the system, vinithi signal of arm926ej-s tm , and initram signal that enab le exception vector address change and itcm reboot after power-on reset. 6.2. feature rbc has following features: ? remap control register ? initram signal control register ? vinithi signal control register 6.3. block diagram figure 6-1 shows rbc block diagram. rbc remap control register apb signals remap initram control register initram vinithi control register vinithi (from pin) vinithi crstn (from crg) hresetn (from crg) (to busmatrix) (to a rm926ej-s core ) (to a rm926ej-s core ) figure 6-1 rbc block diagram table 6-1 shows rbc?s external port function. table 6-1 rbc external port function list signal name i/o description vinithi i default value of output port, vinithi
6-2 MB86R01 lsi product specifications fujitsu semiconductor confidential remap boot controller (rbc) 6.4. supply clock apb clock is supplied to rbc. refer to "5. cloc k reset generator (crg)" for frequency setting and control specification of the clock. 6.5. register this section describes rbc register. 6.5.1. register list rbc is controlled by the register shown in table 6-2. t able 6-2 rbc register list address base offset register name abbreviation description + 00 h (reserved) ? reserved area (access prohibited) + 04 h remap control register rbremap remap state control + 08 h vinithi control register a rbv iha vinithi output signal control fffe_6000 h + 0c h initram control register a rbi tra initram output signal control + 10 h ? + fff h (reserved) ? reserved area (access prohibited)
6-3 MB86R01 lsi product specifications fujitsu semiconductor confidential remap boot controller (rbc) description format of register following format is used for descri ption of register?s each bit in " 6.5.2 remap control register (rbremap)" to " 6.5.4 initram control register a (rbitra)". address base address + offset bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r/w initial value bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r/w initial value meaning of item and sign address address (base address + offset address) of the register bit bit number of the register name bit field name of the register r/w attribution of read/write of each bit field ? r0:read value is always "0" ? r1: read value is always "1" ? w0: write value is always "0", and write access of "1" is ignored ? w1: write value is always "1", and write access of "0" is ignored ? r: read ? w: write initial value each bit field?s value after reset ? 0: value is "0" ? 1: value is "1" ? x: value is undefined
6-4 MB86R01 lsi product specifications fujitsu semiconductor confidential remap boot controller (rbc) 6.5.2. remap control register (rbremap) remap control register (rbremap) controls remap stat e. once remap is carried out, its state kept until reset. write operation to this register is valid only th e first time after reset, and its second time or later is ignored. this register is reset by hresetn input. this register should be accessed in word unit. address gpr0: fffe_6000 h + 04 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) rem ap r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-1 (reserved) reserved bit. 0 remap remap state is controlled. when write operation to remap register is pe rformed (both "0" and "1" of write data are available) remap output signal becomes high. busmatrix is designed to remap memo ry map with remap output signal. remap = low: vector area is allocated to internal boot rom remap = high: vector area is allocated to internal sram_0
6-5 MB86R01 lsi product specifications fujitsu semiconductor confidential remap boot controller (rbc) 6.5.3. vinithi control register a (rbviha) vinithi control register a (rbviha) controls vinithi output signal. this register is reset by the crstn input, and its initial value is determined by input level of external pin, vinithi. this register should be accessed in word unit. address gpr0: fffe_6000 h + 08 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value determined by input level of external pin, vinithi bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) viha r/w r r r r r r r r r r r r r r r r/w initial value determined by input level of external pin, vinithi bit field no. name description 31-1 (reserved) reserved bits. write access is ignored. reading these bits enable read ing the value set by vinithi. 0 viha vinthi output signal is controlled.
6-6 MB86R01 lsi product specifications fujitsu semiconductor confidential remap boot controller (rbc) 6.5.4. initram control register a (rbitra) initram control register a (rbitra) controls initram output signal. this register is reset by the crstn input. it should be accessed in word unit. address gpr0: fffe_6000 h + 0c h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) itra r/w r r r r r r r r r r r r r r r r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-1 (reserved) reserved bits. write access is ignored. read valu e of these bits is always "0". 0 itra intram output signal is controlled.
6-7 MB86R01 lsi product specifications fujitsu semiconductor confidential remap boot controller (rbc) 6.6. operation this section describes rbc operation. 6.6.1. rbc reset rbc has two reset input ports. rbremap register is reset by hr esetn input, and rbviha and rbitr a registers are reset by crstn value. table 6-3 shows correlation between these reset and register. t able 6-3 correlation between reset and register reset input register description hresetn rbremap this port is reset by hresetn. rbviha this port value reflects to valu e of external pin, vinithi by crstn input. crstn rbitra this port is reset by crstn input. 6.6.2. remap control remap changes vector area (00000000 h - 00008000 h ) after power-on. vector area is allocated to built-in boot rom at power-on and the system starts up from it. with the remap control, the allocated area is changed to built-in sram_0; then vector table is able to be overwritten. 6.6.3. vinithi control arm926ej-s has vinithi signal which determines exception vector address. when it is low at reset, the exception vector is located in 00000000 h . on the other hand, when the signal is high at reset, the exception vector is located in ffff0000 h . refer to "technical reference manual" of individual arm9 provided by arm ltd. for detail of vinithi signal. the initial value of rbviha register is defined by external pin, vinithi.
6-8 MB86R01 lsi product specifications fujitsu semiconductor confidential remap boot controller (rbc) 6.6.4. initram control arm926ej-s has initram signal. when it is high at reset, instruction tcm automatically becomes valid which enables reboot operation from itcm. refer to "technical reference manual" of individual arm9 core provided by arm ltd. for detail of initram signal. rbitra register is initialized to "0" by crstn, how ever it is not reset by hresetn. this means, reboot operation from itcm is able to be proceeded at software reset when exception vector table is copied to itcm before software reset
7-1 MB86R01 lsi product specifications fujitsu semiconductor confidential interrupt controller (irc) 7. interrupt controller (irc) this chapter describes function and operation of interrupt controller (irc.) 7.1. outline irc consists of two channels, irc0 and irc1 which determine priority of irq source up to 32 factors respectively, and report to arm core the highest prio rity irq source as irq interrupts. therefore, those channels have priority setting register of irq factor and level setting register for the interrupt from arm core. note: the irq interrupt determined by irc1 is accepted as irq6 interrup t factor of irc0. therefore, priority of all irq sources allocated to irc1 is determined according to irc1 and irc0?s irq6 settings. the irq vector defined in arm926ej-s is only "018", but the vector table factor is extended to 32 by irc. when irq interrupt is asserted to the arm co re, interrupt vector table address corresponding to the irq interrupt factor is generated and displayed during the register. irq interrupt handler must refer to the v ector table extended further than "018". irc, connected to apb bus has delay interrupt c ontrol circuit and interrupt wake-up circuit from stop/standby mode which is composed of clock control circuit. 7.2. feature irc has following features: ? 2 channels of irc to correspond up to 32 factors of interrupt request ? determination of irq interrupt priority to transfer to arm926ej-s ? enable/mask of extension irq interrupt ? extension irq vector address display ? supply of returning signal from stop mode to crg (clock/reset generator) ? capability of issuing software interrupt (irc0_irq30/irc0_fiq ) by register access
7-2 MB86R01 lsi product specifications fujitsu semiconductor confidential interrupt controller (irc) 7.3. block diagram figure 7-1 shows irc block diagram and detail of interrupt request signal connection. a 92 6 arm926ej-s commtx commrx nir q nfi q irc0 (32ch) dma c 8ch timer 2ch uart 2ch external interrupt request ext irc 4ch 4 8 2 2 23 ????16 4 swir1 s wir 0 irq 25 24 27 26 31 30 29 28 not used n o t use d not used adc 2ch 2 gpi o 1ch 1 15 14 13 . . 10 9 8 7 6 1 5 . . . 0 irc1 (32ch) 23 ... 19 swir1 s wir 0 irq 25 27 26 31 30 29 28 12 11 10 9 8 7 6 4 gd c 1 0 1 3 2 5 14 13 18 ? 15 n o t used can 2ch sd i/f 1ch mbus 2axi i2s 3ch spi 1ch ide6 6 1ch i2 c 2ch pw m 2ch uart 4ch usb ahb 2axi mbus 2axi hbus 2axi mlb 1ch 1 1 11 1 3 2 1 5 422 3 2 not used apb bus apb bus 24 n o t used figure 7-1 block diagram of irc
7-3 MB86R01 lsi product specifications fujitsu semiconductor confidential interrupt controller (irc) 7.4. supply clock apb clock is supplied to irc. refer to "5. clock reset generator (crg)" for frequency setting and control specification of the clock. 7.5. interrupt map this section describes interrupt map. 7.5.1. exception vector to arm926ej-s core table 7-1 shows exception vector defined in the arm926ej-s core. each interrupt factor input to irc is notifie d as final interrupt of either irq (0000_0018 h/ ffff_0018 h ) or fiq (0000_001c h / ffff_001c h ) to the core. table 7-1 exception vector defined by arm926ej-s exception factor mode vector address at low vector/high vector reset svc 0000_0000 h /ffff_0000 h undefined instruction und 0000_0004 h /ffff_0004 h software interrupt svc 0000_0008 h /ffff_0008 h prefetch abort (memory fault at in struction fetch) abort 0000_000c h /ffff_000c h data abort (memory fault at data access) abort 0000_0010 h /ffff_0010 h reserved ? 0000_0014 h /ffff_0014 h irq (normal) interrupt irq 0000_0018 h /ffff_0018 h fiq (high speed) interrupt fiq 0000_001c h /ffff_001c h
7-4 MB86R01 lsi product specifications fujitsu semiconductor confidential interrupt controller (irc) 7.5.2. extension irq interrupt vector of irc0/irc1irc0/irc1 table 7-2 and table 7-3 show irq interrupt vector extended by irc0/irc1. base address of the ex tension vector table is determined with irc's tbr register. table 7-2 expansion irq interrupt vector of irc0 irq interrupt no. exception factor decimal notation hexadecimal notation interrupt control register (level setting) correction value tbr address + correction value (at tbr=0000_0000 h ) irq0 (unused) | irq5 (unused) 0 | 5 00 h | 05 h icr00 | icr05 20 h | 34 h 0000_0020 h | 0000_0034 h irq6 (irc1 interrupt) 6 06 h icr06 38 h 0000_0038 h irq7 (gpio interrupt) 7 07 h icr07 3c h 0000_003c h irq8 (adc ch0 interrupt) 8 08 h icr08 40 h 0000_0040 h irq9 (adc ch1 interrupt) 9 09 h icr09 44 h 0000_0044 h irq10 (external interrupt 0) 10 0a h icr10 48 h 0000_0048 h irq11 (external interrupt 1) 11 0b h icr11 4c h 0000_004c h irq12 (external interrupt 2) 12 0c h icr12 50 h 0000_0050 h irq13 (external interrupt 3) 13 0d h icr13 54 h 0000_0054 h irq14 (timer ch0 interrupt) 14 0e h icr14 58 h 0000_0058 h irq15 (timer ch1 interrupt) 15 0f h icr15 5c h 0000_005c h irq16 (dmac ch0 interrupt) 16 10 h icr16 60 h 0000_0060 h irq17 (dmac ch1 interrupt) 17 11 h icr17 64 h 0000_0064 h irq18 (dmac ch2 interrupt) 18 12 h icr18 68 h 0000_0068 h irq19 (dmac ch3 interrupt) 19 13 h icr19 6c h 0000_006c h irq20 (dmac ch4 interrupt) 20 14 h icr20 70 h 0000_0070 h irq21 (dmac ch5 interrupt) 21 15 h icr21 74 h 0000_0074 h irq22 (dmac ch6 interrupt) 22 16 h icr22 78 h 0000_0078 h irq23 (dmac ch7 interrupt) 23 17 h icr23 7c h 0000_007c h irq24 (uart ch0 interrupt) 24 18 h icr24 80 h 0000_0080 h irq25 (uart ch1 interrupt) 25 19 h icr25 84 h 0000_0084 h irq26 (unused) 26 1a h icr26 88 h 0000_0088 h irq27 (unused) 27 1b h icr27 8c h 0000_008c h irq28 (commrx interrupt) 28 1c h icr28 90 h 0000_0090 h irq29 (commtx interrupt) 29 1d h icr29 94 h 0000_0094 h irq30 (delay interrupt 0) 30 1e h icr30 98 h 0000_0098 h irq31 (unused) 31 1f h icr31 9c h 0000_009c h
7-5 MB86R01 lsi product specifications fujitsu semiconductor confidential interrupt controller (irc) table 7-3 extension irq interrupt vector of irc1 irq interrupt no. exception factor decimal notation hexadecimal notation interrupt control register (level setting) correction value tbr address + correction value (at tbr=0000_0100 h ) irq0 (gdc interrupt) 0 00 h icr00 20 h 0000_0120 h irq1 (unused) 1 01 h icr01 24 h 0000_0124 h irq2 (can ch0 interrupt) 2 02 h icr02 28 h 0000_0128 h irq3 (can ch1 interrupt) 3 03 h icr03 2c h 0000_012c h irq4 (sd i/f interrupt) 4 04 h icr04 30 h 0000_0130 h irq5 (mbus2axi (cap) interrupt) 5 05 h icr05 34 h 0000_0134 h irq6 (i2s ch0 interrupt) 6 06 h icr06 38 h 0000_0138 h irq7 (i2s ch1 interrupt) 7 07 h icr07 3c h 0000_013c h irq8 (i2s ch2 interrupt) 8 08 h icr08 40 h 0000_0140 h irq9 (spi interrupt) 9 09 h icr09 44 h 0000_0144 h irq10 (ide66 interrupt) 10 0a h icr10 48 h 0000_0148 h irq11 (i2c ch0 interrupt) 11 0b h icr11 4c h 0000_014c h irq12 (i2c ch1 interrupt) 12 0c h icr12 50 h 0000_0150 h irq13 (pwm ch0 interrupt) 13 0d h icr13 54 h 0000_0154 h irq14 (pwm ch1 interrupt) 14 0e h icr14 58 h 0000_0158 h irq15 (uart ch2 interrupt) 15 0f h icr15 5c h 0000_015c h irq16 (uart ch3 interrupt) 16 10 h icr16 60 h 0000_0160 h irq17 (uart ch4 interrupt) 17 11 h icr17 64 h 0000_0164 h irq18 (uart ch5 interrupt) 18 12 h icr18 68 h 0000_0168 h irq19 (usb 2.0 host phycnt interrupt) 19 13 h icr19 6c h 0000_016c h irq20 (usb 2.0 ehci host interrupt) 20 14 h icr20 70 h 0000_0170 h irq21 (usb 1.1 ohci host interrupt) 21 15 h icr21 74 h 0000_0174 h irq22 (usb 2.0 function interrupt) 22 16 h icr22 78 h 0000_0178 h irq23(usb 2.0 function dmac interrupt) 23 17 h icr23 7c h 0000_017c h irq24 (ahb2_axi (ahbbus) interrupt) 24 18 h icr24 80 h 0000_0180 h irq25 (unused) 25 19 h icr25 84 h 0000_0184 h irq26 (mbus2axi (disp) interrupt) 26 1a h icr26 88 h 0000_0188 h irq27 (mbus2axi (draw) interrupt) 27 1b h icr27 8c h 0000_018c h irq28 (hbus2axi interrupt) 28 1c h icr28 90 h 0000_0190 h irq29 (mlb_cint interrupt) 29 1d h icr29 94 h 0000_0194 h irq30 (mlb_sint interrupt) 30 1e h icr30 98 h 0000_0198 h irq31 (mlb_dint interrupt) 31 1f h icr31 9c h 0000_019c h
7-6 MB86R01 lsi product specifications fujitsu semiconductor confidential interrupt controller (irc) 7.6. register this section describes irc register. 7.6.1. register list table 7-4 shows irc0 register list and table 7-5 shows irc1 register list.
7-7 MB86R01 lsi product specifications fujitsu semiconductor confidential interrupt controller (irc) table 7-4 irc0 register list address base offset register name abbreviation description + 00 h irq flag register ir0irqf irq interrupt flag control + 04 h irq mask register ir0irqm irq in terrupt asserted mask control + 08 h interrupt level mask register ir0ilm valid interrupt level setting from arm core + 0c h icr monitoring register ir0icrmn current irq interrupt source?s interrupt level display + 10 h (reserved) ? reserved (access prohibited) + 14 h delay interrupt register 0 ir0dicr0 de lay interrupt control for task switch ffff_fe00 h or fffe_8000 h + 18 h delay interrupt register 1 ir0dicr1 delay interrupt control + 1c h table base register ir0tbr high order a ddress (24 bit) setting of irq vector + 20 h interrupt vector register ir0vct interrupt vector table display + 24 h (reserved) ? reserved (access prohibited) + 28 h (reserved) ? reserved (access prohibited) + 2c h (reserved) ? reserved (access prohibited) + 30 h interrupt control register 0 ir0icr00 irq0 interru pt level setting (unuse d and access prohibited) + 34 h interrupt control register 1 ir0icr01 irq1 interru pt level setting (unuse d and access prohibited) + 38 h interrupt control register 2 ir0icr02 irq2 interru pt level setting (unuse d and access prohibited) + 3c h interrupt control register 3 ir0icr03 irq3 interru pt level setting (unuse d and access prohibited) + 40 h interrupt control register 4 ir0icr04 irq4 interru pt level setting (unuse d and access prohibited) + 44 h interrupt control register 5 ir0icr05 irq5 interru pt level setting (unuse d and access prohibited) + 48 h interrupt control register 6 ir0icr06 irq6 interrupt level setting (irc1 interrupt) + 4c h interrupt control register 7 ir0icr07 irq7 interrupt level setting (gpio interrupt) + 50 h interrupt control register 8 ir0icr08 irq8 interrupt level setting (adc ch0 interrupt) + 54 h interrupt control register 9 ir0icr09 irq9 in terrupt level setting (adc ch1 interrupt) + 58 h interrupt control register 10 ir0icr10 irq10 interrupt is set (external interrupt 0) + 5c h interrupt control register 11 ir0icr11 irq11 in terrupt level setting (e xternal interrupt 1) + 60 h interrupt control register 12 ir0icr12 irq12 inte rrupt level setting (external interrupt 2) + 64 h interrupt control register 13 ir0icr13 irq13 inte rrupt level setting (external interrupt 3) + 68 h interrupt control register 14 ir0icr14 irq14 in terrupt level setting (timer ch0 interrupt) + 6c h interrupt control register 15 ir0icr15 irq15 in terrupt level setting (timer ch1 interrupt) + 70 h interrupt control register 16 ir0icr16 irq16 in terrupt level setting (dmac ch0 interrupt) + 74 h interrupt control register 17 ir0icr17 irq17 in terrupt level setting (dmac ch1 interrupt) + 78 h interrupt control register 18 ir0icr18 irq18 in terrupt level setting (dmac ch2 interrupt) + 7c h interrupt control register 19 ir0icr19 irq19 in terrupt level setting (dmac ch3 interrupt) + 80 h interrupt control register 20 ir0icr20 irq20 in terrupt level setting (dmac ch4 interrupt) + 84 h interrupt control register 21 ir0icr21 irq21 in terrupt level setting (dmac ch5 interrupt) + 88 h interrupt control register 22 ir0icr22 irq22 in terrupt level setting (dmac ch6 interrupt) + 8c h interrupt control register 23 ir0icr23 irq23 in terrupt level setting (dmac ch7 interrupt) + 90 h interrupt control register 24 ir0icr24 irq24 in terrupt level setting (uart ch0 interrupt) + 94 h interrupt control register 25 ir0icr25 irq25 in terrupt level setting (uart ch0 interrupt) + 98 h interrupt control register 26 ir0icr26 irq26 inte rrupt level setting (unused and access prohibited) + 9c h interrupt control register 27 ir0icr27 irq27 inte rrupt level setting (unused and access prohibited) + a0 h interrupt control register 28 ir0icr28 irq28 interrupt level setting (commrx interrupt) + a4 h interrupt control register 29 ir0icr29 irq29 interrupt level setting (commtx interrupt) + a8 h interrupt control register 30 ir0icr30 irq30 interrupt level setting (delay interrupt) + ac h interrupt control register 31 ir0icr31 irq31 inte rrupt level setting (unused and access prohibited)
7-8 MB86R01 lsi product specifications fujitsu semiconductor confidential interrupt controller (irc) table 7-5 irc1 register list address base offset register name abbreviation description + 00 h irq flag register ir1irqf irq interrupt flag control + 04 h irq mask register ir1irqm irq in terrupt asserted mask control + 08 h interrupt level mask register ir1ilm valid interrupt level setting from arm core + 0c h icr monitoring register ir1icrmn current irq interrupt source?s interrupt level display + 10 h (reserved) ? reserved (access prohibited) + 14 h (reserved) ? reserved (access prohibited) fffb_0000 h + 18 h (reserved) ? reserved (access prohibited) + 1c h table base register ir1tbr irq vector?s high order address (24 bit) setting + 20 h interrupt vector register ir1vct interrupt vector table display + 24 h (reserved) ? reserved (access prohibited) + 28 h (reserved) ? reserved (access prohibited) + 2c h (reserved) ? reserved (access prohibited) + 30 h interrupt control register 0 ir1icr00 irq0 interrupt level setting (gdc interrupt) + 34 h interrupt control register 1 ir1icr01 irq1 inte rrupt level setting (unu sed and access prohibited) + 38 h interrupt control register 2 ir1icr02 irq2 in terrupt level setting (can ch0 interrupt) + 3c h interrupt control register 3 ir1icr03 irq3 in terrupt level setting (can ch1 interrupt) + 40 h interrupt control register 4 ir1icr04 irq4 interrupt level setti ng (sd i/f interrupt) + 44 h interrupt control register 5 ir1icr05 irq5 inte rrupt level setting (mbus2axi (cap) interrupt) + 48 h interrupt control register ir1icr06 irq6 in terrupt level setting (i2s ch0 interrupt) + 4c h interrupt control register 7 ir1icr07 irq7 interrupt level setting (i2s ch1 interrupt) + 50 h interrupt control register 8 ir1icr08 irq8 interrupt level setting (i2s ch2 interrupt) + 54 h interrupt control register 9 ir1icr09 irq9 interrupt level setting (spi interrupt) + 58 h interrupt control register 10 ir1icr10 irq10 interrupt level setting (ide66 interrupt) + 5c h interrupt control register 11 ir1i cr11 irq11 interrupt level setting (i 2 c ch0 interrupt) + 60 h interrupt control register 12 ir1i cr12 irq12 interrupt level setting (i 2 c ch1 interrupt) + 64 h interrupt control register 13 ir1icr13 irq13 in terrupt level setting (pwm ch0 interrupt) + 68 h interrupt control register 14 ir1icr14 irq14 in terrupt level setting (pwm ch1 interrupt) + 6c h interrupt control register 15 ir1icr15 irq15 in terrupt level setting (uart ch2 interrupt) + 70 h interrupt control register 16 ir1icr16 irq16 in terrupt level setting (uart ch3 interrupt) + 74 h interrupt control register 17 ir1icr17 irq17 in terrupt level setting (uart ch4 interrupt) + 78 h interrupt control register 18 ir1icr18 irq18 in terrupt level setting (uart ch5 interrupt) + 7c h interrupt control register 19 ir1icr19 irq19 in terrupt level setting (usb 2.0 host phycnt interrupt) + 80 h interrupt control register 20 ir1icr20 irq20 interru pt level setting (usb 2.0 ehci host interrupt) + 84 h interrupt control register 21 ir1icr21 irq21 interrupt level setting (usb 1.1 ohci host interrupt) + 88 h interrupt control register 22 ir1icr22 irq22 inte rrupt level setting (usb 2.0 function interrupt) + 8c h interrupt control register 23 ir1icr23 irq23 inte rrupt level setting (usb 2.0 function dmac interrupt) + 90 h interrupt control register 24 ir1icr24 irq24 in terrupt level setting (ahb2_axi (ahbbus) interrupt) + 94 h interrupt control register 25 ir1icr25 irq25 inte rrupt level setting (unused and access prohibited) + 98 h interrupt control register 26 ir1icr26 irq26 inte rrupt level setting (mbus2axi (disp) interrupt) + 9c h interrupt control register 27 ir1icr27 irq27 interrupt level setting (mbus2axi (draw) interrupt) + a0 h interrupt control register 28 ir1icr28 irq28 in terrupt level setting (hbus2axi interrupt) + a4 h interrupt control register 29 ir1icr29 irq29 in terrupt level setting (mlb_cint interrupt) + a8 h interrupt control register 30 ir1icr30 irq30 in terrupt level setting (mlb_sint interrupt) + ac h interrupt control register 31 ir1icr31 irq31 in terrupt level setting (mlb_dint interrupt)
7-9 MB86R01 lsi product specifications fujitsu semiconductor confidential interrupt controller (irc) description format of register following format is used for descri ption of register?s each bit in " 7.6.2 irq flag register (ir0irqf/ ir1 irqf)" to " 7.6.10 interrupt control register (ir0icr31/ir1icr31 ? ir0icr00/ir1icr00)". address base address + offset bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r/w initial value bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r/w initial value meaning of item and sign address address (base address + offset address) of the register bit bit number of the register name bit field name of the register r/w attribution of read/write of each bit field ? r0:read value is always "0" ? r1: read value is always "1" ? w0: write value is always "0", and write access of "1" is ignored ? w1: write value is always "1", and write access of "0" is ignored ? r: read ? w: write initial value each bit field?s value after reset ? 0: value is "0" ? 1: value is "1" ? x: value is undefined
7-10 MB86R01 lsi product specifications fujitsu semiconductor confidential interrupt controller (irc) 7.6.2. irq flag register (ir0irqf/ ir1irqf) ir0irqf/ir1irqf registers c ontrol irq interrupt flag. when interrupt level is higher than the one set in ir0ilm/ir1ilm registers as a result of determining irq interrupt source level, irqf bit is set and irq interrupt is asserted to arm core. the interruption to arm core is negated with "0" writing to the ir0irqf/ir1irqf registers. when irqf bit is set, interrupt vector is displaye d to ir0vct/ir1vct registers but its address value is not changed until irqf bit is set. address irc0: ffff_fe00 h or fffe_8000 h + 00 h irc1: fffb_0000 h + 00 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? irqf r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x 0 bit field no. name description 31-1 ? unused bit. the write access is ignored. the read value of these bits is undefined. 0 irqf irq interrupt flag. when interrupt level is higher than the one set in ir0ilm/ir1ilm registers (interrupt level in ir0icr/ir1icr registers > interrupt level in ir0ilm/ir1ilm registers), irqf bit is set to "1" and irqx (interrupt request) is asserted to arm core. 0 irq is not asserted. 1 irq is asserted. this bit is cleared by writing "0", and writing "1" is invalid.
7-11 MB86R01 lsi product specifications fujitsu semiconductor confidential interrupt controller (irc) 7.6.3. irq mask register (ir0irqm/ir1irqm) ir0irqm/ir1irqm registers control masking asserted irq interrupt. address irc0: ffff_fe00 h or fffe_8000 h + 04 h irc1: fffb_0000 h + 04 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? irqm r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x 0 bit field no. name description 31-1 ? unused bit. the write access is ignored. the read value of these bits is undefined. 0 irqm asserted irq interrupt is masked. 0 asserted irq is masked 1 asserted irq is valid this bit is initialized to "0" by reset.
7-12 MB86R01 lsi product specifications fujitsu semiconductor confidential interrupt controller (irc) 7.6.4. interrupt level mask register (ir0ilm/ir1ilm) ir0ilm/ir1ilm registers set interrupt level enabled by the arm core. when the irq interrupt source is larger than the setting value of this register, irc notifies the arm core of the irq interrupt. "interrupt level of ir0icr/ir1icr registers > interrupt enable level of ir0ilm/ir1ilm registers" -> generated irq interrupt address irc0: ffff_fe00 h or fffe_8000 h + 08 h irc1: fffb_0000 h + 08 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ? ? ? ? ? ? ? ? ? ? ? ? ilm3 ilm2 ilm1 ilm0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x 1 1 1 1 bit field no. name description 31-4 ? unused bit. the write access is ignored. the read value of these bits is undefined. 3-0 ilm3-0 these bits are used to set irq interrupt mask level. its range is from 0000 b the highest to 1111 b the lowest. when 0000 b (highest level) is set, all interrupt requests are masked. these bits are initialized to 1111 b by reset.
7-13 MB86R01 lsi product specifications fujitsu semiconductor confidential interrupt controller (irc) 7.6.5. icr monitoring register (ir0icrmn/ir1icrmn) ir0icrmn/ir1icrmn registers display interrupt level of the current irq interrupt source. if irq interrupt source is less than th e setting value of these registers, 1111 b is displayed, and for the case that irq interrupt transmission source is larger than the setting value, the highest interrupt source level is displayed. these registers are updated with setting irqf bit of ir0irqf/ir1irqf "1", and displayed interrupt level is not changed until irqf bit is cleared. after it is cleared, interrupt level is set again and the display is updated with the source set the irqf bit. register value is not defined if the bit is not set to "1". address irc0: ffff_fe00 h or fffe_8000 h + 0c h irc1: fffb_0000 h + 0c h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ? ? ? ? ? ? ? ? ? ? ? ? icrmn3 icrmn2 icrmn1 icrmn0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x x bit field no. name description 31-4 ? unused bit. the write access is ignored. the read value of these bits is undefined. 3-0 ilm3-0 when irq interrupt source is larger than the setting value of ir0ilm/ir1ilm registers, the highest interrupt source level is displayed. the initial value of these bits is undefined.
7-14 MB86R01 lsi product specifications fujitsu semiconductor confidential interrupt controller (irc) 7.6.6. delay interrupt control register 0 (ir0dicr0) ir0dicr0 register controls delay interrupt for the task switch. writing to this register enables software to issue/cancel irq interrupt request. the delay interrupt is allocated into irq30 of irc0. address irc0: ffff_fe00 h or fffe_8000 h + 14 h irc1: reserved area fffb_0000 h + 14 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dlyi0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x 0 bit field no. name description 31-1 ? unused bit. the write access is ignored. the read value of these bits is undefined. 0 dlyi0 delay interrupt is controlled. it is cancelled by writing "0" to this bit. 0 delay interrupt factor is cancelled and interrupt request does not occur. 1 delay interrupt factor is generated and interrupt request occurs. this bit is initialized to "0" by reset.
7-15 MB86R01 lsi product specifications fujitsu semiconductor confidential interrupt controller (irc) 7.6.7. delay interrupt control register 1 (ir0dicr1) writing to ir0dicr1 register enables softwa re to issue/cancel fiq interrupt request. the delay interrupt is allocated into fiq of the arm. address irc0: ffff_fe00 h or fffe_8000 h + 18 h irc1: reserved area fffb_0000 h + 18 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dlyi1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x 0 bit field no. name description 31-1 ? unused bit. the write access is ignored. the read value of these bits is undefined. 0 dlyi1 delay interrupt is controlled. it is cancelled by writing "0" to this bit. 0 delay interrupt factor is cancelled but interrupt request does not occur 1 delay interrupt factor is generated and interrupt request occurs this bit is initialized to "0" by reset.
7-16 MB86R01 lsi product specifications fujitsu semiconductor confidential interrupt controller (irc) 7.6.8. table base register (ir0tbr/ir1tbr) ir0tbr/ir1tbr registers indicate upp er address (24 bit) of irq v ector. when irc receives irq interrupt source, and irq is asserted to the arm co re, the address displayed in ir0vct/ir1vct registers are as follows. (ir0tbr/ir1tbr setting value) + individual irq interrupt source vector address address irc0: ffff_fe00 h or fffe_8000 h + 1c h irc1: fffb_0000 h + 1c h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name tbr31 tbr30 tbr29 tbr28 tbr27 tbr26 tbr25 tbr24 tbr23 tbr22 tbr21 tbr20 tbr19 tbr18 tbr17 tbr16 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tbr15 tbr14 tbr13 tbr12 tbr11 tbr10 tbr9 tbr8 zero zero zero zero zero zero zero zero r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-8 tbr31-8 set upper address (24 bit) of irq vector. these bits are initialized to "0" by reset. 7-0 zero "0" fixed bit. writing is invalid and "0" is always read in the read value. these bits are initialized to "0" by reset.
7-17 MB86R01 lsi product specifications fujitsu semiconductor confidential interrupt controller (irc) 7.6.9. interrupt vector register (ir0vct/ir1vct) ir0vct/ir1vct registers display interrupt vector table to the interrupt source to be processed when irq is asserted to arm core ("1" is set to irqf bit of ir0irqf/ir1irqf registers.) the priority of vector address is as follows. ? the highest interrupt source vector level in the generated irq interrupt source has higher priority ? when interrupt of same level and transmission sour ce occurs at the same time, the one with less address offset valu e is prioritized address irc0: ffff_fe00 h or fffe_8000 h + 20 h irc1: fffb_0000 h + 20 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name vct31 vct30 vct29 vct28 vct27 vct26 vct25 vct24 vct23 vct22 vct21 vct20 vct19 vct18 vct17 vct16 r/w r r r r r r r r r r r r r r r r initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vct15 vct14 vct13 vct12 vct11 vct10 vct9 vct8 vct7 vct6 vct5 vct4 vct3 vct2 vct1 vct0 r/w r r r r r r r r r r r r r r r r initial value x x x x x x x x x x x x x x x x bit field no. name description 31-0 vct31-0 interrupt vector table is displaye d to the interrupt source to be processed. the value adding each interrupt factor?s offset value to upper address value set by ir0tbr/ir1tbr registers is displayed as vector value. refer to " table 7-2 expansion irq interrupt vector of irc0" and " table 7-3 extension irq interrup t vector of irc1" for correlation of inte rrupt source, interrupt level register, and vector address. the initial value of these bits is undefined. after irqf bit of ir0irqf/ir1irqf registers is set to "1", the displayed vector address value is not changed until the irqf bit is cleared. when the bit is cleared, interrupt level is set again and the display is updated by the source that sets the irqf bit. regist er value is not defined if the bit is not set to "1". firmware branches into the address specified by vct register (branched to extension vector table) with the instruction in irq vector (0000_0018 h ). then it branches into interrupt handler by the instruction on the address. if irqf bit is cleared after the branch , asserting irq enables to observe whether new irq source is higher than the current one in the interrupt handler.
7-18 MB86R01 lsi product specifications fujitsu semiconductor confidential interrupt controller (irc) 7.6.10. interrupt control register (ir0icr31/ir1icr31 ? ir0icr00/ir1icr00) ir0icr31/ir1icr31 C ir0icr00/ir1icr00 registers are supplied to each irq interrupt source, and are able to set interrupt level to the corresponding irq in terrupt source. when irq interrupt source is larger than the setting value of ir0ilm/ir1ilm registers (interrupt level of ir0icrn/ir1icrn registers <= interrupt level of ir0ilm/ir1ilm registers), it is masked. address irc0: ffff_fe00 h or fffe_8000 h + 30 h | ffff_fe00 h or fffe_8000 h + ac h irc1: fffb_0000 h + 30 h | fffb_0000 h + ac h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ? ? ? ? ? ? ? ? ? ? ? ? icr3 icr2 icr1 icr0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x 1 1 1 1 bit field no. name description 31-4 ? unused bit. the write access is ignored. the read value of these bits is undefined. 3-0 icr3-0 these bits are used to set interrupt leve l value of each interrupt source. its range is from "0000 b " the highest to "1111 b " the lowest. icr3 icr3 icr1 icr0 interrupt level 0 0 0 0 settable highest level 0 0 0 1 (highest) 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 (lowest) 1 1 1 1 uninterruptible these bits are initialized to " 1111 b " by reset.
7-19 MB86R01 lsi product specifications fujitsu semiconductor confidential interrupt controller (irc) 7.7. operation this section describes irc operation. 7.7.1. outline interrupt operation process is described with using irq24 interrupt as an example. 1. when irq interrupt is asserted to arm core as a result of prioritization of irq24 interrupt source with interrupt controller, the arm core refers instruction of vector address 0000_0018 h. 2. loading instruction, ldr pc, [pc, #_0200] is written to vector table address 0000_0018 h beforehand. then extension interruption vector address of irq24 (vct register value) is loaded into pc, and the arm core refers irq24 vector address of extension interrupt vector table. 3. branch instruction to the irq24 interrupt handle r should be written to irq24 extension interrupt vector address. then pc branches into the irq2 4 interrupt handler with the branch instruction. all interrupt handlers should be set within 32mb of the extension interrupt vector table in order to use the branch instruction. if the handler is unable to be set in the range, use load instruction, ldr pc, [pc, #_0x200] instead. ldr pc,[pc, #-0x200] 00000080 h irq24 interrupt handler b irq24 handler 00000018 h fffffe20 h irq vector reference ir0vct register extended interrupt vector table 00000080 h figure 7-2 irq24 interrupt process example 7.7.2. initialization 1. determine individual exception table after power-on. 2. set extension interrupt vector table. 3. store load instruction, ldr pc, [pc, #_0x200] to irq vector (00000018 h ) in the arm core. 4. set base address of the interrupt table to ir0tbr register. 5. set interrupt level of each interrupt source to ir0icr31 - 00 registers. 6. set interrupt level that irq interrupt becomes valid to the ir0ilm register. 7. set i flag of cpsrs register in the arm core to "0" (to validate irq.) 8. validate interrupt with ir0irqm register in irc.
7-20 MB86R01 lsi product specifications fujitsu semiconductor confidential interrupt controller (irc) 7.7.3. multiple interrupt process example of multiple interrupt process is shown below. m ain routine irq request 1 1st interrupt process (1) save register value to stack (2) save current ir0ilm register value and spsr_irq (in the core) register value to stack not to lose them at the next interrupt process (3) s et ir 0ic r m n register value to ir 0ilm register, and validate higher level interrupt than the first interrupt (4) clear the interrupt source currently occurred (5) clear irqf flag (then nirq is negated and determ ining interrupt level is restarted) (6) c onfirm ir q flag is cleared (7) c lear i bit to c p s r register of the a r m core to be ready for interrupt reception irq request 2 return process of 1st interrupt process proceed the same return process as the 2nd one 2nd interrupt process p roceed the sam e interrupt process as the 1st one return process of 2nd interrupt process (1) set i bit of cpsr register and disable interrupt (2) restore saved spsr_irq value to spsr_irq register (3) restore the value on stack to register (4) restore pc value to go back to the regular routine, and restore the register value to cpsr as well cpsr spsr_irq figure 7-3 example of multiple irq interrupt process 7.7.4. example of irq interrupt handler irq_handler rout stmfd sp!, {r0-r12, r14} ;save register value message "enter dummy irq handler" ldr r0, = ir0ilm ldr r1, [r0] mrs r2, spsr stmfd sp!, {r1, r2} ;ir0ilm and spsr_irq register values are saved ldr r2, = ir0icrmn ldr r1, [r2] str r1, [r0] ;ir0icrmn register value is set to ir0ilm register
7-21 MB86R01 lsi product specifications fujitsu semiconductor confidential interrupt controller (irc) routine to clear interrupt factor mov r1, #0 ldr r0, = ir0irqf str r1, [r0]; ;clear irqf bit (bit 0) of ir0irqf register ;start the next inte rrupt level setting operation. loop ldr r1,[r0] ;check irqf flag clear cmp r1,#0 bne loop ;; clear arm irq flag enable interrupt mrs r2, cpsr bic r2, r2, #i_bit msr cpsr_c, r2; ;clear i bit of cpsr register (included in the core) and validate irq interrupt (enable) if the irq interrupt higher than the current irq source occurs, move to the corresponding interrupt handler. main routine for this interrupt factor mrs r2, cpsr orr r2, r2 #1_bit msr cpsr_c, r2; ;set i bit of cpsr register (included in the core) and invalidate irq interrupt (disable) ldr r0, = ir0ilm ldmfd sp!, {r1, r2} msr spsr_cxsf, r2 str r1, [r0]; ;resume saved value in ir0ilm and spsr_irq registers (included in the core) ldmfd sp! {r0-r12, r14}; ;resume register value subs pc, r14, #4; ;cpsr < - spsr_irq, pc < - r14 ?4
7-22 MB86R01 lsi product specifications fujitsu semiconductor confidential interrupt controller (irc) 7.7.5. resume from stop and standby modes resume from stop and standby modes is able to be instructed to crg (clock reset controller) with issuing irq interrupt from macro. the resume signal from stop and standby modes, asserted to arm clock controller is generated by higher irq factor than the interrupt leve l set with ir0ilm register (see figure 7-1.) 7.7.6. notice for using irc notice for using irc is shown below. notice for irq clear timing as described in " 7.6.2 irq flag register (ir0irqf/ ir1irq f)", "0" writing to irqf bit of ir0irqf/ir1irqf registers negates irqx (interrupt request) to th e arm core; however, irqx is negated during 1 cycle of apb clock after writing "0". therefore, the arm core may wrongly goes into irq mode again by the irqx before clear operation if the code (interrupt handler) which may validate arm core interrupt again is written after "0" writing to the irqf. this might occurs especially when arm core?s cl ock frequency is faster than the irc frequency. in order to prevent such problem, add dummy instruction wh ich accesses to irc interrupt register after clear instruction of irqf. in this way, irqx is cleared properly before in terrupt of the arm core becomes valid again.
8-1 MB86R01 lsi product specifications fujitsu semiconductor confidential external bus interface 8. external bus interface this chapter describes external bus of MB86R01. 8.1. outline MB86R01 has external bus interface for accessing to external memory device such as sram and flash. 8.2. spec limitation external bus interface supports 8 chip selects (cs0-7). however, only cs0, cs2, and cs4, which have external pin (mem_xcs[0/2/4]) are able to be used. the others (cs1, cs3, cs5, cs6, cs7) are not usable since they do not have external pin. while external bus interface is able to use cs0/2/ 4 chip selects, address area for other chip selects (cs1/3/5/6/7) are allocated in lsi during initialization (see figure 8-1.) 0x1100_0000 cs1 0x1000_0000 0x0f00_0000 0x0e00_0000 0x0d00_0000 0x0c00_0000 0x0b00_0000 0x0a00_0000 0x0900_0000 0x0800_0000 0x0700_0000 cs7 0x0600_0000 cs6 0x0500_0000 cs5 0x0400_0000 reserved under initialing 0x0300_0000 cs3 0x0200_0000 cs1: 0x1100_0000-0x11ff_ffff (16mb) cs3: 0x0300_0000-0x03ff_ffff (16mb) cs5: 0x0500_0000-0x05ff_ffff (16mb) cs6: 0x0600_0000-0x06ff_ffff (16mb) cs7: 0x0700_0000-0x07ff_ffff (16mb) figure 8-1 initialization value of chip select ion address area (except cs0/2/4) valid in lsi
8-2 MB86R01 lsi product specifications fujitsu semiconductor confidential external bus interface if address area of cs0/2/4 and cs1/3/5/6/7 is overlapped, cs0/2/4 signals (mem_xcs[0/2/4] pin output) may not be asserted correctly. therefore, perform in itial setting shown in the next page for using external bus interface. initial setting for using external bus interface cs1/3/5/6/7 address areas should be set out of cs0/2/4 address areas with sram/flash area register 1/3/5/6/7 (mcfarea1/3/5/6/7.) (see table 8-1.) table 8-1 cs1/3/5/6/7 sram/flash area register 1/3/5/6/7 address and recommended setting value sram/flash area register chip select abbreviation address recommended setting value (note) cs1 mcfarea1 0xfffc0044 0x0000001f cs3 mcfarea3 0xfffc004c 0x0000001f cs5 mcfarea5 0xfffc0054 0x0000001f cs6 mcfarea6 0xfffc0058 0x0000001f cs7 mcfarea7 0xfffc005c 0x0000001f note) since cs1/3/5/6/7 are unable to be used, the same address area is settable. 0x11ff ffff | 0x11f0 0000 cs1, cs3, cs5, cs6, cs7 set cs1/3/5/6/7 area out of cs0/2/4 address areas 0x1100_0000 0x1000_0000 0x0f00_0000 0x0e00_0000 0x0d00_0000 0x0c00_0000 0x0b00_0000 0x0a00_0000 0x0900_0000 0x0800_0000 0x0700_0000 0x0600_0000 0x0500_0000 0x0400_0000 0x0300_0000 0x0200_0000 figure 8-2 cs1/3/5/6/7 address areas this initial setting enables cs0/2/4 address areas setting in 0x0200_0000 - 0x11ef_ffff. for 0x1000_0000 - 0x10ff_ffff (external boot rom), address area is fixed in cs4. remarks: cs1/3/5/6/7 address areas are able to set other values than the one indicated in table 8-1; in this case, make sure that address area of cs0/2/4 and cs1/3/5/6/7 addresses are not overlapped.
8-3 MB86R01 lsi product specifications fujitsu semiconductor confidential external bus interface 8.3. feature external bus interface of mb86r0 1 has the following features. ? supporting 16/32 bit (32 bit is an option) width of sram/flash ? 3 chip selects for sram/flash (mem_xcs[4] is for boot operation). ? parameter setting by individual chip select for sram/flash ? supporting nor flash page access ? supporting bi-endian 8.4. block diagram figure 8-3 shows block diagra m of external bus interface. ccpb a hb bus external bus i/f a hb i/f switcher mem_rdy mem_xcs[4/2/0] mem_xrd mem_ea[24:1] (mem_xwr[3:2]) mem_xwr[1:0] (mem_ed[31:16]) mem_ed[15:0] mpx_mode_1[1:0] bigend MB86R01 figure 8-3 block diagram of external bus interface part
8-4 MB86R01 lsi product specifications fujitsu semiconductor confidential external bus interface 8.5. related pin table 8-2 external interface related pin pin i/o no. of pin function mem_ea[24:1] o 24 address bus mem_xwr[3:0] o 4 writing enabled upper 2 bits are multiplexed pin mem_xrd o 1 reading enabled mem_xcs[4] o 1 chip select for boot operation mem_xcs[2] o 1 chip select mem_xcs[0] o 1 chip select mem_ed[31:0] io 32 data bus upper 16 bits are multiplexed pin mem_rdy i 1 ready input for low-speed device 8.6. supply clock ahb clock is supplied to external bus interface. re fer to "5. clock reset generator (crg)" for frequency setting and control specification of the clock.
8-5 MB86R01 lsi product specifications fujitsu semiconductor confidential external bus interface 8.7. register this section describes 32 bit width external bus i/f register. be sure to access to it in word (32 bit.) 8.7.1. sram/flash mode register 0-7 (mcfmode0-7) register address baseaddress+0x0000 mcfmode0 (external pin: mem_xcs[0]) baseaddress+0x0004 mcfmode1 external pin: n/a) (*1) baseaddress+0x0008 mcfmode2 (external pin:mem_xcs[2]) baseaddress+0x000c mcfmode3 (external pin: n/a) (*1) baseaddress+0x0010 mcfmode4 (external pin:mem_xcs[4]) baseaddress+0x0014 mcfmode5 (external pin: n/a) (*1) baseaddress+0x0018 mcfmode6 (external pin: n/a) (*1) baseaddress+0x001c mcfmode7 (external pin: n/a) (*1) bit no. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit field name reserved r/w r/w0 initial value x bit no. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved rdy page reserved wdth r/w r/w0 r/w r/w r/w0 r/w initial value x 0 0 x x x 0 (*2) *1: mcfmode1/3/5/6/7 are access prohibited *2: initial value of data width to mem_xcs[4] mpx_mode_1[1:0]=2?b01: 2:32 bit others: 1:16 bit bit31-7: reserved reserved bits. write "0" to these bits. their read value is undefined. bit6: rdy (ready mode) when handshake is performed with low-speed peripherals that use mem_rdy signal, set this bit to "1". rdy signal at reading should be asserted to "l" at least 2 cy cles from 2 cycles before falling edge of mem_xrd signal to actual falling edge. for the writing operation, the rdy signal should also be asserted to "l" at least 2 cycles from 2 cycles before falling edge of mem_xwr signal to actual falling edge. for accessing to device such as sram memory w ithout using the mem_rdy signal, this bit should be set to "0". 0: ready mode off (initial value) 1: ready mode on bit5: page (page access mode) nor flash page access mode this bit controls nor flash page access mode wh ich issues the first address cycle according to firstreadaddresscycle (fradc) se tting. then, the access is continuously executed according to read access cycle (racc) setting until it reaches to 16 byte boundary. in order to select this mode, set read address cycle (radc) to 0. 0: ready mode off (initial value) 1: ready mode on
8-6 MB86R01 lsi product specifications fujitsu semiconductor confidential external bus interface bit4-2: reserved reserved bits. write "0" to these bits. their read value is undefined. note: writing "1" to these bits are prohibited. bit1-0: wdth (data width) these bits specify data bit width of the connected device. 0: 8 bit (initial value) 1: 16 bit 2: 32 bit 3: reserved
8-7 MB86R01 lsi product specifications fujitsu semiconductor confidential external bus interface 8.7.2. sram/flash timing register 0-7 (mcftim0-7) register address baseaddress+0x0020 mcftim0 (external pin: mem_xcs[0]) baseaddress+0x0024 mcftim1 (external pin: n/a) (*1) baseaddress+0x0028 mcftim2 (external pin: mem_xcs[2]) baseaddress+0x002c mcftim3 (external pin: n/a) (*1) baseaddress+0x0030 mcftim4 (external pin: mem_xcs[4]) baseaddress+0x0034 mcftim5 (external pin: n/a) (*1) baseaddress+0x0038 mcftim6 (external pin: n/a) (*1) baseaddress+0x003c mcftim7 (external pin: n/a) (*1) bit no. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit field name widlc wwec wadc wacc r/w r/w initial value 0 5 5 15 bit no. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name ridlc fradc radc racc r/w r/w initial value 15 0 0 15 *1: mcftim1/3/5/6/7 are access prohibited bit31-28: widlc (write idle cycle: write idle cycle) these bits set the number of idle cycle after the write access. when rdy bit is set to "1", specify 2 or more value. 0 1 cycle (initial value) | | 15 16 cycles bit27-24: wwec (write enable cycle) these bits set the number of write enable asse rtion cycle. this setting also affects to mem_xwr[3:0]. when rdy bit is set to "1", the value should be 3 or more (4 cycles or more.) 0 1 cycle | | 5 6 cycles (initial value) | | 14 15 cycles 15 reserved bit23-20: wadc (write address setup cycle) these bits set number of write access setup cycle. address is output to the cycle; however, write enable is not asserted. when rdy bit is set to "1", the value should be 1 or more (2 cycles or more.) 0 1 cycle | | 5 6 cycles (initial value) | | 14 15 cycles 15 reserved
8-8 MB86R01 lsi product specifications fujitsu semiconductor confidential external bus interface bit19-16: wacc (write access cycle) these bits specify number of cy cle required for write access. the address does not change during the cycle specified in these bits. the wacc value should be larger than the total number of address setup cycle (wadc) and write enable cycle (wwec). twacc >= (twadc+twwec) when rdy bit is set to "1", the value should be 6 or more (7 cycles or more.) 0, 1 reserved 2 3 cycles | | 15 16 cycles (initial value) bit15-12: ridlc (read idle cycle) these bits set number of idle cycle after read access. they are used to pr event data collision that occurs by write access immediately after the read access. 0 1 cycle | | 15 16 cycles (initial value) bit11-8: fradc (first read address cycle) these bits are exclusive use for nor flash setting that corresponds to page mode access, and are set initial latency in the address of flash read access. the address is retained with number of cycle specified by these bits only at the first read access. the subsequent read access is executed according to the number of cycle set in the racc. mem_xcs[0/2/4] and mem_xrd are asserted simultaneously. when other values than 0 are set to these bits, specify "0" to radc (rea d address setup cycle.) 0 0 cycle (initial value) | | 15 15 cycles bit7-4: radc (read address setup cycle) these bits set number of read address setup cycle which asserts mem_xcs[0/2/4] and its address but not mem_xrd. when 0 is selected, mem_xrd and mem_xcs[0/2/4] are asserted simultaneously. the specifying value should be within number of the read access setup cycle. when nor flash page access mode is applied, set these bits to "0". when rdy bit is set to "1", the value should be 3 or more (3 cycles or more.) 0 0 cycle (initial value) | | 15 15 cycles bit3-0: racc (rea d access cycle) these bits set number of cycle required for the re ad access. although the address does not change during the cycle specified by these bits , data is fetched at the last cycle. when rdy bit is set to "1", the value should be 3 or more (4 cycles or more.) 0 1 cycle | | 15 16 cycles (initial value)
8-9 MB86R01 lsi product specifications fujitsu semiconductor confidential external bus interface 8.7.3. sram/flash area register 0-7 (mcfarea0-7) register address baseaddress+0x0040 mcfarea0 (external pin: mem_xcs[0]) baseaddress+0x0044 mcfarea1 (external pin: n/a) (*1) baseaddress+0x0048 mcfarea2 (external pin: mem_xcs[2]) baseaddress+0x004c mcfarea3 (external pin: n/a) (*1) baseaddress+0x0050 mcfarea4 (external pin: mem_xcs[4]) baseaddress+0x0054 mcfarea5 (external pin: n/a) (*1) baseaddress+0x0058 mcfarea6 (external pin: n/a) (*1) baseaddress+0x005c mcfarea7 (external pin: n/a) (*1) bit no. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit field name reserved mask r/w r/w0 r/w initial value x 15 (16mb width) bit no. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved addr r/w r/w0 r/w initial value x (in order of mem_xcs[0/2/4]) 64,32,0 *1: this must set not to overlap addre ss area of cs0/2/4 and cs1/3/5/6/7 (refer 8.2 spec limitation) bit31-23: reserved reserved bits. write "0" to these bits. their read value is undefined. bit22-16: mask (address mask) these bits set mask value of the one set to addr. this external bus interface masks addr (masked with setting "1") and internal bus mask ad dress according to the specified mask to compare them. when they are matched, external bus interface accesses to mem_xcs[4/2/0] signal. [22:16] masks each address [26:20]. (example) addr = 00001000 (b) mask = 0000011 (b) internal bus address (external interface address): ad = 0x10900000 mask addr & (!mask) = 00001000 (b) ad [27:20] & (!mask) = 00001000 (b) ?.. matched, and this device is selected internal bus address (external interface address): ad = 0x10c00000 masking addr & (!mask) = 00001000 (b) ad [27:20] & (!mask) = 00001100 (b) ?.. unmatched, and device is not selected
8-10 MB86R01 lsi product specifications fujitsu semiconductor confidential external bus interface the masking selects area size; in this exampl e, 0x10800000 - 0x10b00000 (4mb) are selected. the bit specified "1" with masking is lost during mask processing. these bits are invalid even if they are set to addr. when lsb in the example is 1 (addr = 00001001 (b)), the same address field is selected since it is invalid in masking. the correlation of the size in mask setting and address field is shown below. 0000000 (b) 1mb 0001111 (b) 16mb 0000001 (b) 2mb 0011111 (b) 32mb 0000011 (b) 4mb 0000111 (b) 8mb note: each address field must not overlapped. bit15-8: reserved reserved bits. write "0" to these bits. their value is undefined. bit7-0: addr (address) these bits specify setting address in the corres ponding chip select area. these addresses (0x0200_0000 - 0x11ff_ffff) are allocated by sram/flash interface in 256mb fixed area. define corresponding value to [27:20] part of the address. table 8-3 addr (address [27:20]) setting value and chip select area's setting address addr (address[27:20]) setting address of chip select area 0xff 0x0ff0_0000 (*1) 0xfe 0x0fe0_0000 (*1) ~ ~ 0x21 0x0210_0000 (*1) 0x20 0x0200_0000 (*1) 0x1f 0x11f0_0000 (*2) 0x1e 0x11e0_0000 (*2) ~ ~ 0x01 0x1010_0000 (*2) 0x00 0x1000_0000 (*2) *1: address becomes [31:28] = 0 0 at addr (address [27:20] = 20 - ff setting. *2: address becomes [31:28] = 0 1 at addr (address [27:20] = 00 - 1f setting.
8-11 MB86R01 lsi product specifications fujitsu semiconductor confidential external bus interface 8.7.4. memory controller error register (mcerr) register address baseaddress + 0x0200 bit no. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit field name reserved r/w r/w0 initial value x bit no. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved reserved sfion reserved sfer r/w r/w0 r/w0 r/w r r/w0 initial value x 0 0 0 0 bit31-4: reserved reserved bits. write "0" to these bits. their value is undefined. bit3: reserved reserved bit. write "0" to this bit. its value is undefined. note: writing "1" to this bit is prohibited. bit2: sfion (sram/flash error interrupt: on) this bit validates interrupt at sram/flash error. 0: off (initial value) 1: on bit1: reserved reserved bit. write "0" to this bit. its value is undefined. bit0: sfer (sram/flash error) this bit indicates that the area without mapping is accessed. in this case, memory controller returns error to internal bus; at the same time, this bit, is set. when the value is "1", it is cleared by writing "0" on ly when "1" is set to this bit, clear operation is available. 0: no error (initial value) 1: error
8-12 MB86R01 lsi product specifications fujitsu semiconductor confidential external bus interface 8.8. connection example 16 bit nor flash figure 8-4 connection example of 16 bit nor flash 16 bit nor flash + 8 bit sram 2 figure 8-5 connection example of 16 bit nor flash + 8 bit sram 2 MB86R01 mem_ea[24:1] mem_xcs[4] mem_xrd mem_xwr[0] mem_ed[15:0] x16 nor flash a xce xoe xwe dq[15:0] MB86R01 x8 sram x8 sram mem_ed[7:0] mem_ed[15:8] mem_ea[24:1] mem_xcs[0] mem_xrd mem_xwr[1:0] mem_ed[15:0] mem_xcs[4] mem_xwr[0] mem_xwr[1] a csn oen wen d q[ 7:0 ] a csn oen wen dq[7:0] x16 nor flash a xce xoe xwe dq[15:0] mem_xwr[0] mem_ed[15:0]
8-13 MB86R01 lsi product specifications fujitsu semiconductor confidential external bus interface 32 bit nor flash figure 8-6 connection example of 32 bit nor flash MB86R01 mem_ea[24:2] mem_xcs[4] mem_xrd mem_xwr[2] mem_ed[31:16] mem_xwr[0] mem_ed[15:00] mpx_mode_1[0] mpx_mode_1[1] x16 nor flash a[22:0] xce xoe xwe dq[15:0] x16 nor flash a[22:0] xce xoe xwe dq[15:0] mpx_mode_1[1:0]=2?b01
8-14 MB86R01 lsi product specifications fujitsu semiconductor confidential external bus interface 8.9. example of access waveform word read access to 16 bit width sram/nor flash 01 x d01 mem_ea[24:1] 00 d00 x mem_ed[15:0] mem_xrd mem_xwr[1:0] mem_xcs[4/2/0 ] internal clock mem_rdy tracc + tracc cycle tradc = read address setup cycle tradc tracc = read access cycle tradc tridlc tridlc = read idle cycle figure 8-7 access waveform example (word read access to 16 bit width sram/nor flash) word write access to 16 bit width sram/nor flash 01 x d01 mem_ea[24:1] 00 d00 x mem_ed[15:0] mem_xrd mem_xwr[1:0] mem_xcs[4/2/0 ] internal clock mem_rdy twadc = write address setup cycle twadc twacc = write access cycle twadc twidlc twwec = write enable cycle twwec x twwec twidlc = write idle cycle 1 cycle 1 cycle 1 cycle twacc twacc twadc figure 8-8 access waveform example (word write access to 16 bit width sram/nor flash)
8-15 MB86R01 lsi product specifications fujitsu semiconductor confidential external bus interface read/write to low-speed device figure 8-9 access waveform example (half-word read access to 16 bit width low speed device) figure 8-10 access waveform example (half-word write access to 16 bit width low speed device)
8-16 MB86R01 lsi product specifications fujitsu semiconductor confidential external bus interface figure 8-11 access waveform example (word read access to 16 bit width low speed device) figure 8-12 access waveform example (word wr ite access to 16 bit width low speed device)
8-17 MB86R01 lsi product specifications fujitsu semiconductor confidential external bus interface page read of 16 bit nor flash figure 8-13 access waveform example (16 bit nor flash page read)
8-18 MB86R01 lsi product specifications fujitsu semiconductor confidential external bus interface 8.10. operation external bus interface equips 3 chip select signals and controls sram and flash. 8.10.1. external bus interface this interface has 256mb address space that each address is able to be set arbitrarily (actual max. address size is 32mb with taking bit width of external output address into account.) different timing is able to be set to each chip sel ect. nor flash is connectable and it accesses in normal sram access. in sram access, mem_xcs[4/2/ 0] is selected at 1 access. when access is performed with wider bit width than the target?s, it is converted to continuous access. in continuous access, mem_xc s[4/2/0] is fixed to l and address is changed. for instance, the case that 32 bit read access is proceeded from intern al bus to 16 bit width device, address is changed from 0 to 2, and the data is continuo usly fetched from mem_ed [15:0] according to the transition timing while mem_xcs[4/2/0] is fixed to l (refer to " 8.9 example of access waveform".) th en the data suited to endian is returned to the internal bus. when access is proceeded with narrower bit width than the target?s (for instance, the byte access to 16 bit target), byte access is carried out with mem_xwr[ 3:0] signal control during writing operation (for external bus interface, only necessary data is output.) 8.10.2. low-speed device interface function the external bus interface has interface function with low-speed device and mem_rdy pin which are used by connecting rdy signal to mem_rdy pin of this lsi. mem_rdy pin is available only when wait state is at l and ready state is at h. rdy signal at reading should be asserted to "l" at least 2 cycles from 2 cycles before falling edge of mem_xrd signal to actual falling edge. for the writing operation, the rdy signal should also be assert ed to "l" at least 2 cycles from 2 cycles before falling edge of mem_wxr signal to actual falling edge. for the access exceeding external data bus width (e.g. wo rd (32 bit) access to 16 bit device), the access is carried out "read read, write write" continuously until all exceeded bits are covered. in this case, mem_xcs[4/2/0] signal is not negated during the access regardless of setting. when the device using negation of mem_xcs[4/2/0] signal, the access sh ould be done with in the target width. for the device without using rdy function (e.g. sram memory), be sure to set "0" to rdy bit of applied chip select. when rdy signal is h from the access start, the access is carried out in the same method as normal sram access. if rdy becomes l or high pulse during access cycle, the operation is not assured. * this function cannot be applied to the rdy/busy signals of the flash memory.
8-19 MB86R01 lsi product specifications fujitsu semiconductor confidential external bus interface 8.10.3. endian and byte lane to each access the external bus interface corresponds to both little endian and big endian. these switches are set with external pin, bigend. external data bus width is set with external pin, mpx_mode_1[1:0]. correlation of each endian, external data bus widt h, and byte lane to each access is shown below. table 8-4 relation of by te lane at little endian mem_ed[7:0] 1 st : h*data [ 7:0 ] 0 mem_ed[7:0] 2 nd : h*data [ 15:8 ] 0 mem_ed[7:0] 3 rd : h*data [ 23:16 ] 1 mem_ed[7:0] 4 th : h*data [ 31:24 ] 1 mem_ed[15:0] 1 st : h*data [ 15:0 ] 0 mem_ed[15:0] 2 nd : h*data [ 31:16 ] 1 32bit(prohibited) - - - - - - mem_ed[7:0] 1 st : h*data [ 7:0 ] 0 mem_ed[7:0] 2 nd : h*data [ 15:8 ] 0 mem_ed[7:0] 3 rd : h*data [ 23:16 ] 1 mem_ed[7:0] 4 th : h*data [ 31:24 ] 1 mem_ed[15:0] 1 st : h*data [ 15:0 ] 0 mem_ed[15:0] 2 nd : h*data [ 31:16 ] 1 32bit 0 mem_ed[31:0] h*data[31:0] 00 00 0 mem_ed[7:0] 1 st : h*data [ 7:0 ] 0 mem_ed[7:0] 2 nd : h*data [ 15:8 ] 0 mem_ed[7:0] 1 st : h*data [ 23:16 ] 1 mem_ed[7:0] 2 nd : h*data [ 31:24 ] 1 0 mem_ed[15:0] h*data[15:0] not active 00 0 2 mem_ed[15:0] h*data[31:16] not active 00 1 32bit(prohibited) - - - - - - mem_ed[7:0] 1 st : h*data [ 7:0 ] 0 mem_ed[7:0] 2 nd : h*data [ 15:8 ] 0 mem_ed[7:0] 1 st : h*data [ 23:16 ] 1 mem_ed[7:0] 2 nd : h*data [ 31:24 ] 1 0 mem_ed[15:0] h*data[15:0] not active 00 0 2 mem_ed[15:0] h*data[31:16] not active 00 1 0 mem_ed[15:0] h*data[15:0] 11 00 0 2 mem_ed[31:16] h*data[31:16] 00 11 0 0 mem_ed[7:0] h*data[7:0] not active 10 0 1 mem_ed[7:0] h*data[15:8] not active 10 0 2 mem_ed[7:0] h*data[23:16] not active 10 1 3 mem_ed[7:0] h*data[31:24] not active 10 1 0 mem_ed[7:0] h*data[7:0] not active 10 0 1 mem_ed[15:8] h*data[15:8] not active 01 0 2 mem_ed[7:0] h*data[23:16] not active 10 1 3 mem_ed[15:8] h*data[31:24] not active 01 1 32bit(prohibited) - - - - - - 0 mem_ed[7:0] h*data[7:0] not active 10 0 1 mem_ed[7:0] h*data[15:8] not active 10 0 2 mem_ed[7:0] h*data[23:16] not active 10 1 3 mem_ed[7:0] h*data[31:24] not active 10 1 0 mem_ed[7:0] h*data[7:0] not active 10 0 1 mem_ed[15:8] h*data[15:8] not active 01 0 2 mem_ed[7:0] h*data[23:16] not active 10 1 3 mem_ed[15:8] h*data[31:24] not active 01 1 0 mem_ed[7:0] h*data[7:0] 11 10 0 1 mem_ed[15:8] h*data[15:8] 11 01 0 2 mem_ed[23:16] h*data[23:16] 10 11 0 3 mem_ed[31:24] h*data[31:24] 01 11 0 endian (bigend) access size mpx_mode_ 1[1:0] internal bus address target width (wdth) corresponding internal bus data mem_ea[1] mem_xwr [1:0] 10 10 word mem_xwr [3:2] enabled byte lane 16bit 16 bit ( 2?b01) 32 bit (=2?b01) 8bit 32bit 16 bit ( 2?b01) not active 00 10 not active 8bit 0 not active 0n o t a c t i v e 8bit 0 10 10 half-word 00 16 bit ( 2?b01) 32 bit (=2?b01) not active 8bit 0 10 16bit 0 byte 0 2 16bit not active not active not active 2 16bit 8bit 16bit 32 bit (=2?b01) 8bit 16bit 32bit little (=1'b0) h*data: hwdata or hrdata is internal signals not active
8-20 MB86R01 lsi product specifications fujitsu semiconductor confidential external bus interface table 8-5 relation of byte lane at big endian mem_ed[15:8] 1 st : h*data [ 31:24 ] 0 mem_ed[15:8] 2 nd : h*data [ 23:16 ] 0 mem_ed[15:8] 3 rd : h*data [ 15:8 ] 1 mem_ed[15:8] 4 th : h*data [ 7:0 ] 1 mem_ed[15:0] 1 st : h*data [ 31:16 ] 0 mem_ed[15:0] 2 nd : h*data [ 15:0 ] 1 32bit(prohibited) - - - - - - mem_ed[15:8] 1 st : h*data [ 31:24 ] 0 mem_ed[15:8] 2 nd : h*data [ 23:16 ] 0 mem_ed[15:8] 3 rd : h*data [ 15:8 ] 1 mem_ed[15:8] 4 th : h*data [ 7:0 ] 1 mem_ed[15:0] 1 st : h*data [ 31:16 ] 0 mem_ed[15:0] 2 nd : h*data [ 15:0 ] 1 32bit 0 mem_ed[31:0] h*data[31:0] 00 00 0 mem_ed[15:8] 1 st : h*data [ 31:24 ] 0 mem_ed[15:8] 2 nd : h*data [ 23:16 ] 0 mem_ed[15:8] 1 st : h*data [ 15:8 ] 1 mem_ed[15:8] 2 nd : h*data [ 7:0 ] 1 0 mem_ed[15:0] h*data[31:16] not active 00 0 2 mem_ed[15:0] h*data[15:0] not active 00 1 32bit(prohibited) - - - - - - mem_ed[15:8] 1 st : h*data [ 31:24 ] 0 mem_ed[15:8] 2 nd : h*data [ 23:16 ] 0 mem_ed[15:8] 1 st : h*data [ 15:8 ] 1 mem_ed[15:8] 2 nd : h*data [ 7:0 ] 1 0 mem_ed[15:0] h*data[31:16] not active 00 0 2 mem_ed[15:0] h*data[15:0] not active 00 1 0 mem_ed[31:16] h*data[31:16] 00 11 0 2 mem_ed[15:0] h*data[15:0] 11 00 0 0 mem_ed[15:8] h*data[31:24] not active 01 0 1 mem_ed[15:8] h*data[23:16] not active 01 0 2 mem_ed[15:8] h*data[15:8] not active 01 1 3 mem_ed[15:8] h*data[7:0] not active 01 1 0 mem_ed[15:8] h*data[31:24] not active 01 0 1 mem_ed[7:0] h*data[23:16] not active 10 0 2 mem_ed[15:8] h*data[15:8] not active 01 1 3 mem_ed[7:0] h*data[7:0] not active 10 1 32bit(prohibited) - - - - - - 0 mem_ed[15:8] h*data[31:24] not active 01 0 1 mem_ed[15:8] h*data[23:16] not active 01 0 2 mem_ed[15:8] h*data[15:8] not active 01 1 3 mem_ed[15:8] h*data[7:0] not active 01 1 0 mem_ed[15:8] h*data[31:24] not active 01 0 1 mem_ed[7:0] h*data[23:16] not active 10 0 2 mem_ed[15:8] h*data[15:8] not active 01 1 3 mem_ed[7:0] h*data[7:0] not active 10 1 0 mem_ed[31:24] h*data[31:24] 01 11 0 1 mem_ed[23:16] h*data[23:16] 10 11 0 2 mem_ed[15:8] h*data[15:8] 11 01 0 3 mem_ed[7:0] h*data[7:0] 11 10 0 01 mem_ea[1] mem_xwr [1:0] not active 00 h*data: hwdata or hrdata is internal signals 32 bit (=2?b01) byte 16 bit ( 2?b01) 8bit 16bit 32 bit (=2?b01) half-word 16bit 32bit 01 big (=1'b1) 0n o t a c t i v e 01 8bit 32 bit (=2?b01) 16 bit ( 2?b01) 8bit enabled byte lane corresponding internal bus data mem_xwr [3:2] 01 not active 0 16 bit ( 2?b01) 8bit 0 internal bus address 16bit word not active 00 0 16bit 2 0 not active not active 01 01 16bit 8bit 0 2 not active not active 01 01 8bit 16bit 32bit endian (bigend) access size mpx_mode_ 1[1:0] target width (wdth)
9-1 MB86R01 lsi product specifications fujitsu semiconductor confidential ddr2 controller 9. ddr2 controller this chapter describes function and operation of ddr2 controller (ddr2c.) 9.1. outline ddr2c adopts ahb bus used in the register access as host if and axi bus used in the memory access. memory if supports ddr2sdram (ddr2-400.) 9.2. feature ddr2c has following features: a. ahb if a) register access by slave function of ahb if b) register setting contents a- operation setting of ddr2c b- initialization sequence control (ddr if macro setting, ocd/odt setting on ddr2c side, sdram initialization command issu e, and sdram control setting) b. axi if a) storing read/write transactions to inte rnal fifo by slave function of ahb if b) internal fifo composition a- address fifo: depth = 8 - 28 (controllable with register setting). b- write data fifo: depth = 52 c- read data fifo: depth = 62 d- read control fifo: depth = 28 c. dram if a) 512m bit/256m bit ddr2sdram (sstl1 8) 2pcs. (reco mmended) or 1pc. (ddr2-400/533/667/800 in compliance with jesd79-2c is used as ddr2-400; in addition, sdram with odt=50 setting is recommended.) b) switch of initialization mode and normal operation mode c) sdram usage restriction (al = 0, cl = 3, wl = 2, bl = 4, bank = 4) d) automatic issuing function of refresh command e) max. 166mhz of sdram clk (double edge: 333mhz)
9-2 MB86R01 lsi product specifications fujitsu semiconductor confidential ddr2 controller 9.3. block diagram figure 9-1 shows block diagram of ddr2 controller (ddr2c.) figure 9-1 block diagram of ddr2 controller (ddr2c) table 9-1 shows each function of the ddr2c block. table 9-1 individual block function block function ahb if ? slave function of ahb if ? control register. axi if ? slave function of axi if ? fifo control function fifo ? address/write ? data/read ? control/read ? data storage fifo dram if ? ddrif macro control function ? sdram if control function ddrif macro ? connection between dram if module and io (read data?s importing phase adjustment) ? built-in dll sstl_18 i/o ? stub series terminated logic for 1.8v si ngle end buffer (ocd and odt functions are embedded) ? stub series terminated logic for 1.8v di fferential buffer (ocd and odt functions are embedded) ? odt auto. adjustment function
9-3 MB86R01 lsi product specifications fujitsu semiconductor confidential ddr2 controller 9.4. supply clock ahb clock is supplied to ddr2 controller. refer to "5. clock reset generator (crg)" for frequency setting and control specification of the clock. 9.5. register this section describes ddr2 controller (ddr2c) register. 9.5.1. register list table 9-2 shows ddr2c register list. table 9-2 ddr2c register list address base offset register name abbreviation description f300_0000 h + 00 h dram initialization control register dric initialization control register + 02 h dram initialization command register [1] dric1 initialization control command register 1 + 04 h dram initialization command register [2] dric2 initialization control command register 2 + 06 h dram ctrl add register drca address control register + 08 h dram control mode register drcm mode control register + 0a h dram ctrl set time1 register drcst1 timing setting register 1 + 0c h dram ctrl set time2 register drcst2 timing setting register 2 + 0e h dram ctrl refresh register drcr refresh control register + 10 h - + 1f h (reserved) - access prohibited + 20 h dram ctrl fifo register drcf fifo control register + 22 h - + 2f h (reserved) - access prohibited + 30 h axi setting drasr axi operation setting register + 32 h - + 4f h (reserved) - access prohibited + 50 h dram if macro setting dll register drimsd ddrifmacro setting register + 52 h - + 5f h (reserved) - access prohibited + 60 h dram odt setting register dros odt setting register + 62 h - + 63 h (reserved) - access prohibited + 64 h io buffer setting odt1 dribs odt1 io odt1 setting register + 66 h - + 6f h (reserved) - access prohibited + 70 h odt auto bias adjust droaba odt bias self adjustment register + 72 h - + 83 h (reserved) - access prohibited + 84 h odt bias select register drobs odt bias selection register + 86 h - + 96 h (reserved) - access prohibited + 98 h ocd impedance setting register1 droisr 1 ocd impedance setting register 1 + 9a h ocd impedance setting register2 droisr 2 ocd impedance setting register 2
9-4 MB86R01 lsi product specifications fujitsu semiconductor confidential ddr2 controller description format of register following format is used for descri ption of register?s each bit in " 9.5.2 dram initialization control register (dric)" to " 9.5.18 ocd impedance setting register2 (droisr2)". address base address + offset bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r/w initial value bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r/w initial value meaning of item and sign address address (base address + offset address) of the register bit bit number of the register name bit field name of the register r/w attribution of read/write of each bit field ? r0:read value is always "0" ? r1: read value is always "1" ? w0: write value is always "0", and write access of "1" is ignored ? w1: write value is always "1", and write access of "0" is ignored ? r: read ? w: write initial value each bit field?s value after reset ? 0: value is "0" ? 1: value is "1" ? x: value is undefined
9-5 MB86R01 lsi product specifications fujitsu semiconductor confidential ddr2 controller 9.5.2. dram initialization control register (dric) dric register is used to initialize dram; in addition, it controls initialization mode setting, issue of initialization command, and others. address f300_0000 h + 00 h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name drini cken - - - - - - - - - - refbsy ddrbsy cmdrdy drcmd r/w r/w r/w r/w r/w r/w r/w r /w r/w r/w r/w r/w r/w r r r w initial value 1 0 x x x x x x x x x x x x x x bit field no. name description 15 drini this sets dram initialization operation mode. 0 normal operation 1 initialization mode (initial value) when initialization is completed, this bit becomes 0. only when drini bit is 1, cken and drcm d bits of this register, and the dram initialization command register [1]/[2] become valid. when this bit is 0, these registers and bits are don?t care. note: ? data access and auto. refresh to dram are not performed in the initialization operation mode. ? only when there is no access request to ddr, drini bit can be changed to 0 1. the access request to ddr is able to be judged by ddrbsy (bit 2.) ? when drini bit is "1", do not access to data from axi. when data access is requested in the state of drini = 1, ddr2 controller may keep occupying the axi bus. moreover, the data requested from axi may be destroyed. 14 cken this is cke control signal to ddr. normal operation (drini = 0): cke output always becomes "1" initialization mode (drini = 1): cke output becomes "1" 13-4 (reserved) reserved bits. write access is ignored. 3 refbsy this bit indicates refresh cycle to ddr. 0 it is not refresh cycle 1 it is refresh cycle 2 ddrbsy this bit indicates status that data access is requested to ddr. 0 neither command request to ddr nor access to ddr occurs 1 command request to ddr or access operation to ddr occurs (busy) 1 cmdrdy this bit indicates dram command is ready. it also shows whether "1" is able to be written to drcmd bit (writing command bit to dram.) 0 1 cannot be written to drcmd (bit 0) 1 1 can be written to drcmd this bit indicates valid value for only at drini = 1. cmdrdy bit becomes "1" in the following cases: ? between writing "1" to drcmd (bit 0) to completion of the command. ? accessing to dram is not completed when drini bit is changed to 0 1 without reset.
9-6 MB86R01 lsi product specifications fujitsu semiconductor confidential ddr2 controller bit field no. name description 0 drcmd this is writing command bit to dram. writing "1" to this bit outputs setting condi tion of dram initialization command register [1]/[2] to dram during 1ck period of time. note: ? when drcmd bit does not issue command in the initialization mode, the state becomes nop or dsel to dram. ? only when cmdbsy (bit 1) is "0", "1" is able to be written to this bit.
9-7 MB86R01 lsi product specifications fujitsu semiconductor confidential ddr2 controller 9.5.3. dram initialization command register [1] (dric1) this register sets each control signal valu e of dram at the initialization operation. when "1" is written to drcmd in the initialization mode (drini = 1), the signal corresponding to dram bus is driven by this setting value. address f300_0000 h + 02 h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - - - - - - #cs #ras #cas #we ba2 ba1 ba0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x 1 1 1 1 1 1 1 9.5.4. dram initialization command register [2] (dric2) this register sets dram address signal value at the initialization operation. when "1" is written to drcmd in the initialization mode (drini = 1), the signal corresponding to dram bus is driven by this setting value. address f300_0000 h + 04 h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dram initialization method all dram is initialized by cpu. ddr2 controller is structured that each signal conductor necessary for the dram setting can be driven by the register value in the initialization mode. set certa in value to this register beforehand and "1" to command bit (drcmd) to execute the setting command to dram. to issue "precharge all (pall)" command to dram 1) set "bit[5:0] = 001000(b)" to the dram initialization command register [1]. 2) set "bit[13:0] = 00010000000000(b)" to the dram initialization command register [2]. (setting order of these 2 registers is not specified.) 3) write "1" to bit 0 of the dram initialization control register. the value set at 1) and 2) is output to dram for 1ck period of time, and this becomes command to dram. ? command to dram without command execution in the initialization mode is nop or dsel ? for each control method of dram command and initia lization, refer applied dram data sheet.
9-8 MB86R01 lsi product specifications fujitsu semiconductor confidential ddr2 controller 9.5.5. dram ctrl add register (drca) this register sets items such as capacity of dram to be connected. 06 h -0c h register settings related to ddr2 controller?s dram operation should be fixed before completing dram initialization. address f300_0000 h + 06 h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name type bus16 - - - ba nkrange rowrange colrange r/w r/w r/w r/w r/ w r/w r/w r/w r/w initial value 1 1 0 x x x 0 1 0 0 1 0 0 0 1 0 bit field no. name description 15-14 type operation mode of dram control core is set. 11 dram control core operates in the ddr2sdram mode others reserved (setting prohibited) 13 bus16 this specifies bus width of dram connected to external part. 0 32 bit 1 16 bit remark: ? use dq[15:0], dqs0/1, and dm0/1 ? see the pin specifications for process of unused dq[31:16], dqs2/3, and dm2/3 12-10 (reserved) reserved bits. write access is ignored. 9-8 bankrange bank address is set. since only 4 banks are applied, these bits are ready only and fixed to 01(b.) 7-4 rowrange row address range is set. 0001 4096 (12 bit) 0010 8192 (13 bit) others reserved (setting prohibited) 3-0 colrange col address range is set. 0001 256 (8 bit) 0010 512 (9 bit) 0100 1024 (10 bit) others reserved (setting prohibited)
9-9 MB86R01 lsi product specifications fujitsu semiconductor confidential ddr2 controller 9.5.6. dram control mode register (drcm) this register sets operation mode of dram, and the same setting as dram should be set. the operation mode is unable to be changed due to ddrif macro and other restrictions. address f300_0000 h + 08 h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - bt - al - cl - bl r/w r/w r/w r/w r r/ w r r/w r/w r/w r/w initial value x x x 0 x 0 0 0 x 0 1 1 x 0 1 0 bit field no. name description 15-13 (reserved) reserved bits. write access is ignored. 12 bt only sequential is applied in the burst type setting. setting to dram should also be "sequential". 0 sequential (initial value) 1 reserved (setting prohibited) 11 (reserved) reserved bit. write access is ignored. 10-8 al additive latency is set. this module operates with al = 0, and it should also be set to dram. 7 (reserved) reserved bit. write access is ignored. 6-4 cl cas latency is specified. 011 cl = 3 (fixed) others reserved (setting prohibited) dram setting should also have the same as this register?s. 3 (reserved) reserved bit. write access is ignored. 2-0 bl burst length is specified. 010 bl = 4 (fixed) others reserved (setting prohibited) dram setting should also have the same as this register?s. note: ? the drcm register is unable to be used for dram initialization. ? set operation mode of dram control core at normal operation to this register. when drini bit (bit 15) of the dram initialization control register becomes "0" (normal operation mode), dram control core operates accordin g to the drcm register setting. be sure to complete the setting before "0" is set to the drini bit.
9-10 MB86R01 lsi product specifications fujitsu semiconductor confidential ddr2 controller 9.5.7. dram ctrl set time1 register (drcst1) this register sets access timing to dram. it should be set with correlation of internal clock frequency and dram spec to be used. address f300_0000 h + 0a h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - trcd - tras - trp trc r/w r/w r/w r/w r/w r/w r/w r/w initial value x 1 1 1 x 1 1 1 x 1 1 1 1 1 1 1 bit field no. name description 15 (reserved) reserved bit. write access is ignored. 14-12 trcd ras to cas delay time (rrcd : active to read or write command delay) bit[14:12] delay time (number of clock) 000 - 001 - reserved (setting prohibited) 010 2 011 3 100 4 101 5 110 6 111 7 (initial value) 11 (reserved) reserved bit. write access is ignored. 10-8 tras ras active time (rras : active to precharge command) bit[10:8] delay time (number of clock) 000 - reserved (setting prohibited) 001 5 010 6 011 7 100 8 101 9 110 10 111 11 (initial value) 7 (reserved) reserved bit. write access is ignored. 6-4 trp precharge time (trp : precharge period) bit[6:4] delay time (number of clock) 000 - reserved (setting prohibited) 001 3 010 4 011 5 100 6 101 7 110 8 111 9 (initial value)
9-11 MB86R01 lsi product specifications fujitsu semiconductor confidential ddr2 controller bit field no. name description 3-0 trc ras cycle time (trc : active to active/auto. refresh command time) bit[3:0] delay time (number of clock) 0000 - 0001 - 0010 - 0011 - 0100 - 0101 - reserved (setting prohibited) 0110 8 0111 9 1000 10 1001 11 1010 12 1011 13 1100 14 1101 15 1110 16 1111 17 (initial value) for act command interval, larger value of either rrc and rras+rrp+twr is used.
9-12 MB86R01 lsi product specifications fujitsu semiconductor confidential ddr2 controller 9.5.8. dram ctrl set time2 register (drcst2) this register sets access timing to dram. it should be set by the correlation between dram spec and inner clock frequency. address f300_0000 h + 0c h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - trfc - - trrd - twr r/w r/w r/w r/w r /w r/w r/w r/w initial value x 1 1 0 1 0 1 1 x x 1 1 x 1 0 1 bit field no. name description 15-12 (reserved) reserved bits. write access is ignored. 11-8 trfc auto. refresh command period (trfc : auto. refresh to active/auto. refresh command time ) bit[11:8] cycle time (number of clock) 0000 4 0001 5 0010 6 0011 7 0100 8 0101 9 0110 10 0111 11 1000 12 1001 13 1010 14 1011 15 (initial value) 1100 16 1101 17 1110 18 1111 19 7-6 (reserved) reserved bits. write access is ignored. 5-4 trrd ras to ras bank active delay time (trrd : active bank a to active bank b command period) active command interval for when continuously activ ating ras in different bank is set in cycle. bit[5:4] cycle time (number of clock) 11 3 (initial value) others - reserved (setting prohibited) 3 (reserved) reserved bit. write access is ignored.
9-13 MB86R01 lsi product specifications fujitsu semiconductor confidential ddr2 controller bit field no. name description 2-0 twr write recovery time (twr : write recovery time) write recovery time of dram is set in cycle. bit[2:0] cycle time (number of clock) 000 - reserved (setting prohibited) 001 2 010 3 011 4 100 5 101 6 (initial value) 110 - 111 - reserved (setting prohibited)
9-14 MB86R01 lsi product specifications fujitsu semiconductor confidential ddr2 controller 9.5.9. dram ctrl refresh register (drcr) this register sets auto. refresh occurrence interval to dram. after changing this register value, refresh occurs irregularly. address f300_0000 h + 0e h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - - - - cntld ref_cnt r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x 0 0 0 0 0 0 0 0 0 bit field no. name description 15-9 (reserved) reserved bits. write access is ignored. 8 cntld counter load. ref_cnt value is forcibly loaded into internal counter. when this bit is set to 0 1, ref_cnt value of bit[7:0] is fo rcibly loaded into internal refresh counter. this is used when setting value needs to be applied, such as after ref_cnt value change. this bit does not need to be rewritten to 0 imme diately after loaded because it is performed after detecting the bit change. however, this bit keeps the writing value. if bit value is not 0 at executing load operation, "1" shoul d be written after writing "0". although cntld is not used after ref_cnt change, it operates with the changed ref_cnt by having the period before setting ref_cnt. 7-0 ref_cnt refresh count. auto. refresh request occurrence is set in 16 cycle. 00 h refresh request is continuously issued. priority of refresh is higher than the read/write. although access reque st to dram occurs, only refresh occurs with this setting. 01 h - ff h refresh request occurs in ref_cnt 16 clock interval. if dram data is accessed at refresh request, refresh does not start until the access is completed.
9-15 MB86R01 lsi product specifications fujitsu semiconductor confidential ddr2 controller 9.5.10. dram ctrl fifo register (drcf) this is ddr2c's internal fifo control related register. address f300_0000 h + 20 h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name *1 - - - - - - - - - - fifo_cnt r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 x x x x x x x x x x 1 0 1 1 0 *1: fifo_arb bit field no. name description 15 fifo_arb capture bandwidth is improved. 0 default 1 capture bandwidth is improved. 14-5 (reserved) reserved bits. write access is ignored. 4-0 fifo_cnt fifo full count. this is number of stage setting of address fifo (full condition.) when picture flickers due to axi access latency at using display a nd capture, it is recovered by reducing number of fifo stage a nd decreasing axi bus latency. bit[4:0] address fifo number of stage 00 h - 01 h - reserved (setting prohibited) 02 h 8 03 h 9 04 h 10 05 h 11 06 h 12 07 h 13 08 h 14 09 h 15 0a h 16 0b h 17 0c h 18 0d h 19 0e h 20 0f h 21 10 h 22 11 h 23 12 h 24 13 h 25 14 h 26 15 h 27 16 h 28 (initial value) 17 h - 1f h - reserved (setting prohibited)
9-16 MB86R01 lsi product specifications fujitsu semiconductor confidential ddr2 controller 9.5.11. axi setting register (drasr) this register sets axi interface operation. address f300_0000 h + 30 h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - - - - - - - - - - - - cache r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x 0 bit field no. name description 15-1 (reserved) reserved bits. write access is ignored. 0 cache cache on/off of cash operation at reading are performed. 0 cache off (initial value) 1 cache on when single reading continuously occurs in a single access (16 byte) to dram, reading operation from axi is enabled by the cached data in axi module instead of accessing to dram. however cache is cleare d in the following conditions. ? burst reading access occurs to axi bus in ddr2c ? write access occurs to axi bus in dr2c
9-17 MB86R01 lsi product specifications fujitsu semiconductor confidential ddr2 controller 9.5.12. dram if macro setting dll register (drimsd) this register is for ddr2-sdram interface macro se tting which drives macro pi n corresponding to each bit by the setting value. this is also for dll timing setting. address f300_0000h + 50h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - isft_3[2:0] - isft_2[2:0] - isft_1[2:0] - isft_0[2:0] r/w r/w r/w r/w r/ w r/w r/w r/w r/w initial value x 1 1 0 x 1 1 0 x 1 1 0 x 1 1 0 bit field no. name description 15 (reserved) reserved bit. write access is ignored. 14-12 isft_3[2:0] value of isft_3[2:0] 110 (initial value) 101 normal operation setting value (set to 101 at dram initialization) others reserved (setting prohibited) 11 (reserved) reserved bit. write access is ignored. 10-8 isft_2[2:0] value of isft_2[2:0] 110 (initial value) 101 normal operation setting value (set to 101 at dram initialization) others reserved (setting prohibited) 7 (reserved) reserved bit. write access is ignored. 6-4 isft_1[2:0] value of isft_1[2:0] 110 (initial value) 101 normal operation setting value (set to 101 at dram initialization) others reserved (setting prohibited) 3 (reserved) reserved bit. write access is ignored. 2-0 isft_0[2:0] value of isft_0[2:0] 110 (initial value) 101 normal operation setting value (set to 101 at dram initialization) others reserved (setting prohibited)
9-18 MB86R01 lsi product specifications fujitsu semiconductor confidential ddr2 controller 9.5.13. dram odt setting register (dros) this register sets odt control signal to ddr2 memory connected to external part. address f300_0000 h + 60 h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - - - - - - - - - - - - odt0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x 0 bit field no. name description 15-1 (reserved) reserved bits. write access is ignored. 0 odt0 this is the value of external output pin, odtcont. initial value is 0.
9-19 MB86R01 lsi product specifications fujitsu semiconductor confidential ddr2 controller 9.5.14. io buffer setting odt1 (dribsodt1) odt related setting of io buffer is set. address f300_0000 h + 64 h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - - - - - - - zseln odtonn zselp odtonp zsel odton r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x 0 0 0 0 0 0 bit field no. name description 15-6 (reserved) reserved bits. write access is ignored. 5 zseln this becomes zseln value of io buffer, and this is odt resistance setting for dqsn. 0 150 or 100 (initial value) 1 75 or 50 4 odtonn this is odt setting for dqs?s io, and controls odtonn of the io buffer. initial value is 0. 0 io buffer?s odton is always "0" 1 this should be set to use odt of io buffer odton is set to off in the following case: ? to adjust ocd 3 zselp this becomes zselp value of the io buffer, and it is odt resistance setting of dqsp?s io. 0 150 or 100 (initial value) 1 75 or 50 2 odtonp this is odt setting of dqs?s io, and controls odtonp of the io buffer. initial value is 0. 0 io buffer?s odton is always "0" 1 this should be set to use odt of io buffer odton is set to off in the following case: ? to adjust ocd 1 zsel this is zsel value of the io buffer th at is odt resistance of io for dq and dm. 0 150 or 100 (initial value) 1 75 or 50 0 odton this is odt setting of io for dq a nd dm, and it controls odton of io buffer. initial value is 0. 0 io buffer?s odton is always "0" 1 this should be set to use odt of io buffer odton is set to off in the following case: ? to adjust ocd
9-20 MB86R01 lsi product specifications fujitsu semiconductor confidential ddr2 controller 9.5.15. odt auto bias adjust register (droaba) this register sets auto. adjustment related items of odt bias. address f300_0000 h + 70 h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - - - - oco mpnpol oco mpppol - - - iavset odtbias r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x 1 0 x x x 0 0 0 0 bit field no. name description 15-9 (reserved) reserved bits. write access is ignored. 8 ocompnpol this sets to detect either 0 1 or 1 0 of ococmpn value as valid at bias adjustment operation. 0 0 1 is valid 1 1 0 is valid (initial value) 7 ocompppol this sets to detect either 0 1 or 1 0 of ococmpp value as va lid at bias adjustment operation. 0 0 1 is valid (initial value) 1 1 0 is valid 6-4 (reserved) reserved bits. write access is ignored. 3-2 iavset average number of times of bias adjustment is specified. adjustment is performed for predetermined numbe r of times to output the average value to odt of the i/o cell. 00 32 times (initial value) 01 64 times 10 128 times 11 256 times 1-0 odtbias operation of bias auto. adjustment circuit is set. 00 auto. adjustment circuit of the bias is reset (initial value) 01 reserved (setting prohibited) 10 reserved (setting prohibited) 11 auto. adjustment circuit of the bias is performed remark: each setting of bit2 - 8 should be set after setting odtbias of bit 1 - 0 to "00" and stopping auto. adjustment operation.
9-21 MB86R01 lsi product specifications fujitsu semiconductor confidential ddr2 controller 9.5.16. odt bias select register (drobs) this register sets odt. address f300_0000 h + 84 h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - - - - - - - - - - - - auto r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x 0 bit field no. name description 15-1 (reserved) reserved bits. write access is ignored. 0 auto this sets whether to use odt auto. setting value mode. when it is set, the average value calculated with auto. adjustment of the bias is used to odt value of the i/o cell. 0 the odt auto. setting value mode is not used 1 the odt auto. setting value mode is used
9-22 MB86R01 lsi product specifications fujitsu semiconductor confidential ddr2 controller 9.5.17. ocd impedance setting rrgister1 (droisr1) this register sets impedance adjustment value. address f300_0000 h + 98 h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name drvn2 drvp2 drvn1 drvp1 r/w r/w r/w r/w r/w initial value 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 bit field no. name description 15-12 drvn2 this register sets drvn value of dq[15:8], dqs1, and dm1 11-8 drvp2 this register sets dr vp value of dq[15:8], dqs1, and dm1 7-4 drvn1 this register sets drvn value of dq[7:0], dqs0, and dm0 3-0 drvp1 this register sets drvp value of dq[7:0], dqs0, and dm0 9.5.18. ocd impedance setting register2 (droisr2) this register sets impedance adjustment value. address f300_0000 h + 9a h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name drvn4 drvp4 drvn3 drvp3 r/w r/w r/w r/w r/w initial value 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 bit field no. name description 15-12 drvn4 this register sets drvn value of dq[31:24], dqs3, and dm3 11-8 drvp4 this register sets dr vp value of dq[31:24], dqs3, and dm3 7-4 drvn3 this register sets dr vn value of dq[23:16], dqs2, and dm2 3-0 drvp3 this register sets drvp value of dq[23:16], dqs2, and dm2
9-23 MB86R01 lsi product specifications fujitsu semiconductor confidential ddr2 controller 9.6. operation this section describes ddr2c operation. 9.6.1. dram initialization sequence initialization sequence at using ddr2sdram is described below. figure 9-2 shows initialization sequence at usin g ddr2sdram in time chart. to proceed memory access to ddr2sdram, initialization sequence should be performed after power-on. during initialization sequence, ddrif macro setting, dll reset release in ddrif macro, sdram initialization, ocd adjustment, odt setting, and others are processed. refer to " 9.6.2 dram in itialization procedure" for more detail of initialization sequence. figure 9-2 ddr2sdram initialization time chart ireset*5 (ddrif macro reset) xrst (chip reset) iusrrst*5 (ddrif macro reset) idllrst*5 (ddrif macro dll reset) mcke (ddr2 if cke) *1 pll lock up time or more *2 mckp cycle (166mhz=6[ns]) 20cycle = 120[ns] mckp (ddr2 if clk) mcs (ddr2 if xcs) *3 dll lock up time or more (79[us]) *4 based on ddr2sdram spec odtcont (ddr2 if odt) *5 this is internal signal of chip, not pin signal (ddrifmacro module input signal) power-on (1) *1 (6) idllrst release (4) ireset/iusrrst release (2) ddrif macro register setting (3) 120[ns] or more*2 (5) 120[ns] or more*2 (7)79[us] or more *3 (8)200[us] or more *4 (9) mcke on (10) sdram initialization (11) odtcont-on shifting to ddr2c normal operation mode
9-24 MB86R01 lsi product specifications fujitsu semiconductor confidential ddr2 controller 9.6.2. dram initialization procedure the figure below is a whole flow of the register setting procedure for initialization sequence. each number matches to the one in ddr2sdram initialization time chart shown in figure 9-2. th e procedure showing here is only the register setting relating to the dram initialization. figure 9-3 dram initialization procedure (1) pll lock up time or more wait (3) 166mhz (6[ns]) x 20 cycles = 120[ns] or more wait (4) ireset/iusrrst release write ?00000002? to general register 1 (offset + ech) of ccnt module (2) ddrif macro register setting write "5555? to drimsd register (offset + 50h) (5) 166mhz([ns]) x 20 cycles = 120[ns] or more wait power-on (6) idllrst release write ?00000003? to general register 1 (offset + ech) of ccnt module (7) dll lock up time (79[s]) or more wait (8) 200[s] (specification of ddr2sdram) or more wait (9) mcke on write ?003f? to dric1 register (offset + 02h) write ?0000? to dric2 register (offset + 04h) write ?c124? to drca register (offset + 06h) write ?c000? to dric register (offset + 00h) (10) sdram initialization (11) shift to odtcont on (sdram side) and ddr2c normal operation mode write ?0001? to dros register (offset + 60h) write ?4000? to dric register (offset + 00h) dram initialization completion refer to "9.6.2.1 sdra m initialization procedure " for detail note: for the construction of 512m bit ddr2sdram 2
9-25 MB86R01 lsi product specifications fujitsu semiconductor confidential ddr2 controller 9.6.2.1. sdram initialization procedure the figure below is ddr2sdram initialization setting procedure at dram initialization. ddr2sdram initialization sequence's command contents to be issued may change depending on the memory specification connected to this chip. for each command's issuing contents and ddr2c comma nd issuing timing, be sure to confirm memory spec in use to set properly. figure 9-4 ddr2sdram initialization procedure write ?c001? to dric register (offset + 00h) start write ?0017? to dric1 register (offset + 02h) write ?0400? to dric2 register (offset + 04h) write ?c001? to dric register (offset + 00h) write ?0006? to dric1 register (offset + 02h) write ?0000? to dric2 register (offset t+ 04h) write ?c001? to dric register (offset + 00h) ddr2 if: issue nop command ddr2 if: issue pall command ddr2 if: issue emr (2) command write ?0007? to dric1 register (offset + 02h) write ?0000? to dric2 register (offset + 04h) write ?c001? to dric register (offset + 00h) ddr2 if: issue emr (3) command write ?0005? to dric1 register (offset +02h) write ?0000? to dric2 register (offset t+04h) write ?c001? to dric register (offset +00h) ddr2 if: issue emr (1) command write ?0000? to dric1 register (offset + 02h) write ?0532? to dric2 register (offset + 04h) write ?c001? to dric register (offset + 00h) ddr2 if: issue mrs command write ?0017? to dric1 register (offset + 02h) write ?0400? to dric2 register (offset + 04h) write ?c001? to dric register (offset + 00h) ddr2 if: issue pall command write ?000f? to dric1 register (offset + 02h) write ?0400? to dric2 register (offset + 04h) write ?c001? to dric register (offset + 00h) write ?c001? to dric register (offset + 00h) ddr2 if: issue ref command write ?0000? to dric1 register (offset + 02h) write ?0432? to dric2 register (offset + 04h) write ?c001? to dric register (offset + 00h) ddr2 if: issue mrs command write ?0005? to dric1 register (offset + 02h) write ?0380? to dric2 register (offset + 04h) write ?c001? to dric register (offset + 00h) ddr2 if: issue emr (1) command a to next sheet
9-26 MB86R01 lsi product specifications fujitsu semiconductor confidential ddr2 controller figure 9-4 ddr2sdram initialization procedure end write ?0005? to dric1 register (offset + 02h) write ?0044? to dric2 register (offset + 04h) write ?c001? to dric register (offset + 00h) ddr2 if: issue emr (1) command set to odt 50 ddr2 if timing setting (bt, al, cl, and bl) a continued from the previous page write ?0032? to drcm register (offset + 08h) write ?3318? to drcst1 register (offset + 0ah) write ?6e32? to drcst2 register (offset + 0ch) write ?0141? to drcr register (offset + 0eh) write ?0002? to drcf register (offset + 20h) write ?0001? to drasr register (offset + 30h) ddr2 if timing setting (trcd, tras, trp, and trc) ddr2 if timing setting (trfc, trrd, and twr) refresh issued at ddr2c normal operation mode command issuing interval setting (the value is reference) address fifo's number of stage setting in ddr2c (set to 8 stages) ddr2c's axi cache function setting on
9-27 MB86R01 lsi product specifications fujitsu semiconductor confidential ddr2 controller 9.6.2.2. odt setting procedure the figure below is odt adjustment setting procedure of sstl_18 io used for ddr2sdram if. with proceeding odt setting, ddr2c automatically adjusts odt of sstl_18 io; moreover, auto. adjustment always operates during memory reading at normal operation. pin for odt adjustment is mdq[31:0], mdm[3:0], mdqsp[3:0], and mdqsn[3:0]. figure 9-5 odt adjustment setting procedure of sstl_18 io write "0001" to drobs register (offset + 84h) start set to the mode using odt auto. setting value odt auto. adjustment on set odt to on 75/50 : ?003f? 150 /100 : ?0015? write "0083" to droaba register (offset + 70h) write "003f" to dribsodt1 register (offset + 64h) end
10-1 MB86R01 lsi product specifications fujitsu semiconductor confidential built-in sram 10. built-in sram this chapter describes function and operation of built-in sram. 10.1. outline this sram equips 32kb of sram that enables storing instruction and data. 10.2. feature intram has following features: ? operation as bus slave of amba (ahb) ? 2pcs. of built-in sram are accessible from different 2 ahb masters simultaneously ? 32kb of sram is equipped to each built-in sram 10.3. block diagram figure 10-1 shows block diagram of built-in sram. ahb bus built-in sram_1 32kb built-in sram_0 32kb figure 10-1 block diagram of built-in sram 10.4. supply clock ahb clock is supplied to built-in sram. refer to "5. clock reset generator (crg)" for frequency setting and control specification of the clock.
11-1 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) 11. dma controller (dmac) this chapter describes function and operation of dma controller. 11.1. outline dmac is 8 channel dma controller. 11.2. feature dmac in MB86R01 has following features: ? compliant with amba v2.0 ? 8 dma channels ? dma trigger ? external transfer request (2ch of external dma request and 6ch of i2s tran smission/reception dma request are available) ? peripheral transfer request (12 types of uart tr ansmission/reception dma request is selectable per channel) ? software request (start-up by register writing) ? beat transfer 16 word fifo shared by all channels corresponding to incr, incr 4/8/16, and wrap 4/8/16. ? transfer mode ? block transfer ? burst transfer ? demand transfer ? 4 bit block register and 16 bit count register are set by programming ? corresponding to 8, 16, and 32 bit transfer widths ? corresponding to increment and fixed addressing to source and destination ? reload count, source address, and destination address register ? issuing error interrupt and completion interrupt ? displaying end code of dma transfer ? supporting source and destination protection ? corresponding to fixed priority and rotation priority by hardware. in the fixed priority mode, channel 0 has the highest priority, and channel 7 has the lowest priority
11-2 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) 11.3. block diagram figure 11-1 shows block diagram of dma controller. MB86R01 dmac hdmacmasterctrl hdmacfifo ahb master signals hdmacslavectrl ahb slave signals hdmacmaster hdmacre g ister hdmacmaster hdmacre g ister hdmacmaster hdmacre g ister hdmacmaster hdmacre g ister hdmacmaster hdmacre g ister hdmacmaster hdmacre g ister hdmacmaster hdmacre g ister hdmacmaster hdmacre g ister hdmacchannel channel 0 register flag and setting data ahb master signals of each channels channel 1 channel 2 channel 3 channel 4 channel 6 channel 7 irc dirq[7:0] dreq[7:6] dreq[7:6] 2 dack[7:6] xdack[7:6] 2 deop[7:6] open 2 uart0 idreq[0] idreq[1] transfer ready receive ready uart1 idreq[2] idreq[3] transfer ready receive ready idreq[15:12] 4?h0 uart2 idreq[4] idreq[5] transfer ready receive ready uart3 idreq[6] idreq[7] transfer ready receive ready uart4 idreq[8] idreq[9] transfer ready receive ready uart5 idreq[10] idreq[11] transfer ready receive ready i2s_0 dreq[0], dreq[1],deop[0] ,deop[1] dstp[0], dstp[1] tx/rxdreq,tx/rxdeo p txdstp i2s_1 dreq[2], dreq[3],deop[2] ,deop[3] dstp[2], dstp[3] tx/rxdreq,tx/rxdeo p txdstp i2s_2 dreq[4], dreq[5],deop[4] ,deop[5] dstp[4], dstp[5] tx/rxdreq,tx/rxdeo txdstp dstp[7:6] 2 2?h0 channel 5 figure 11-1 block diagram of dma controller
11-3 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) function of individual block table 11-1 shows each block function of this module. table 11-1 individual block function block function dmac most significant module hdmacmasterctrl valid channel selector for priority controller and ahb master transaction hdmacslavectrl dmac ahb slave interface controller and valid channel selector i/f for ahb slave transaction hdmacchannel dmac 1 channel module dmac has 8 modules hdmacmaster dmac ahb master main controller hdmacregister dmac dma confi guration register controller hdmacfifo dmac 16 word fifo 11.4. related pin dmac of MB86R01 has following dma related pin which is common with other functions. to use the pin, external pin should be set to mpx_mode_1[1:0] = "lh" or mpx_mode_1[1:0] = "hl" to select dma related pin. table 11-2 dmac related pin pin direction qty. description dreq[6] dreq[7] i 2 dma request pin which is connected as channel 7 of dmac and channel 6 of external dreq signal. xdack[6] xdack[7] o 2 dma acknowledge pin which is connected as channel 7 of dmac and channel 6 of external dack signal. 11.5. supply clock ahb clock is supplied to dma controller. refer to "5. clock reset generator (crg)" for frequency setting and control specification of the clock.
11-4 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) 11.6. register this section describes dmac register. 11.6.1. register list dmac control related register is shown below. table 11-3 dmac register list module address register function dmac common fffd0000(h) dmacr dm ac configuration register fffd0004(h) fffd000f(h) reserved fffd0010(h) dmaca0 dmac0 configuration a register fffd0014(h) dmacb0 dmac0 configuration b register fffd0018(h) dmacsa0 dmac0 source address register dmac ch0 fffd001c(h) dmacda0 dmac0 des tination address register fffd0020(h) dmaca1 dmac1 configuration a register fffd0024(h) dmacb1 dmac1 configuration b register fffd0028(h) dmacsa1 dmac1 source address register dmac ch1 fffd002c(h) dmacda1 dmac1 des tination address register fffd0030(h) dmaca2 dmac2 configuration a register fffd0034(h) dmacb2 dmac2 configuration b register fffd0038(h) dmacsa2 dmac2 source address register dmac ch2 fffd003c(h) dmacda2 dmac2 des tination address register fffd0040(h) dmaca3 dmac3 configuration a register fffd0044(h) dmacb3 dmac3 configuration b register fffd0048(h) dmacsa3 dmac3 source address register dmac ch3 fffd004c(h) dmacda3 dmac3 des tination address register fffd0050(h) dmaca4 dmac4 configuration a register fffd0054(h) dmacb4 dmac4 configuration b register fffd0058(h) dmacsa4 dmac4 source address register dmac ch4 fffd005c(h) dmacda4 dmac4 des tination address register fffd0060(h) dmaca5 dmac5 configuration a register fffd0064(h) dmacb5 dmac5 configuration b register fffd0068(h) dmacsa5 dmac5 source address register dmac ch5 fffd006c(h) dmacda5 dmac5 des tination address register fffd0070(h) dmaca6 dmac6 configuration a register fffd0074(h) dmacb6 dmac6 configuration b register fffd0078(h) dmacsa6 dmac6 source address register dmac ch6 fffd007c(h) dmacda6 dmac6 des tination address register fffd0080(h) dmaca7 dmac7 configuration a register fffd0084(h) dmacb7 dmac7 configuration b register fffd0088(h) dmacsa7 dmac7 source address register dmac ch7 fffd008c(h) dmacda7 dmac7 des tination address register
11-5 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) notice for register setting note followings for dmac register setting. ? dmacr, dmaca, dmacb, dmacsa, and dmacda re gisters are accessible in byte, half-word, and word size. ? do not set dmac register address to dmacsa and dmacda registers. ? do not change setting register's channel during dma transfer except de/dh bits of dmacr and eb/pb bits of dmaca. description format of register following format is used for descri ption of register?s each bit in " 11.6.2 dma configuration register (dm acr)" to " 11.6.6 dmac destination address register (dmacdax)". address base address + offset bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r/w initial value bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r/w initial value meaning of item and sign address address (base address + offset address) of the register bit bit number of the register name bit field name of the register r/w attribution of read/write of each bit field ? r0:read value is always "0" ? r1: read value is always "1" ? w0: write value is always "0", and write access of "1" is ignored ? w1: write value is always "1", and write access of "0" is ignored ? r: read ? w: write initial value each bit field?s value after reset ? 0: value is "0" ? 1: value is "1" ? x: value is undefined
11-6 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) 11.6.2. dma configuration register (dmacr) address fffd_0000 + 00(h) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name de ds - pr dh[3:0] (reserved) r/w r/w r r r/w r/w r/w r/w r/w r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31 de (dma enable) transfer is controlled for all dma channels. 0 all dma channels are disabled and dma tran sfer is not performed until "1" is set to this bit if the value is cleared to "0" during the transfer, dma is stopped at transmission gap for the channel in transfer 1 dma transfer starts according to the register setting of each channel [transfer gap] the transfer gap is that dmac de-asserts bus reque st (hbusreq) to the arbiter during dma transfer (about 4 clocks) by dmac. its occurrence is different by transfer mode shown below. ? block transfer: transfer gap occurs at bc = 0 (after completing transfer in bc unit) ? burst transfer: there is no transfer gap. ? demand transfer: transfer gap occurs at tc = tc - 1 (after completing 1 dma transfer), or at transfer request negotiation this bit can be used to reset all channels of c onfiguration register at a time during dma transfer. 30 ds (dma stop) this shows all channels of dma transfer is stop. 0 release of disable/halt setting 1 dma transfer stop of all channels by disable/halt setting this bit is set to "1" during dma transf er by either of following operations: ? dmacr.de bit is cleared to "0" (all channels are disabled) ? value other than 4'h0 is set to dm acr.dh bit (all channels are halt) when the state of disable/halt is cleared, dmac clears ds bit to "0". this bit is able to use for confirmation of transfer stop when dmac stops transfer of all channels by disable/halt setting. 29 (reserved) reserved bits. write access is ignored. read value of this bit is always "0". 28 pr (priority rotation) prioritization procedure of dma channel is controlled. 0 "fixed" priority order: ch0 > ch1 > ch2 > ch3 > ch4 > ch5 > ch6 > ch7 1 "rotation" priority order is rotated channel switch occurs by the timing of transfer gap. refer to de bit description for the transfer gap.
11-7 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) bit field no. name description 27- 24 dh[3:0] (dma halt) all channels of dma stop are controlled. when the value other than 4'b0000 is set to this bit, all dma channels stop and dma is not transferred until 4'b0000 is set. if the value other than 4'b0000 is set during dma transfer, it is stopped at transfer gap. refer to de bit description for the transfer gap. these bits are used to stop dma transfer without rese tting each configuration re gister of all channels. 0000 stop release other than 0000 stop of all channels 23-0 (reserved) reserved bits. write access is ignored. read valu e of this bit is always "0".
11-8 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) 11.6.3. dma configuration a register (dmacax) address ch0 fffd_0000+10 (h) ch1 fffd_0000+20 (h) ch2 fffd_0000+30 (h) ch3 fffd_0000+40 (h) ch4 fffd_0000+50 (h) ch5 fffd_0000+60 (h) ch6 fffd_0000+70 (h) ch7 fffd_0000+80 (h) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name eb pb st is[4:0] bt[3:0] bc[3:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tc[15:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31 eb (enable bit) this bit is used to control dma channel transfer. when "1" is set to this bit, channel waits for the trigger to start dma transfer (dmacr/de bits should be set to "1" beforehand.) dmac sets "0" to this bit after dma transfer, then this channel is disabled and dma transfer is not performed until "1" is set to this bit. if "0" is set to this bit during dma transfer, dma stops at transfer gap which is regarded as forcible termination. refer to dmacr/de bits description for transfer gap. this bit is able to use for resetting each configur ation register of the channel during dma transfer. 0 this channel is disabled (initial value) 1 this channel is enabled 30 pb (pause bit) this bit is used to discontinue dma channel transfer. when "1" is set to this bit, this channel stops th e transfer, and it is not performed until this bit is cleared. if "1" is set to this bit during dma transfer, dma stops at transfer gap. refer to dmacr/de bits description for transfer gap. when "1" is set to this bit before receiving transfer request to acquire bus right, dmac is immediately paused; in this case, dmac doe s not hold transfer request during the pause. when "0" is set to this bit during dma transfer is in pause, it is cleared and dmac waits for new transfer request. this bit is able to be used to stop dma transfer without resetting each configuration register of the channel. 0 initial value 1 this channel is stopped 29 st (software trigger) this bit is used to generate software trigger. when "1" is set to this bit, dma transfer star ts as software request is received. after the transfer, dmac sets "0" to this bit. if "0" is set to this bit during dma transfer by software request, it stops at transfer gap. 0 initial value 1 software request
11-9 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) bit field no. name description 28-24 is[4:0] (input select) this bit is used to select trigger for dma transfer. dma transfer trigger is software request (st = 1): set 5?b00000 to is bit dma transfer trigger is external request (dreq): set 5?b01110 or 5?b01111 to is bit dma transfer trigger is peripheral re quest (idreq[15:0]): set 5?b1xxxx to is bit external request (dreq[7:0]) is allocated into each channel, and peripheral request (idreq[15:0]) is allocated into all channels. th us, peripheral request can be selected from all channels. is[4:0] function 0(h) software request 1(h)-b(h) invalid e(h) dreq "h" active level or rising edge f(h) dreq "l" active level or falling edge 10(h) idreq 0 "h" active level or rising edge 11(h) idreq 1 "h" active level or rising edge 12(h) idreq 2 "h" active level or rising edge 13(h) idreq 3 "h" active level or rising edge 14(h) idreq 4 "h" active level or rising edge 15(h) idreq 5 "h" active level or rising edge 16(h) idreq 6 "h" active level or rising edge 17(h) idreq 7 "h" active level or rising edge 18(h) idreq 8 "h" active level or rising edge 19(h) idreq 9 "h" active level or rising edge 1a(h) idreq 10 "h" active level or rising edge 1b(h) idreq 11 "h" active level or rising edge 1c(h) idreq 12 "h" active level or rising edge 1d(h) idreq 13 "h" active level or rising edge 1e(h) idreq 14 "h" active level or rising edge 1f(h) idreq 15 "h" active level or rising edge transfer mode is block transfer or burst transfer: rising edge is selected. transfer mode is demand transfer: "h" active level is selected. [note] ? these bits must not be the same as other channels? ? if these bits are changed at asserting dreq/idreq, dmac regards is bit change as edge (rising edge/falling edge) detection.
11-10 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) bit field no. name description 23-20 bt[3:0] (beat type) these bits are used to select beat transfer on ahb. when these bits are set to normal or single, single source access and single destination access are alternately performed. if these bits are set to incr* or wrap*, c ontiguous source access and contiguous destination access are alternately performed. dmac has 64 byte of fifo that is shared in al l channels. fifo is used for incr* and wrap* dma transfer. refer to the amba specifications (v2.0) for incr* and wrap*. when incr (undefined length burst) is set, th e burst length is specified by the bc bit. bt[3:0] function 0(h) normal (same as single) (initial value) 1(h)-7(h) invalid 8(h) single (same as normal) 9(h) incr a(h) wrap4 b(h) incr4 c(h) wrap8 d(h) incr8 e(h) wrap16 f(h) incr16 while dmacb/ms are set to block transfer and burst transfer, fixed length burst (incr*, wrap*) and undefined length burst (incr) are valid. when dmacb/ms are set to demand transfer, bt should be set to normal or single. 19-16 bc[3:0] (block count) these bits are used to specify number of block for block/burst transfer. when transfer mode is demand transfer, be sure to set 4'b0000 to bc. max. block quantity is 16 (fh.) these bits are valid when beat transfer type is normal, single, or incr. when other types of beat (fixed length burst and lap) are set, these bits are ignored. in addition, they are able to be read during dma transfer. after single source access and single destination access are properly completed, normally bc bit is decremented for 1. [note] these bits are settable even beat type bit (bt[3:0]) is incr, however, read data of bc after starting dma transfer is always 4?h0 in incr dma transfer so that bc does not need to be monitored during the transfer. after dma transfer is completed properl y, dmac sets 4?b0000 to these bits. bc[3:0] function x(h) number of block (initial value: 4?b0000) 15-0 tc[15:0] (transfer count) these bits are used to specify number of block/burst/demand transfer. max. number of transfer is 65536 (ffffh.) any kind of bit type is valid for bt. these bits are readable during dma transfer. after bc becomes "0" and dma transfer is properly completed, normally tc bit is decremente d for 1 in the normal or single mode (bt = normal or single.) in other beat transf er modes (incr, incr*, and wrap*), tc bit is decremented for 1 after completing consecutive source/destination access operation (for example, when 4 consecutive source accesses and 4 consecutive destination accesses are completed, incr4?s tc bit is decremented for 1.) after dma transfer is completed properl y, dmac sets 16?h0000 to these bits. tc[3:0] function x(h) number of transfer (initial value: 16?h0000)
11-11 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) 11.6.4. dma configuration b register (dmacbx) address ch0 fffd_0000+14 (h) ch1 fffd_0000+24 (h) ch2 fffd_0000+34 (h) ch3 fffd_0000+44 (h) ch4 fffd_0000+54 (h) ch5 fffd_0000+64 (h) ch6 fffd_0000+74 (h) ch7 fffd_0000+84 (h) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name tt[1:0] ms[1:0] tw[1:0] fs fd rc rs rd ei ci ss[2:0] r/w r/w r/w r/w r/w r/w r/w r/w r/ w r/w r/w r/w r/w r/w r/w0 r/w0 r/w0 initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sp[3:0] dp[3:0] (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-30 tt[1:0] (transfer type) these bits are used to specify transfer type. currently, only 2 cycle transfer mode is available for dmac. tt[1:0] function 0(h) 2 cycle transfer (initial value) other than 0(h) reserved 29-28 ms[1:0] (mode select) these bits are used to select transfer mode. ms[1:0] function 0(h) block transmission mode (initial value) 1(h) burst transmission mode 2(h) demand transmission mode 3(h) reserved 27-26 tw[1:0] (transfer width) these bits are used to specify transfer data width. hsize of dmac issues this value on ahb. tw[1:0] function 0(h) byte (initial value) 1(h) half-word 2(h) word 3(h) reserved 25 fs (fixed source) this bit is used to fix source address. when the address needs to be added after each transfer, "0" must be set to this bit. fs function 0(h) source address is incremented (initial value) 1(h) source address is fixed 24 fd (fixed destination) this bit is used to fix destination address. when the address needs to be added after each transfer, "0" must be set to this bit. fd function 0(h) destination address is incremented (initial value) 1(h) the destination address is fixed
11-12 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) bit field no. name description 23 rc (reload count) this bit is used to control reload function fo r number of block (dmaca/bc bits) and number of transfer (dmaca/tc bits.) when "1" is set to this bit, dmaca/bc and dmaca/tc are set to the initial value after dma transfer. rc function 0(h) reload function for number of tran sfer is disabled (initial value) 1(h) reload function for number of transfer is enabled 22 rs (reload source) this bit is used to control reload function of source address (dmacsa.) "1" is set to this bit: dmacsa is set to the initial value after dma transfer "0" is set to this bit: dmac sets the next source address to dmacsa after dma transfer rs function 0(h) reload function of source addr ess is disabled (initial value) 1(h) reload function of source address is enabled 21 rd (reload destination) this bit is used to control reload f unction of destination address (dmacda.) "1" is set to this bit: dmacda is set to the initial value after dma transfer "0" is set to this bit: dmac sets the next destination address to dmacda after dma transfer rd function 0(h) reload function of destination ad dress is disabled (initial value) 1(h) reload function of destination address is enabled 20 ei (error interrupt) this bit is used to control issuing interrupt (dirq) caused by error. when this bit is set to "1", error interrupt is issued by the following transfer errors. ? address overflow ? transfer stop request from dstp and idstp, or transfer disable with eb or de bit ? source access error ? destination access error ei function 0(h) error interrupt issue is disabled (initial value) 1(h) error interrupt issue is enabled 19 ci (completion interrupt) this bit is used to control issuing interr upt (dirq) caused by completion of transfer. when this bit is set to "1", completion interrupt is issued after dma is transferred properly. ci function 0(h) completion interrupt is disabled (initial value) 1(h) completion interrupt is enabled
11-13 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) bit field no. name description 18-16 ss[2:0] (stop status) these bits are used to show end code of dma transfer which is shown below. these bits are also used to release interrupt (d irq) which is performed by writing 3'b000 to these bits when interrupt becomes error or it is issued by normal termination. ss function status type 0(h) initial value none 1(h) address overflow error 2(h) transfer stop request error 3(h) source access error error 4(h) destination access error error 5(h) normal termination end 6(h) reserved 7(h) dma discontinuance none when various errors occur at the same time, en d code is displayed by the following priority. high priority reset clear by 3'b000 writing address overflow demand stop source access error destination access error low priority 15-12 sp[3:0] (source protection) these bits are used to control source protection. hprot at source access issues this value to ahb; however, it is not performed if source target does not equip protection function. sp function x(h) protection code (initial value: 4'b0000.) 11-8 dp[3:0] (destination protection) these bits are used to control destination protection. hprot at destination access issues this value to ahb; however, it is not performed if source target does not equip protection function. dp function x(h) protection code (initial value: 4'b0000.) 7-0 (reserved) reserved bits. write access is ignored. read valu e of this bit is always "0".
11-14 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) 11.6.5. dmac source address register (dmacsax) address ch0 fffd_0000+18 (h) ch1 fffd_0000+28 (h) ch2 fffd_0000+38 (h) ch3 fffd_0000+48 (h) ch4 fffd_0000+58 (h) ch5 fffd_0000+68 (h) ch6 fffd_0000+78 (h) ch7 fffd_0000+88 (h) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dmacsa[31:16] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dmacsa[15:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-0 dmacsa[31:0] (dmac source address) these bits are used to specify source address to start dma transfer, and they are able to be read during dma transfer. when fixed address function (dmacb/fs) is disabled, these bits are incremented according to the transfer width (dmacb/tb) after completing source address properly. after the dma transfer, dmac sets the next source address to these bits. [note] it is prohibited to set dmac register address to dmacsa. dmacsa function x(h) source address to start dma transfer (initial value: 32'h00000000)
11-15 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) 11.6.6. dmac destination address register (dmacdax) address ch0 fffd0000+1c (h) ch1 fffd0000+2c (h) ch2 fffd0000+3c (h) ch3 fffd0000+4c (h) ch4 fffd0000+5c (h) ch5 fffd0000+6c (h) ch6 fffd0000+7c (h) ch7 fffd0000+8c (h) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dmacda[31:16] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dmacda[15:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-0 dmacda[31:0] (dmac destination address) these bits are used to specify destination address to start dma transfer, and they are able to be read during dma transfer. when fixed address function (dmacb/fd) is disabled, these bits are incremented according to the transfer width (dmacb/tb) after co mpleting destination address properly. after dma transfer, dmac sets the next destination address to these bits. [note] it is prohibited to set dmac register address to dmacda. dmacda function x(h) destination address to start dma transfer (initial value: 32'h00000000)
11-16 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) 11.7. operation this section describes operation of dmac. 11.7.1. transfer mode dmac has 3 types of transfer modes, and they are set with dmacb.ms[1:0]. 11.7.1.1. block transfer operation in the block transfer mode, dma transfer specified by number of block (dmaca/bc) is executed by 1 transfer request. when number of transfer (dmaca/tc) is set to other values than "0", tc is decremented for 1 after comp leting dma transfer of bc. after the la st transfer (bc is 4'h0 and tc is 16'h0000), dma transfer is completed. transfer gap after completing bc transfer, dmac negates bus request to arbiter for the moment in the block transfer mode. this operation prevents dmac from occupying the bus. transfer gap is able to be used to reflect register setting (e.g. disable/interruption setting) to dmac during dma transfer. transfer request software requirement, external request (dreq), and peripheral request (idreq) are valid in this mode. ? software request set "1" to dmaca/st and set 5'b00000 to dmaca/is ? external request set "0" to dmaca/st, and set 5'b01110 (rising edge of transfer request) or 5'b01111 (fa lling edge of transfer request) to dmaca/is ? peripheral request set "0" to dmaca/st, and set 5'b1**** (rising edge of transfer request) to dmaca/is when external request or peripheral request is select ed, dmac detects transfer request edge. when bc's dma transfer is executed by either of those requests, dmac is unable to detect the next transfer; however, it is able to detect the next transfer re quest after bc's dma transfer is completed.
11-17 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) restrictions when dma transfer is performed by external (dreq) or peripheral (idreq) request, there are restrictions for external and peripheral signal pins. 1. dreq/idreq dreq/idreq must be asserted at least 2 cycles of ahb clock ( hclk). there is no restriction for timing of negating dreq/idreq. after asserting dack/idack, dmac is able to accept new transfer request (edge of dreq/idreq) for the next dma transfer. 2. dack/idack after dmac transfers data to the destination addr ess, dack/idack are asserted during 1 cycle of ahb clock (hclk). when access to the destination is proceeded properly, this signal is asserted. if destination issues error, retry, or sp lit responses at ahb, it is not asserted. in the block transfer mode, these signals indicate dmac properly performs destination access. 3. deop/ideop basically, deop/ideop asserted for 1 ahb cloc k (hclk) cycle when dmac terminates dma transfer properly or abnorm ally. abnormal dma transf er includes following cases: ? forced termination by dstp/idstp ? forced termination by setting 1'b0 to dmaca/eb ? receiving error response from source/destination 4. dstp/idstp dstp/idstp are used to forcibly terminate dma tr ansfer, and asserting them during the transfer is valid (it is also valid to assert dstp/idstp while dma is not transferred due to transfer gap and interruption function.) when these signals are used to forcibly terminate dma transfer, they are not asserted until deop/ideop are asserted. 5. exceptional operation of deop/ideop when dstp/idstp are asserted immediately afte r asserting dreq/dstp, dmac may request bus to execute idle transfer. in this case, dmac ma y assert deop/ideop for 2 cycles or more of ahb clock (hclk.) the asserting period of deop/ideop depends on number of previous master transfer cycle. figure 1 1-2 shows example of this exceptional operation.
11-18 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) dack dreq deop dstp hclk hbusreqm ( hdmac ) hgrantm ( hdmac ) hmaster control hready idle hresp hdmac ok other master nonseq or seq read or write other maste r nonseq or seq read or write figure 11-2 example of exceptional operation for deop/ideop when dma transfer is performed by software reset, dreq/idreq, dack/idack, deop/ideop, and dstp/idstp are not valid. timing chart figure 11-3 shows block transfer in timing chart.
11-19 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) dreq dack deop dstp hclk haddr hwrite control external trigger software trigger dmaca[31:24] hwdata hrdata hbusreq hgrant hready hresp hmaster cpu hdmac cpu hdmac cpu ok s a da sa da s a da sa da htrans n n n n n n n n i i data data data data data data data 0x00 0xa0 dmaca[19:16] 0x0 0x1 bc 0x00 0x0 0x1 0x0 dmaca[15:0] 0x0 0x1 tc 0x0 dmacsa dmacda sa0 sa1 sa2 sa3 sa4 da0 da1 da2 da3 da4 break of transfer data figure 11-3 block transfer (for bc = 0x1 and tc = 0x1)
11-20 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) 11.7.1.2. burst transfer operation in the burst transfer mode, dma tr ansfer is executed for number of block multiplied by number of transfer (dmaca/bc dmaca/tc) with 1 request. when number of transfer (dmaca/tc) is set to othe r values than "0", tc is decremented for 1 after completing dma transfer. after the last transfer (bc is 4'h0 and tc is 16 'h0000), dma transfer is completed. transfer gap after completing dma transfer, dmac negates bus request to arbiter that transfer gap does not occur in the burst transfer mode. register setting change during dma transfer (e.g. disa ble/interruption setting) is reflected after completing dma transfer. transfer request software request, external (dreq), and periphe ral (idreq) requests are valid in this mode. ? software request set "1" to dmaca/st and set 5'b00000 to dmaca/is ? external request set "0" to dmaca/st, and set 5'b01110 (rising edge of transfer request) or 5'b01111 (fa lling edge of transfer request) to dmaca/is ? peripheral request set "0" to dmaca/st, and set 5'b1**** (rising edge of transfer request) to dmaca/is when external request or peripheral request is se lected, dmac detects transfer request edge. when dma transfer of bc tc is executed by either of those requ ests, dmac is unable to detect the next transfer; however, it is able to detect the ne xt transfer request af ter dma transfer of bc tc is completed.
11-21 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) restrictions when dma transfer is performed by external (dreq) and peripheral (idreq) requests, there are some restrictions for external and peripheral signal pins. 1. dreq/idreq dreq/idreq must be asserted at least 2 cycles of ahb clock ( hclk.) there is no restriction for timing of negating dreq/idreq. after completing dma transfer in bc tc and asserting dack/idack and deop/ideop, new transfer request (edge of dreq/idreq) is able to be accepted for the next dma transfer. 2. dack/idack after dmac transfers data to the destination addr ess, dack/idack are asserted for 1 cycle of ahb clock (hclk.) when access to the destination is proceeded properly, this signal is asserted. if destination issues error, retry, or split resp onses at ahb, this signal is not asserted. in the burst transfer mode, these signals indicat e that dmac performs destination access properly. 3. deop/ideop basically, deop/ideop are asserted for 1 ahb clock (hclk) cycle when dmac ends dma transfer properly or abnorm ally. abnormal dma transf er includes following cases: ? forced termination by dstp/idstp ? forced termination by setting 1'b0 to dmaca/eb ? receiving error response from source/destination 4. dstp/idstp dstp/idstp are used to forcibly terminate dma tr ansfer, and asserting them while the transfer is valid (it is also valid to assert dstp/idstp while dma is not transferred due to transfer gap and interruption function.) when these signals are used to forcibly terminate dma transfer, they are not asserted until deop/ideop are asserted. 5. exceptional operation of deop/ideop when dstp/idstp are asserted immediately af ter dreq/dstp are asserted, dmac may request bus to execute idle transfer. in this case, dmac may assert deop/ideop for 2 cycles or more of ahb clock (hclk.) the asserting period of deop/ideop depends on number of previous master transfer cycle. figure 1 1-4 shows example of this exceptional operation.
11-22 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) dack dreq deop dstp hclk hbusreqm(hdmac) hgrantm(hdmac) hmaster control hready idle read hresp noseq or seq read or write hdmac ok other master other master noseq or seq read or write figure 11-4 example of exceptional operation of deop/ideop when dma transfer is performed by software reset, dreq/idreq, dack/idack, deop/ideop, and dstp/idstp are not valid.
11-23 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) timing chart figure 11-5 shows burst tr ansfer in timing chart. dreq dack deop dstp hclk haddr hwrite control external trigger software trigger dmaca[31:24] hwdata hrdata hbusreq hgrant hready hresp hmaster cpu hdmac cpu ok sa da s a da sa da htrans n n n n n i n data data data data data data 0x00 0xa0 dmaca[19:16] 0x0 0x1 bc 0x00 0x0 0x1 0x0 dmaca[15:0] 0x0 0x1 tc 0x0 sa da n n data data figure 11-5 burst transmission (for bc = 0x1 and tc = 0x1)
11-24 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) 11.7.1.3. demand transfer operation in the demand transfer mode, dma transfer is execut ed for 1 time transfer wh en transfer request is asserted, and number of transfer is set to dmaca/tc registers. in this case, dmaca/bc is set to "0". in this mode, dmaca/bc values are ignored. dmaca/tc are decremented for 1 after completing dma transfer. therefore dma transfer ends after the last transfer (tc is16?h0000) is completed. transfer gap after completing 1 transfer, dmac negates bus request to arbiter for the moment even though transfer request is asserted. this operation prevents dmac from occupying bus. transfer gap is able to be used to reflect register setting (e.g. disable/interruption setting) to dmac during dma transfer. transfer request external (dreq) and peripheral (idreq) requests are valid in the demand transfer mode; however, software request setting is prohibited in this mode. ? external request set "0" to dmaca/st, and set 5'b01110 (h level of tr ansfer request) or 5'b01111 (l level of transfer request) to dmaca/is ? peripheral request set "0" to dmaca/st, and set 5'b1**** (h level of transfer request) to dmaca/is when external request or peripheral request is se lected, dmac detects transfer request level.
11-25 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) restrictions when dma transfer is performed by external (dreq) or peripheral (idreq) request, there are some restrictions for the external and peripheral signal pins. 1. dreq/idreq dreq/idreq must be asserted until dack/idack are asserted. after they are asserted, dreq/idreq need to be negated within ahb clock (hclk) cycle of "source access cycle + destination access cycle ? 1". when negation timing of dreq/idreq is sent against to the restrictions, dmac may start the next transfer operation. after completing 1 dmate transfer and dack/idack are asserted, dmac is able to receive new transfer request (dreq/idreq level) for the next dma transfer after the condition of negating time indicated above. 2. dack/idack after dmac transfers control signal to the sour ce address, dack/idack are asserted during 1 cycle of ahb clock (hclk.) in the demand tran sfer mode, these signals indicate that dmac receives demand transfer request. 3. deop/ideop basically, deop/ideop are asserted for 1 ahb clock (hclk) cycle when dmac ends dma transfer properly or abnorm ally. abnormal dma transf er includes following cases: ? forced termination by dstp/idstp ? forced termination by setting 1'b0 to dmaca/eb ? receiving error response from source/destination 4. dstp/idspt dstp/idstp are used to forcibly terminate dma tr ansfer. asserting them during dma transfer is valid (it is also valid to assert dstp/idstp while dma is not transferred due to transfer gap and interrupt function.) when these signals are used to forcibly terminate dma transfer, they are not asserted until deop/ideop are asserted. 5. exceptional operation of deop/ideop when dstp/idstp are asserted immediately af ter dreq/dstp are asserted, dmac may request bus to execute idle transfer. in this case, dmac may assert deop/ideop for 2 cycles or more of ahb clock (hclk.) the asserting period of deop/ideop depends on number of previous master transfer cycle. figure 1 1-6 shows example of this exceptional operation.
11-26 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) dack dreq deop dstp hclk hbusreqm(hdmac) hgrantm(hdmac) hmaster control hready idle read hresp noseq or seq read or write hdmac ok other master other master noseq or seq read or write figure 11-6 example of exceptional operation of deop/ideop
11-27 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) timing chart figure 11-7 shows demand transfer in timing chart. dreq dack deop dstp hclk haddr hwrite control external trigger hwdata hrdata hbusreq hgrant hready hresp hmaster cpu hdmac cpu ok sa da htrans n n i data data dmaca [ 19:16 ] 0x2 bc 0x1 0x0 dmaca[15:0] 0 x 0 tc 0x0 hdmac sa da nn i hdmac sa da n n i data data data data transfer gap transfer gap figure 11-7 demand transfer (for bc = 0x0 (should be 0) and tc = 0x2)
11-28 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) 11.7.2. beat transfer dmac supports beat transfer which means, in th is case, increment/lap burst of the amba standard. dmac has 64 byte fifo shared in all channels, and enables sequential source access and destination access. the beat transfer type is set by dmaca/bt bits. correlation to dmaca/bt and ahb of hburst is shown below. table 11-4 dmaca/bt and hburst dmaca/bt beat transfer type hburst dmaca/ms (mode select) block burst demand 4?b0000 normal single ok ok ok 4?b1000 single single ok ok ok 4?b1001 incr incr ok ok ng 4?b1010 wrap4 wrap4 ok ok ng 4?b1011 incr4 incr4 ok ok ng 4?b1100 wrap8 wrap8 ok ok ng 4?b1101 incr8 incr8 ok ok ng 4?b1110 wrap16 wrap16 ok ok ng 4?b1111 incr16 incr16 ok ok ng in the demand transfer, increment/lap burs t (incr* and wrap*) is unsupported. 11.7.2.1. normal and single transfer normal and single transfer methods are the same. single source access and si ngle destination access are executed alternately as shown in figure 11-2 and figure 11-3.
11-29 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) 11.7.2.2. increment and lap transfer when increment beat transfer (in cr, incr4, incr8 and incr16) or lap beat transfer (wrap4, wrap8, and wrap16) is set to dmaca/bt, sequential source access and destination access are executed by using 64 byte fifo of dmac. for the case of incr4 (dmaca/bt = 4'b1011), dmac performs 4 sequential source accesses. output data from the source is stored in fifo of dmac , then the data is driven to destination in sequence. hclk haddr hwrite control hwdata hrdata hbusreq hgrant hready hresp hmaster cpu hdmac cpu ok sa sa sa sa da da htrans n s s s s i n d4 d1 d1 dmaca [ 19:16 ] bc 0x0 dmaca [ 15:0 ] tc da da ss incr4 incr4 d2 d3 d2 d3 d4 0x0 figure 11-8 increment/lap beat transfer (example of incr4 block transfer)
11-30 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) 11.7.3. channel priority control dmac controls priority of each channel by dmacr/pr bits. 11.7.3.1. fixed priority when priority is set to dmacr/pr bits, priority order is fixed and bus is given to the lowest figure of channel. priority controller of dmac switches ch annel when active channel is in transfer gap. thus, when all channels are active at the same time, the lowest figure of channel (ch0) is able to be selected by priority controller to start transfer. for instance, active channel (ch0) temporarily loses the bus at transfer gap. then it is given to the second lowest figure of channel (ch1). if ch1 loses bus at transfer gap, it is given to ch0 again. as a result, those 2 channels are able to prefer entially acquire bus in the fixed priority mode. figure 11-9 shows defined channel in the fixed priority mode. hbusreqm hgrantm hbusreqm0 hbusreqm1 hbusreqm2 hbusreqm3 hbusreqm4 hbusreqm5 hbusreqm6 hbusreqm7 defined channel #0 #1 #0 #1 #0 #1 #0 #1 #2 #3 #2 #3 #2 #3 #2 hdmac interna l ahb figure 11-9 defined channel in the fixed priority
11-31 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) 11.7.3.2. rotate priority when priority is set to dmacr/pr bits, priority order rotates. after bus is given to the lowest figure of channel, pr iority controller of dmac switches channel at transfer gap of active channel. thus, when all channels become active at the same time , the lowest figure of chan nel (ch0) is selected by priority controller to enable transfer operation. in the rotate priority mode, all channels are able to acquire bus in rotation. for instance, active channel (ch0) temporarily loses the bus at tran sfer gap. then it is given to the second lowest figure of channel (ch1). if ch1 loses bus at transfer gap, it is given to the third lowest figure of channel (ch2.) figure 11-10 shows defined channel in the rotate priority mode. hbusreqm hgrantm hbusreqm0 hbusreqm1 hbusreqm2 hbusreqm3 hbusreqm4 hbusreqm5 hbusreqm6 hbusreqm7 defined channel #0 #1 #2 #3 #4 #5 #6 #7 #0 #1 #2 #3 #4 #5 #6 hdmac interna l ahb figure 11-10 defined channel in the rotate priority
11-32 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) 11.7.4. retry, split, and error dmac supports retry and split responses of ahb slave. 11.7.4.1. retry and split when dmac receives retry or sp lit responses from ahb slave during dma transfer, dmac negates bus temporarily to construct the contents to be retransmitted. figure 11-11 shows example of receiving ret ry response at incr4 dma transfer. hclk haddr hwrite control hwdat a hrdata hbusreq hgrant hready hresp hmaster cpu hdmac cpu ok sa sa sa sa da da htrans n s s s s i n d4 d1 d1 dmaca [ 19:16 ] bc 0x0 dmaca [ 15:0 ] tc da da ss incr4 incr4 d2 d3 d2 d3 d4 0x0 retry ok hdmac da n i d4 incr figure 11-11 increment/lap beat transf er (example of incr4 block transfer) when dmac negates bus temporarily, the channel recei ved retry/split responses is continuously selected by dmac's priority controller that transfer operation is able to start even though higher priority channel requests the bus
11-33 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) 11.7.4.2. error when dmac receives error reply from ahb slave du ring dma transfer, dmac negates bus request and immediately stops the transfer even though it is not completed. in this case, neither block/transfer count register nor source/destina tion address register is updated.
11-34 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) 11.8. example of dmac setting 11.8.1. dma start in single channel example of block and burst transfer by software request (with dmac ch0) ` (2) set dmac source address register dmacsa0 0x0000_0000 (1) set dma configuration register dmacr 0x80 (byte writing) sauce address is set. dma transfer is enabled. (3) set dmac destination address register dmacda0 0x0100_0000 (4) set dma configuration b register dmacb0 0x0808_0000 destination address is set. transfer mode, transfer data width, and completion interrupt are set. in this example, block transfer mode (ms[1:0] = 0 h ) is set as transfer mode. burst transfer mode is able to be set by ms[1:0] = 1 h . dma channel transfer control, software trigger, and number of block and transfer are set. (5) set dma configuration a register dmaca0 0xa00f_000f start dma transfer remark: setting order of step 1 ~ 4 is arbitrary; however, the one of step 5 is unable to be changed. figure 11-12 example of block and burst transfer by software request (with dmac ch0) note: ? dma configuration register (dmacr) should be set by byte writing. ? for block and burst transfer with software re quest, dma configuration a register (dmaca) should be set at the end.
11-35 MB86R01 lsi product specifications fujitsu semiconductor confidential dma controller (dmac) example of demand transfer by software request (with dmac ch0) ` (2) set dmac source address register dmacsa0 0x0100_8000 (1) set dma configuration register dmacr 0x80 (byte writing) source address is set. dma transfer is enabled. (3) set dmac destination address register dmacda0 0xfffe_1000 (4) set dma configuration b register dmacb0 0x2100_0000 destination address is set. transfer mode, transfer data width, and completion interrupt is set. dma channel transfer control, software trigger, and number of block and transfer are set. (5) set dma configuration a register dmaca0 0x9000_000a start dma transfer remark: setting order of step 1 ~ 5 is arbitrary; however, the last setting should be step 1 or 5. figure 11-13 example of demand transfer by software request (with dmac ch0) note: ? dma configuration register (dmacr) should be set by byte writing. 11.8.2. dma start in all channels (in demand transfer mode) all channels are able to start simultaneously by setting dmacr register after setting all dma channels' register in the demand transfer mode. in this case, dmac priority controller receives request of all channels at the same time, then transfer starts by selecting channel according to dma channel priority, which is settable with pr bit of the dmacr.
12-1 MB86R01 lsi product specifications fujitsu semiconductor confidential timer (timer) 12. timer (timer) this chapter describes function and spec of timer. 12.1. outline timer is 2 channel timer module which is able to set 32/16 bit. 12.2. feature timer has following features: ? 32/16 bit counter 2 (bit width is controllable with register) ? supplying 2 interrupt request signals to interrupt controller ? timer clock prescaler unit ? 3 operation modes: ? free-run mode ? cycle timer mode ? one-shot mode ? using apb clock as base clock of the timer 12.3. supply clock apb clock is supplied to timer. refer to "5. clock reset generator (crg)" for frequency setting and control specification of the clock. 12.4. specification timer in MB86R01 uses adkr2p0 (amba design kit) timer module of arm ltd. refer to dual input timer of the amba design kit technical reference manual for detail spec of the timer.
13-1 MB86R01 lsi product specifications fujitsu semiconductor confidential general-purpose input/output port (gpio) 13. general-purpose input/output port (gpio) this chapter describes function and operation of general-purpose input/output port (gpio.) 13.1. outline MB86R01 has max. 24 bit of gpio port which is in common with other peripheral ports. refer to "1.6.1 pin multiplex" for shared peripherals. direction control and data reading/writing of gpio port is performed with using gpio control register. 13.2. feature gpio has following features: ? supplied 24 bit gpio port ? composed of following 2 registers ? port data register (gpdr) ? data direction register (gpddr) 13.3. block diagram figure 13-1 shows block diagram of gpio controller. in MB86R01, 24pcs. of these blocks are equipped. i/o cell gpio module a pb gpddr gpd r (out) external port 1 0 read data of pdr write data gpd r (in) pi po pc figure 13-1 block diagram of gpio module 13.4. supply clock apb clock is supplied to gpio. refer to "5. cl ock reset generator (crg)" for frequency setting and control specification of the clock.
13-2 MB86R01 lsi product specifications fujitsu semiconductor confidential general-purpose input/output port (gpio) 13.5. register this section describes detail of register in gpio. 13.5.1. register list table 13-1 shows list of gpio register. table 13-1 gpio register list address base offset register abbreviation description + 00 h port data register 0 gpdr0 setting of input/output data of gpio_pd[7:0] pin + 04 h port data register 1 gpdr1 setting of input/output data of gpio_pd[15:8] pin + 08 h port data register 2 gpdr2 setting of input/output data of gpio_pd[23:16] pin + 0c h (reserved) ? reserved area (access prohibited) + 10 h data direction register 0 gpddr0 control of input/output direction of gpio_pd[7:0] pin + 14 h data direction register 1 gpddr1 control of input/output direction of gpio_pd[15:8] pin fffe_9000 h + 18 h data direction register 2 gpddr2 control of input/output direction of gpio_pd[23:16] pin + 1c h ? + fff h (reserved) ? reserved area (access prohibited)
13-3 MB86R01 lsi product specifications fujitsu semiconductor confidential general-purpose input/output port (gpio) description format of register following format is used for descri ption of register?s each bit in " 13.5.2 port data register 0-2 (gpdr0- 2)" t o " 13.5.3 data direction register 0-2 (gpddr2-0)". address base address + offset bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r/w initial value bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r/w initial value meaning of item and sign address address (base address + offset address) of the register bit bit number of the register name bit field name of the register r/w attribution of read/write of each bit field ? r0:read value is always "0" ? r1: read value is always "1" ? w0: write value is always "0", and write access of "1" is ignored ? w1: write value is always "1", and write access of "0" is ignored ? r: read ? w: write initial value each bit field?s value after reset ? 0: value is "0" ? 1: value is "1" ? x: value is undefined
13-4 MB86R01 lsi product specifications fujitsu semiconductor confidential general-purpose input/output port (gpio) 13.5.2. port data register 0-2 (gpdr0-2) gpdr0 - 2 registers are to set input/output data of gpio port, and their corresponding gpio pin is as follows. ? gpdr0: gpio bit 7 - 0 (gpio_pd[7:0] pin) ? gpdr1: gpio bit 15 - 8 (gpio_pd[15:8] pin) ? gpdr2: gpio bit 23 - 16 (gpio_pd[23:16] pin) input/output directions of each gpio are determined by the corresponding bit of gpddr0 - 2 registers. address gpdr0: fffe_9000 h + 00 h gpdr1: fffe_9000 h + 04 h gpdr2: fffe_9000 h + 08 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) pdr0_7 pdr1_15 pdr2_23 pdr0_6 pdr1_14 pdr2_22 pdr0_5 pdr1_13 pdr2_21 pdr0_4 pdr1_12 pdr2_20 pdr0_3 pdr1_11 pdr2_19 pdr0_2 pdr1_10 pdr2_18 pdr0_1 pdr1_9 pdr2_17 pdr0_0 pdr1_8 pdr2_16 r/w ? ? ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x x bit field no. name description 31-8 (reserved) reserved bits. write access is ignored. read valu e of these bits is undefined. 7-0 pdr0_7-0 gpdr0 register's bit field. the register is setting register of gpio_pd[7:0] pin's input/output data, and each bit corresponds to gpio pin as follows. ? pdr0_7: gpio_pd[7] pin ? pdr0_6: gpio_pd[6] pin ? pdr0_5: gpio_pd[5] pin ? pdr0_4: gpio_pd[4] pin ? pdr0_3: gpio_pd[3] pin ? pdr0_2: gpio_pd[2] pin ? pdr0_1: gpio_pd[1] pin ? pdr0_0: gpio_pd[0] pin input/output directions of gpio_pd[7] - gpio_pd[0] pins are determined by the correspondence bit of the gpddr0 register. initial value of these bits is undefined. pdr1_15-8 gpdr1 register's bit field. this register is setting register of gpio_p d[15:8] pin's input/output data, and each bit corresponds to gpio pin as follows. ? pdr1_15: gpio_pd[15] pin ? pdr1_14: gpio_pd[14] pin ? pdr1_13: gpio_pd[13] pin ? pdr1_12: gpio_pd[12] pin ? pdr1_11: gpio_pd[11] pin ? pdr1_10: gpio_pd[10] pin ? pdr1_09: gpio_pd[9] pin ? pdr1_08: gpio_pd[8] pin input/output directions of gpio_pd[15] - gpio_pd[8] pi ns are determined by the corresponding bit of the gpddr1 register. initial value of these bits is undefined.
13-5 MB86R01 lsi product specifications fujitsu semiconductor confidential general-purpose input/output port (gpio) bit field no. name description 7-0 pdr2_23-16 gpdr2 register's bit field. this register is setting register of gpio_p d[23:16] pin's input/output data, and each bit corresponds to gpio pin as follows. ? pdr2_23: gpio_pd[23] pin ? pdr2_22: gpio_pd[22] pin ? pdr2_21: gpio_pd[21] pin ? pdr2_20: gpio_pd[20] pin ? pdr2_19: gpio_pd[19] pin ? pdr2_18: gpio_pd[18] pin ? pdr2_17: gpio_pd[17] pin ? pdr2_16: gpio_pd[16] pin input/output directions of gpio_pd[23] - gpio_pd[16] pi ns are determined by the corresponding bit of the gpddr2 register. initial value of these bits is undefined.
13-6 MB86R01 lsi product specifications fujitsu semiconductor confidential general-purpose input/output port (gpio) 13.5.3. data direction register 0-2 (gpddr2-0) gpddr0 - 2 registers are to control input/output directions of gpio port, and their corresponding gpio pin is as follows. ? gpddr0: gpio bit 7 - 0 (gpio_pd[7:0] pin) ? gpddr1: gpio bit 15 - 8 (gpio_pd[15:8] pin) ? gpddr2: gpio bit 23 - 16 (gpio_pd[23:16] pin) address gpddr0: fffe_9000 h + 10 h gpddr1: fffe_9000 h + 14 h gpddr2: fffe_9000 h + 18 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) ddr0_7 ddr1_15 ddr2_23 ddr0_6 ddr1_14 ddr2_22 ddr0_5 ddr1_13 ddr2_21 ddr0_4 ddr1_12 ddr2_20 ddr0_3 ddr1_11 ddr2_19 ddr0_2 ddr1_10 ddr2_18 ddr0_1 ddr1_9 ddr2_17 ddr0_0 ddr1_8 ddr2_16 r/w ? ? ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x 0 0 0 0 0 0 0 0 bit field no. name description 31-8 (reserved) reserved bits. write access is ignored. read va lue of these bits is undefined. 7-0 ddr0_7-0 gpdr0 register's bit field. this register controls input/output directions of gpio_pd[7:0] pin. 0 gpio becomes input port 1 gpio becomes output port gpio pin corresponding to this register is as follows: ? ddr0_7: gpio_pd[7] pin ? ddr0_6: gpio_pd[6] pin ? ddr0_5: gpio_pd[5] pin ? ddr0_4: gpio_pd[4] pin ? ddr0_3: gpio_pd[3] pin ? ddr0_2: gpio_pd[2] pin ? ddr0_1: gpio_pd[1] pin ? ddr0_0: gpio_pd[0] pin these bits are initialized to "0" by reset.
13-7 MB86R01 lsi product specifications fujitsu semiconductor confidential general-purpose input/output port (gpio) bit field no. name description 7-0 ddr1_15-8 gpddr1 register's bit field. this register controls input/output directions of gpio_pd[15:8] pin. 0 gpio becomes input port 1 gpio becomes output port gpio pin corresponding to this register is as follows: ? ddr1_15: gpio_pd[15] pin ? ddr1_14: gpio_pd[14] pin ? ddr1_13: gpio_pd[13] pin ? ddr1_12: gpio_pd[12] pin ? ddr1_11: gpio_pd[11] pin ? ddr1_10: gpio_pd[10] pin ? ddr1_9: gpio_pd[9] pin ? ddr1_8: gpio_pd[8] pin these bits are initialized to "0" by reset. ddr2_23-16 gpddr2 register's bit field. this register controls input/output directions of gpio_pd[23:16] pin. 0 gpio becomes input port 1 gpio becomes output port gpio pin corresponding to this register is as follows: ? ddr2_23: gpio_pd[23] pin ? ddr2_22: gpio_pd[22] pin ? ddr2_21: gpio_pd[21] pin ? ddr2_20: gpio_pd[20] pin ? ddr2_19: gpio_pd[19] pin ? ddr2_18: gpio_pd[18] pin ? ddr2_17: gpio_pd[17] pin ? ddr2_16: gpio_pd[16] pin these bits are initialized to "0" by reset.
13-8 MB86R01 lsi product specifications fujitsu semiconductor confidential general-purpose input/output port (gpio) 13.6. operation this section describes gpio operation. 13.6.1. direction control direction of gpio port (bit 23 ? 0) and its each bit is able to change by the gpddrx register. initial direction (ddrx bit's initial value of the gpddrx register) after reset is "0" (input port.) note: notice for bus conflict at cha nging gpio port direction. 13.6.2. data transfer when gpio port is used as input port (ddrx = 0), the data signal input to the port input signal (pi) is stored to pdrx (in) at rising edge of apb clock (see figure 13-1 . ) re ading gpdrx register enables to observe input data. during the period, write access to the gpdrx register is valid that pdrx (out) is changeable except at ddrx = 0. when gpio port is used as output port (ddr = 1), gpdrx register value is output to the port output signal (po); in that time, read data of the register becomes the same value as the port output signal's.
14-1 fujitsu semiconductor confidential pwm MB86R01 lsi product specifications 14. pwm this chapter describes operation and function of pwm (pulse width modulator.) 14.1. outline MB86R01 has 2 channels of pwm which is able to output high-precision pwm wave pattern efficiently. 14.2. feature pwm has following features: ? built-in 2 channels ? individually setting of duty ratio, phase, and polarity ? specifying one-shot output/continuous output of the pulse
14-2 fujitsu semiconductor confidential pwm MB86R01 lsi product specifications 14.3. block diagram figure 14-1 shows block diagram of pwm. cl k generator apb bus pulse generator pwm module apb i/f irc pwm_o0 pwm_o1 int figure 14-1 pwm block diagram 14.4. related pin pwm uses following pins. pin direction qty. description pwm_o0 pwm_o1 out 2 pwm0/1 output pwm pin is common with other peripheral i/o functions. to use the pin, its function should be set by either of followings to be selected to pwm side. ? set to mpx_mode_2[2:0] = "000 b " of multiplex mode setting register ? set to mpx_mode_4[1:0] = "01 b " of multiplex mode setting register ? set to mpx_mode_5[1] pin = "h" and mpx_mode_5[0] pin = "l" when these are set in multiples and pwm function is selected, the set pin makes pwm pin valid in parallel. 14.5. supply clock apb clock is supplied to pwm. refer to "5. clock reset generator (crg)" for frequency setting and control specification of the clock. 14.6. interrupt when interrupt factor occurs, pwm notifies it to irc. refer to "7. interrupt controller (irc)" for more detail.
14-3 fujitsu semiconductor confidential pwm MB86R01 lsi product specifications 14.7. register this section describes pwm register. 14.7.1. register list this lsi equips 2 channels of pwm, and each of them has register shown in table 14-1. t able 14-1 pwm register list address channel base offset register abbreviation description pwm ch0 fff4_1000 h + 00 h pwm ch0 base clock register pwm0bcr setting base clock of pwm cycle (output pin pwm_o0) + 04 h pwm ch0 pulse width register pwm0tp r setting cycle length of 1 pulse + 08 h pwm ch0 phase register pwm0pr setting phase cycle of the pulse + 0c h pwm ch0 duty register pwm0dr setting duty cycle of the pulse + 10 h pwm ch0 status register pwm0cr setti ng pwm such as pulse output format and polarity + 14 h pwm ch0 start register pwm0sr setting start/stop of pwm + 18 h pwm ch0 current count register pwm0ccr indicating current count value in the baseclk base + 1c h pwm ch0 interrupt register pwm0ir se lecting cause of pwm interrupt factor pwm ch1 fff4_1100 h + 00 h pwm ch1 base clock register pwm1bcr setting base clock of pwm cycle (output pin pwm_o1) + 04 h pwm ch1 pulse width register pwm1tp r setting cycle length of 1 pulse + 08 h pwm ch1st place aspect register pwm1pr setting phase cycle of the pulse + 0c h pwm ch1 duty register pwm1dr setting duty cycle of the pulse + 10 h pwm ch1 status register pwm1cr setti ng pwm such as pulse output format and polarity + 14 h pwm ch1 start register pwm1sr setting start/stop of pwm + 18 h pwm ch1 current count register pwm1ccr indicating current count value in the baseclk base + 1c h pwm ch1 interrupt register pwm1ir se lecting cause of pwm interrupt factor note: access pwm ch0 and pwm ch1 ar eas with 32 bit (word.)
14-4 fujitsu semiconductor confidential pwm MB86R01 lsi product specifications description format of register following format is used for descri ption of register?s each bit in " 14.7.2 pwmx base clock register (pw mxbcr)" to " 14.7.9 pwmx interrupt register (pwmxir)". address base address + offset bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r/w initial value bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r/w initial value meaning of item and sign address address (base address + offset address) of the register bit bit number of the register name bit field name of the register r/w attribution of read/write of each bit field ? r0:read value is always "0" ? r1: read value is always "1" ? w0: write value is always "0", and write access of "1" is ignored ? w1: write value is always "1", and write access of "0" is ignored ? r: read ? w: write initial value each bit field?s value after reset ? 0: value is "0" ? 1: value is "1" ? x: value is undefined
14-5 fujitsu semiconductor confidential pwm MB86R01 lsi product specifications 14.7.2. pwmx base clock register (pwmxbcr) this register is to set base clock of pwm cycle. address ch0 fff4_1000 + 00 h ch1 fff4_1100 + 00 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bcr[15:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-16 (reserved) reserved bits. the write access is ignored. the read value of these bits is always "0". 15-0 bcr base clock of the pwm cycle is set. bcr[15:0] base clock 0 0 apbclk (setting prohibited) 1 1 apbclk | | 65535 65535 apbclk
14-6 fujitsu semiconductor confidential pwm MB86R01 lsi product specifications 14.7.3. pwmx pulse width register (pwmxtpr) this register is to set cycle length of 1 pulse. address ch0 fff4_1000 + 04 h ch1 fff4_1100 + 04 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tpr[15:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-16 (reserved) reserved bits. the write access is ignored. the read value of these bits is always "0". 15-0 tpr cycle length of 1 pulse shown in figure 14-2 is set. tpr[15:0] pulse cycle length 0 0 baseclk (setting prohibited) 1 1 baseclk (setting prohibited) 2 2 baseclk | | 65535 65535 baseclk a pbclk baseclk pwm phase duty next cycle (skippable) pulse width (1 cycle) figure 14-2 setting parameter
14-7 fujitsu semiconductor confidential pwm MB86R01 lsi product specifications 14.7.4. pwmx phase register (pwmxpr) this register is to set phase cycle of the pulse. address ch0 fff4_1000 + 08 h ch1 fff4_1100 + 08 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pr[15:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-16 (reserved) reserved bits. the write access is ignored. the read value of these bits is always "0". 15-0 pr phase cycle shown in figure 14-3 is set. p r[15:0] phase cycle 0 0 baseclk (setting prohibited) 1 1 baseclk | | 65535 65535 baseclk a pbclk baseclk pwm phase duty next cycle (skippable) pulse width (1 cycle) figure 14-3 setting parameter
14-8 fujitsu semiconductor confidential pwm MB86R01 lsi product specifications 14.7.5. pwmx duty register (pwmxdr) this register is to set duty cycle of the pulse. address ch0 fff4_1000 + 0c h ch1 fff4_1100 + 0c h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dr[15:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-16 (reserved) reserved bits. the write access is ignored. the read value of these bits is always "0". 15-0 dr duty cycle shown in figure 14-4 is set. dr[15:0] duty cycle 0 0 baseclk (setting prohibited) 1 1 baseclk | | 65535 65535 baseclk a pbclk baseclk pwm phase duty next cycle (skippable) pulse width (1 cycle) figure 14-4 setting parameter
14-9 fujitsu semiconductor confidential pwm MB86R01 lsi product specifications 14.7.6. pwmx status register (pwmxcr) this register is to set pwm such as pulse output format and polarity. address ch0 fff4_1000 + 10 h ch1 fff4_1100 + 10 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) oneshot (reserved) pol r/w r r r r r r r r r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-4 (reserved) reserved bits. the write access is ignored. the read value of these bits is always "0". 3 oneshot pulse output format, either cont inuous output or one-shot output is set. 0 continuous output (initial value) 1 one-shot output 2-1 (reserved) reserved bits. write "0" to these bits. read value of these bits is undefined. note: writing "1" to these bits is prohibited. 0 pol polarity of the pulse is set. 0 negative pulse (initial value) 1 positive pulse
14-10 fujitsu semiconductor confidential pwm MB86R01 lsi product specifications 14.7.7. pwmx start register (pwmxsr) this register is to set pwm start-up/stop. address ch0 fff4_1000 + 14 h ch1 fff4_1100 + 14 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) start r/w r r r r r r r r r r r r r r r r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-1 (reserved) reserved bits. the write access is ignored. the read value of these bits is always "0". 0 start start-up/stop of pwm are set. 0 stop (initial value) 1 start-up after pulse cycle ends, this bit is cl eared to "0" when onshot bit = 1 of pwmxcr register.
14-11 fujitsu semiconductor confidential pwm MB86R01 lsi product specifications 14.7.8. pwmx current count register (pwmxccr) this register is to indicate current count value in baseclk base. address ch0 fff4_1000 + 18 h ch1 fff4_1100 + 18 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ccr[15:0] r/w r r r r r r r r r r r r r r r r initial value x x x x x x x x x x x x x x x x bit field no. name description 31-16 (reserved) reserved bits. the write access is ignored. the read value of these bits is always "0". 15-0 ccr current count value in baseclk base is indicated. ccr[15:0] duty cycle 0 0 baseclk 1 1 baseclk | | 65535 65535 baseclk
14-12 fujitsu semiconductor confidential pwm MB86R01 lsi product specifications 14.7.9. pwmx interrupt register (pwmxir) this register is to select cause of pwm interrupt. address ch0 fff4_1000 + 1c h ch1 fff4_1100 + 1c h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) intrep[1:0] (reserved) done r/w r r r r r r r/w r/w r r r r r r r/w1 r/w1 initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-10 (reserved) reserved bits. the write access is ignored. the read value of these bits is always "0". 9-8 intrep[1:0] the bit (done bit) which might be the cause of pwm in terrupt is selected. intrep[1:0] possible cause bit for pwm interrupt 00 done bit is not selected 01 done bit is selected as cause of interrupt factor 10 (setting prohibited) 11 (setting prohibited) 7-1 (reserved) reserved bits. the write access is ignored. the read value of these bits is always "0". 0 done this bit indicates end of 1 pulse cycle. 0 1 pulse is not output (initial value) 1 1 pulse is output this bit is cleared to "0" by writing "1".
14-13 fujitsu semiconductor confidential pwm MB86R01 lsi product specifications 14.8. example of setting register this section describes example of register's initial setting. power-on set pwmx base clock register (pwmxbcr) set polarity (pol) and one-shot (oneshot) pulses set pwmx p ulse width re g ister (pwmxtpr) set pwmx phase register (pwmxpr) set pwmx dut y re g ister (pwmxdr) set pwmx status register (pwmxcr) set pwmx activation register (pwmxsr) pwm activates pwmx interrupt register's intrep bit output 1 pulse cycle ye s interrupt occurs no pwmxsr start bit = 1 ye s no end pwm stops with negating start bit (pwmxsr start bit) at completing pulse cycle, not immediately after negating the start bit set each register in the following condition: ? pwmx base clock register 1 ? pwmx phase register 1 ? pwmx duty register 1 ? pwmx phase register + pwmx duty register pwmx pulse width register 2 (the next phase setting after duty operation is omitted) figure 14-5 pwm register initial setting example
15-1 MB86R01 lsi product specifications fujitsu semiconductor confidential a/d converter 15. a/d converter this chapter describes function and operation of a/d converter. 15.1. outline MB86R01 has 2 channels of a/d converter. 15.2. feature ? successive approximation a/d converter ? max. conversion rate: approx. 648k sample/sec, 10 bit resolution ? immediate reading operation of a/d value by analog data auto. polling operation ? a/d converter operation clock dividing ratio can be selected ? 1/4 (apb clock is 41.5mhz: approx. 648.4k sample/sec) ? 1/8 (apb clock is 41.5mhz: approx. 324.1k sample/sec) ? 1/16 (apb clock is 41.5mhz: approx. 162.0k sample/sec) ? 1/32 (apb clock is 41.5mhz: approx. 81.0k sample/sec) ? 1/64 (apb clock is 41.5mhz: approx. 40.5k sample/sec) ? 1/256 (apb clock is 41.5mhz: approx. 10.1k sample/sec) ? 1/1024 (apb clock is 41.5mhz: approx. 2.5k sample/sec) ? 1/4096 (apb clock is 41.5mhz: approx. 0.6k sample/sec)
15-2 MB86R01 lsi product specifications fujitsu semiconductor confidential a/d converter 15.3. block diagram figure 15-1 shows block diagram of a/d converter. apb if apb if ad_vr0/ad_vr1 a/d converter 10bit dac 10bit register sar sample & hold external ad_vrh0/ad_vrh1 ad_vrl0/ad_vrl1 comparator ad_vin0/ad_vin1 figure 15-1 block diagram of a/d converter 15.4. related pin a/d converter uses following pins. table 15-1 a/d converter related pin pin direction qty. description ad_vin0 in 1 a/d analog input pin ad_vin1 in 1 a/d analog input pin ad_vrh0 in 1 reference voltage "h" input pin ad_vrh1 in 1 reference voltage "h" input pin ad_vrl0 in 1 reference voltage "l" input pin ad_vrl1 in 1 reference voltage "l" input pin ad_vr0 out 1 reference output ad_vr1 out 1 reference output ad_avd0 in 1 analog power supply pin ad_avs1 in 1 analog gnd 15.5. supply clock apb clock is supplied to a/d converter. refer to "5. clock reset generator (crg)" for frequency setting and control specification of the clock.
15-3 MB86R01 lsi product specifications fujitsu semiconductor confidential a/d converter 15.6. output truth value list example of truth value of a/d converter is shown below. table 15-2 a/d converter's truth value example list ideal input level output code vin[v] d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 2.2485 ... h h h h h h h h h h 2.2471 ... 2.2485 h h h h h h h h h l 2.2456 ... 2.2471 h h h h h h h h l h 0.7515 ... 0.7529 l l l l l l l l l h ... 0.7515 l l l l l l l l l l note: ad_avd0 = 3.0v, ad_vrh0/ad_vrh1 = 2.25v, ad_ vrl0/ad_vrl1 = 0.75v
15-4 MB86R01 lsi product specifications fujitsu semiconductor confidential a/d converter 15.7. analog pin equivalent circuit figure 15-2 shows analog pin's equivalent circuit of a/d converter. sample c equivalent circuit in sampling period ?sample? is internal signal vr0 internal pd 2 r r 2 r r internal pd 2 r r avd0 ad_avs1 2 r r internal pd ad_vrh0/ad_vrh1 ad_vrl0/ad_vrl1 vin0/vin1 figure 15-2 analog pi n's equivalent circuit
15-5 MB86R01 lsi product specifications fujitsu semiconductor confidential a/d converter 15.8. register this section describes a/d converter register. 15.8.1. register list this lsi has 2 channels of a/d converter unit, and each unit has the register shown in table 15-3. t able 15-3 adc register list address channel base offset register abbreviation description adc ch0 fff5_2000 h + 00 h adc ch0 data register adc0data a/d converted data is stored + 04 h (reserved) ? reserved area, access prohibited + 08 h adc ch0 power down control register adc0xpd power down mode is set/released + 0c h (reserved) ? reserved area, access prohibited + 10 h adc ch0 clock selection register adc0cksel clock frequency is supplied to a/d converter + 14 h adc ch0 status register adc0status a/d conve rted data is stored to data register adc ch1 fff5_3000 h + 00 h adc ch1 data register adc1data a/d converted data is stored + 04 h (reserved) ? reserved area, access prohibited + 08 h down of adc ch1 power control register adc1xpd power down mode is set/released + 0c h (reserved) ? reserved area, access prohibited + 10 h adc ch1 clock selection register adc1cksel clock frequency is supplied to a/d converter + 14 h adc ch1 status register adc1status a/d conve rted data is stored to data register note: access adc ch0 and adc ch1 ar eas with 32 bit (word.)
15-6 MB86R01 lsi product specifications fujitsu semiconductor confidential a/d converter description format of register following format is used for descri ption of register?s each bit in " 15.8.2 adcx data register (a dcxdata)" to " 15.8.4 adcx clock selection register (adcxcksel)". address base address + offset bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r/w initial value bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r/w initial value meaning of item and sign address address (base address + offset address) of the register bit bit number of the register name bit field name of the register r/w attribution of read/write of each bit field ? r0:read value is always "0" ? r1: read value is always "1" ? w0: write value is always "0", and write access of "1" is ignored ? w1: write value is always "1", and write access of "0" is ignored ? r: read ? w: write initial value each bit field?s value after reset ? 0: value is "0" ? 1: value is "1" ? x: value is undefined
15-7 MB86R01 lsi product specifications fujitsu semiconductor confidential a/d converter 15.8.2. adcx data register (adcxdata) this register is to store a/d converted data. address ch0 fff5_2000 + 00 h ch1 fff5_3000 + 00 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) data[9:0] r/w r0 r0 r0 r0 r0 r0 r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-10 (reserved) it is a reserved bit. write access is ignored. read valu e of these bits is always "0". 9-0 data[9:0] output data from a/d convert er is stored with polling operation. when power down mode is set to release at adcx power down control register (adcxxpd), data is imported to this register. 15.8.3. adcx power down contro l register (adcxxpd) this register is to control a/d converter operation. address ch0 fff5_2000 + 08 h ch1 fff5_3000 + 08 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) xpd r/w r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-1 (reserved) it is a reserved bit. write access is ignored. read valu e of these bits is always "0". 0 xpd a/d converter operation is controlled. 0 power down mode (initial value) 1 release of power down mode when "1" is written to xpd bit, a/d converter 's power-down mode is released and a/d data polling starts. writing "0" to the bit sets a/ d converter's power-down mode and a/d data polling stops.
15-8 MB86R01 lsi product specifications fujitsu semiconductor confidential a/d converter 15.8.4. adcx clock selection register (adcxcksel) this register is to se to specify adc clock frequency supplying to a/d converter. this setting enables sampling plate change. address ch0 fff5_2000 + 10 h ch1 fff5_3000 + 10 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) cksel[2:0] r/w r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-3 (reserved) it is a reserved bit. write access is ignored. read valu e of these bits is always "0". 2-0 cksel[2:0] specify clock freque ncy supplying to a/d converter. cksel[2:0] clock frequency sett ing sampling late [sample/sec.] 000 b 1/4096 0.6k 001 b 1/1024 2.5k 010 b 1/256 10.1k 011 b 1/64 40.5k 100 b 1/32 81.0k 101 b 1/16 162.0k 110 b 1/8 324.1k 111 b 1/4 648.4k this clock is made dividing apb clock (41.5mhz.) analog voltage sampling is carried out every 16 cycles of clock set in this register.
15-9 MB86R01 lsi product specifications fujitsu semiconductor confidential a/d converter 15.8.5. adcx status register (adcxstatus) this register is to indicate whether a/d data conversion is completed. address ch0 fff5_2000 + 14 h ch1 fff5_3000 + 14 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) cmp r/w r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r/w0 initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-1 (reserved) it is a reserved bit. write access is ignored. read valu e of these bits is always "0". 0 cmp whether a/d data conversio n is completed is indicated. 0 a/d data conversion is not completed (initial value) 1 a/d data conversion is completed at the time data is set to adcxdata, cmp bit becomes "1". writing "0" to the bit clears register value (although "1" is written to cmp bi t, register bit value does not change.) setting "1" to cmp bit outputs interrupt.
15-10 MB86R01 lsi product specifications fujitsu semiconductor confidential a/d converter 15.9. basic operation flow basic operation flow of adc is shown below. set of adcxcksel write "0x0 - 0x7" to adcxcksel register power-on after 16 adc clocks, analog data is converted into digital data set of adcxxpd write "0x1" to adcxxpd register (the polling of data starts) * the data value is updated only every 16 adc clocks though adcxdata register can be read at any time. set converted a/d data to adcxdata register. (a range of data is "0x0 - 0x3ff") the value of adcxstatus register doesn't change if adcxstatus register is "0x1". if adcxstatus register is "0x0", the value of adcxstatus register becomes "0x1". int clear? int no yes set of adcxstatus write "0x0" to adcxstatus register figure 15-3 ad convert er's basic operation flow
16-1 MB86R01 lsi product specifications fujitsu semiconductor confidential graphics display controller (gdc) 16. graphics display controller (gdc) refer to another document, MB86R01/r03 lsi product specifications graphics display controller (gdc) for the controller spec.
17-1 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) 17. serial audio interface (i2s) this chapter describes function and operation of serial audio interface (hereafter called, i2s.) 17.1. outline MB86R01 equips audio i/o interface in i2s format, and up to 3 channels are able to be used. note: i2s is inter-ic sound bus advocated by philips semiconductors (now nxp). 17.2. feature i2s interface in MB86R01 has following features: ? selecting master/slave operations by programmable ? supporting state of transmission only, recepti on only, and simultaneous transmission and reception ? selecting 1 sub frame and 2 sub frame constructions ? setting up to 32 channels to each sub frame ? individually setting number of channel in each sub frame ? individually setting channe l length of each sub frame (number channel bit) ? individually setting word length in channel of each sub frame (corresponding to msb-justified) ? setting valid/invalid of each channel in each sub frame (note 1) ? setting word length from 7 to 32 bit ? programming frequency of frame synchronous signal ? setting up to 3071 bit in 1 frame ? programming width of frame synchronous signal (1 bit or 1 channel length) ? programming phase of frame synchronous signal (0 bits or 1 bit delay) ? setting polarity of frame synchronous signal ? setting polarity of serial bit clock ? programming sampling point of received data ? selecting clock frequency dividing source of serial bit clock in the master mode (internal and external clock.) ? setting clock frequency dividing ratio in the master mode frequency of i2s_sclk = frequency of ahb clock (or external clock)/2 ckrt[5:0] frequency dividing ratio is settable within 0 ? 126 in multiple of 2 (when the ratio is 0, frequency dividing source is by-passed) ? data transfer to system memory by dma, interrupt, and polling note 1: data is not sent or r eceived to invalid channel
17-2 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) 17.3. block diagram figure 17-1 shows block diagram of i2s. as shown below, MB86R01 has 3 channels of i2s module. i2s0 module i2s_sck0 i2s_ws0 i2s_sdo0 ahb bus MB86R01 hdmac i2s_sdi0 i2s1 module i2s_sck1 i2s_ws1 i2s_sdo1 i2s_sdi1 i2s2 module i2s_sck2 i2s_ws2 i2s_sdo2 i2s_sdi2 figure 17-1 block diagram of i2s
17-3 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) 17.4. related pin i2s interface uses following pins which are common with other functions. to use this pin, its function should be set to be selected on i2s side to external pin, mpx_mode_1[1:0] or pin mpx select register on ccnt module. ? i2s ch0: set to mpx_mode_1[1:0] pin = "hl" ? i2s ch1: set to mpx_mode_2[2:0] = "010"/"011"/"100", or mpx_mode_4[1:0] = "01" of multiplex mode setting register ? i2s ch2: set to mpx_mode_2[2:0] = "000"/"010"/"100" of multiplex mode setting register for the case of "100" settin g, only the pin with input function among i2s ch2 related pins become valid table 17-1 i2s related pin pin direction qty. description i2s_eclk0 i2s_eclk1 i2s_eclk2 i 3 external clock input i2s_sck0 i2s_sck1 i2s_sck2 io 3 bit clock input/output signal in the master mode: clock output in the slave mode: clock input i2s_ws0 i2s_ws1 i2s_ws2 io 3 input/output signals of frame synchronization polarity is settable in the register in the master mode: frame synch. signal output in the slave mode: frame synch. signal input i2s_sdi0 i2s_sdi1 i2s_sdi2 i 3 serial reception data input signal i2s_sdo0 i2s_sdo1 i2s_sdo2 o 3 serial transmissi on data output signal 17.5. supply clock ahb clock is supplied to i2s interface unit. refer to "5. clock reset generator (crg)" for frequency setting and control specification of the clock.
17-4 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) 17.6. register this section describes i2s register. 17.6.1. register list register relating to i2s control is shown below. table 17-2 i2s register list module address register function ffee_0000 i2s0rxfdat reception fifo data register ffee_0004 i2s0txfdat transmission fifo data register ffee_0008 i2s0cntreg control register ffee_000c i2s0mcr0reg channel control register 0 ffee_0010 i2s0mcr1reg channel control register 1 ffee_0014 i2s0mcr2reg channel control register 2 ffee_0018 i2s0oprreg operation control register ffee_001c i2s0srst software reset register ffee_0020 i2s0intcnt interrupt control register ffee_0024 i2s0status status register i2s ch0 ffee_0028 i2s0dmaact dma start-up register ffef_0000 i2s1rxfdat reception fifo data register ffef_0004 i2s1txfdat transmi ssion fifo data register ffef_0008 i2s1cntreg control register ffef_000c i2s1mcr0reg channel control register 0 ffef_0010 i2s1mcr1reg channel control register 1 ffef_0014 i2s1mcr2reg channel control register 2 ffef_0018 i2s1oprreg operation control register ffef_001c i2s1srst software reset register ffef_0020 i2s1intcnt interrupt control register ffef_0024 i2s1status status register i2s ch1 ffef_0028 i2s1dmaact dma start-up register fff0_0000 i2s2rxfdat reception fifo data register fff0_0004 i2s2txfdat transmission fifo data register fff0_0008 i2s2cntreg control register fff0_000c i2s2mcr0reg channel control register 0 fff0_0010 i2s2mcr1reg channel control register 1 fff0_0014 i2s2mcr2reg channel control register 2 fff0_0018 i2s2oprreg operation control register fff0_001c i2s2srst software reset register fff0_0020 i2s2intcnt interrupt control register fff0_0024 i2s2status status register i2s ch2 fff0_0028 i2s2dmaact dma start-up register all registers of i2s correspond to access in byte (8 bit), half word (16 b it), and word (32 bit.)
17-5 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) description format of register following format is used for descri ption of register?s each bit in " 17.6.2 i2sxrxfdat register" to " 17.6.12 i2sxdmaact register". address base address + offset bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r/w initial value bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r/w initial value meaning of item and sign address address (base address + offset address) of the register bit bit number of the register name bit field name of the register r/w attribution of read/write of each bit field ? r0:read value is always "0" ? r1: read value is always "1" ? w0: write value is always "0", and write access of "1" is ignored ? w1: write value is always "1", and write access of "0" is ignored ? r: read ? w: write initial value each bit field?s value after reset ? 0: value is "0" ? 1: value is "1" ? x: value is undefined
17-6 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) 17.6.2. i2sxrxfdat register this register is reception fifo regi ster that is able to maintain up to 66 words (simultaneous transmission and reception mode) or 132 words (reception only mode.) address ch0 ffee_0000 (h) ch1 ffef_0000 (h) ch2 fff0_0000 (h) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name rxdata r/w r r r r r r r r r r r r r r r r initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rxdata r/w r r r r r r r r r r r r r r r r initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-0 rxdata[31:0] the word received from serial bus is written to reception fifo. when frame is 1 sub frame construction a nd word length set to s0wdln of mcr0reg register is 32 bit or less (16 bit when rhll of cntreg register is "1"), it is written to reception fifo after higher order bit is extended. when frame is 2 sub frame construction a nd word length set to s0wdln of mcr0reg register is 32 bit or less (16 bit when rhll of cntreg register is "1"), reception data of sub frame 0 is written to reception fifo after higher order bit is extended. for the case that word length set to s1wdl of mcr0reg register is 32 bit or less, reception data of sub frame 1 is written to reception fifo after higher order bit is extended. when bext of cntreg register is "1", it is extended with msb of reception word (sign extension). for the case that the value is "0", it is enhanced by "0". top of the data (first in) of reception fifo is able to be read by read access, and then the next reception fifo data is automatically updated. it is able to be accessed regardless of shift register's operation status. when rxnum of status register is "0", invalid data is able to be read. writing to rxdata is ignored.
17-7 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) 17.6.3. i2sxtxfdat register this register is transmission fifo register that is able to maintain up to 66 words (simultaneous transmission and reception mode mode) or 132 words (transmission only mode.) address ch0 ffee_0004 (h) ch1 ffef_0004 (h) ch2 fff0_0004 (h) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name txdata r/w w w ww w wwwwwwww w w w initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name txdata r/w w w ww w wwwwwwww w w w initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-0 txdata[31:0] word to be transmitted is able to be written as long as transmission fifo is not full. write access is able to be performed rega rdless of shift register's operation status. the word written to full transmission fifo is actually not written. although writing data is accessed in word, half-word, and byte access, actual number of bit to be transmitted is determined by s0wdl and s1wdl (when frame is 2 sub frame) of mcr0reg register. the data read from txdata is invalid one (the data after right justified last written data.)
17-8 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) 17.6.4. i2sxcntreg register address ch0 ffee_0008 (h) ch1 ffef_0008 (h) ch2 fff0_0008 (h) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ckrt ovhd r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ? mskb msmd sbfn rhll eckm bext frun mlsb txdis rxdis smpl cpol fsph fsln fspl r/w r r/w r/w r/w r/w r/w r/w r/ w r/w r/w r/w r/w r/w r/w r/w r/w initial 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 bit field no. name description 31-26 ckrt[5:0] this sets output clock frequ ency dividing ratio at master operation. ahb clock is divided at eckm = 0, and external clock is divided at eckm = 1. only even number of the ratio is supported and output clock's duty becomes 50%. ckrt [5:0] 2 becomes number of ahb clock or external clock cycle included in 1 cycle (i2s_sckx.) setting examples are shown below. external clock mode and external clock are 24.576mhz: ckrt dividing ratio i2s_sckx 0x00 by pass 24.576mhz (external clock is output as it is) 0x01 1/2 12.288mhz 0x02 1/4 6.144mhz 0x03 1/6 4.096mhz 0x04 1/8 3.072mhz 0x05 1/10 2.458mhz : : : internal clock mode and ahb clock are 80mhz: ckrt dividing ratio i2s_sckx : : : 0x04 1/8 10mhz 0x05 1/10 8mhz 0x06 1/12 6.67mhz 0x07 1/14 5,71mhz 0x08 1/16 5mhz 0x09 1/18 4.44mhz : : : 25-16 ovhd[9:0] frame rate is ab le to be adjusted by in serting ovhd bit following to valid data of the frame. ovhd section of the transmission frame become s in high impedance. up to 0 ? 1023 ovhd bit is able to be inserted, and is inserted at the end of the frame. the value set to ovhd becomes the number of insertion bit. the following expressions are formed for ovhd and frame synchronous signal cycle (2nd.) 1 sub frame construction: ovhd = frame synchronous signal cycle/i2s_sckx cycle ? (s0chl + 1) (s0chn + 1) 2 sub frame construction: ovhd = frame synchronous signal cycle/i2s_sckx cycle ? (s0chl + 1) (s0chn + 1) ? (s1chl + 1) (s1chn + 1) 15 (reserved) reserved bits. the write access is ignored. the read value of these bits is always "0".
17-9 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) bit field no. name description 14 mskb serial output data of i nvalid transmission frame is set. for master operation (msmd = 1), free-running mode (frun = 0), and txenb = 1: when transmission fifo is empty at frame synchr onous signal output, mskb is output to all valid channels of its transmission frame. for slave operation (msmd = 0) and txenb = 1: when transmission fifo is empty at frame synchronous signal re ception, mskb is output to all valid channels of its transmission frame. for the case that transmission word length is shor ter than the channel length, mskb is driven to the rest of bit in transmission ch annel (channel length -word length.) 13 msmd master and slave modes are set. 0 slave operation 1 master operation 12 sbfn sub frame construction (number of sub frame) of the frame is specified. 0 1 sub frame construction (only sub frame 0) 1 2 sub frame construction (sub frame 0 and sub frame 1) frame starts from the 0th sub frame 11 rhll whether word structure of fifo is 1 or 2 words is set. it is considered to be used at prot ocol, such as i2s and msb-justified. 0 32 bit fifo word is handled as 1 word 1 32 bit fifo word is handled as 2 words at serial bus with dividing 16 bit each to low order and high order. they are transferred by serial bus in order of low order, high order, low order, and high order. at reception, 2 consecutive words from seri al bus is handled as low order and high order, and they are put in 1 word (32 bit) to write to reception fifo. 10 eckm clock frequency dividing is selected in the master mode. 0 internal clock (ahb clock) is divided and output 1 external clock (2s_eclkx pin input) is divided and output 9 bext when reception word length is shorter than th e word length of fifo (32 bit when rhll is "0", and 16 bit when rhll is "1"), extension mode of upper bit (word length of fifo - reception word length) should be set. 0 extended by 0 1 extended by sign bit (for msb of word is "1", extended by "1" and its "0" is extended by "0") 8 frun output mode of frame synchronous signal is set. 0 burst mode when start bit of oprreg register is "1", frame synchronous signal is output according to txenb, rxenb, and tran smission/reception fifo conditions 1 free-running mode when start bit of oprreg register is "1", frame synchronous signal proceeds free-running with the set frame rate when start bit is "0", frame synchronous signal is not output.
17-10 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) bit field no. name description 7 mlsb word bit's shift order is set. 0 shift starts from msb of the word 1 shift starts from lsb of the word 6 txdis transmitting function is enabled or disabled. 0 transmitting function is enabled 1 transmitting function is disabled 5 rxdis receiving function is enabled or disabled. 0 receiving function is enabled 1 receiving function is disabled 4 smpl sampling point of the data is specified. 0 sampling at the center of reception data 1 sampling at the end of reception data 3 cpol i2s_sckx polarity which drives/s amples serial data is specified. 0 data is driven at rising edge of i2s_sckx, and sampled at falling edge 1 data is driven at falling edge of i2s_sckx, and sampled at rising edge 2 fsph phase is specified to i2s_wsx frame data. 0 i2s_wsx becomes valid 1 clock befo re the first bit of frame data 1 i2s_wsx becomes valid at the same time as the first bit of frame data 1 fsln pulse width of i2s_wsx is specified. 0 pulse width is 1 cycle/i2s_sckx long (1 bit) 1 pulse width is 1 channel long (1 channel) setting "1" is prohibited when frame length is 1 channel long. 0 fspl polarity of i2s_wsx pin is set. 0 frame synchronous signal becomes valid with i2s_wsx is "1" the value is "0" at idle 1 frame synchronous signal becomes valid with i2s_wsx is "0" the value is "1" at idle note: do not overwrite cntreg register when start bit of oprreg register is "1".
17-11 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) 17.6.5. i2sxmcr0reg register address ch0 ffee_000c (h) ch1 ffef_000c (h) ch2 fff0_000c (h) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ? s1chn s1chl s1wdl r/w r r/w r/w r/w r/w r/w r/w r/ w r/w r/w r/w r/w r/w r/w r/w r/w initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ? s0chn s0chl s0wdl r/w r r/w r/w r/w r/w r/w r/w r/ w r/w r/w r/w r/w r/w r/w r/w r/w initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31 (reserved) reserved bits. the write access is ignored. the read value of these bits is always "0". 30-26 s1chn[4:0] number of channel of sub frame 1 is set. this is valid only when the fram e is 2 sub frame construction (sbf n of cntreg is "1"), and is invalid when the frame is 1 sub frame c onstruction (sbfn of cntreg is "0".) up to 32 channels are able to be specified, and s1chn needs to be set to "number of channel ? 1". example 1 s1chn = "00011": sub frame 1 becomes 4 channel construction example 2 s1chn = "11111": sub frame 1 becomes 32 channel construction s1wdl is valid only in 2 sub frame construction (sbfn of cntreg is "1") and is invalid in 1 sub frame construction (sbfn of cntreg is "0".) 25-21 s1chl[4:0] channel length of the channel construc ting sub frame 1 (bit length of channel) is set. 7 - 32 bit of channel length are available but 1 - 6 bit are prohibited. s1chn needs to be set to "number of channel ? 1". example 1 s1chl = "00110": channel length becomes 7 bit example 2 s1chl = "11111": channel length becomes 32 bit channel length is able to be set to 32 or less regardless of rhll value of cntreg register. s1wdl is valid only in 2 sub frame construction (sbfn of cntreg is "1") and is invalid in 1 sub frame construction (sbf n of cntreg is "0".) 20-16 s1wdl[4:0] word length of the channel constructin g sub frame 1 (bit length of channel) is set. 7 - 32 bit of word length are available but 1 - 6 bit are prohibited. s1wdl needs to be set to "word length ? 1". example 1 s1wdl = "00110": word length becomes 7 bit example 2 s1wdl = "11111": word length becomes 32 bit rhll of cntreg register is "1": set word length to 16 or less and channel length to shorter than the one set to s1chl rhll of cntreg register is "0": set word length to 32 or less and channel length to shorter than the one set to s1chl s1wdl is valid only in 2 sub frame construction (sbfn of cntreg is "1") and is invalid in 1 sub frame construction (sbf n of cntreg is "0".) 15 (reserved) reserved bits. the write access is ignored. the read value of these bits is always "0". 14-10 s0chn[4:0] number of channel of sub frame 0 is set up to 32 channels. s0chn needs to be set to "number of channel ? 1". example 1 s0chn = "00011": sub frame 0 becomes 4 channel construction example 2 s0chn = "11111": sub frame 0 becomes 32 channel construction
17-12 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) bit field no. name description 9-5 s0chl[4:0] channel length of the channel construc ting sub frame 0 (bit length of channel) is set. 4 - 32 bit of channel length are available but 1 - 6 bit are prohibited. s0chn needs to be set to "channel length ? 1". example 1 s0chl = "00110": channel length becomes 7 bit example 2 s0chl = "11111": channel length becomes 32 bit the channel length can be set to 32 or less re gardless of rhll value of cntreg register. 4-0 s0wdl[4:0] word length of the channel constructin g sub frame 0 (number of bit in channel) is set. 4 - 32 bit of word length are available but 1-6 bit are prohibited. s0wdl needs to be set to "word length ? 1". example 1 s0wdl = "00110": word length becomes 7 bit example 2 s0wdl = "11111": word length becomes 32 bit rhll of cntreg register is "1": set word length to 16 or less and channel length to shorter than the one set to s0chl rhll of cntreg register is "0": set word length to 32 or less and channel length to shorter than the one set to s0chl 17.6.6. i2sxmcr1reg register this register controls enable and disable functions to each channel of sub frame 0. address ch0 ffee_0010 (h) ch1 ffef_0010 (h) ch2 fff0_0010 (h) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name s0ch 31 s0ch 30 s0ch 29 s0ch 28 s0ch 27 s0ch 26 s0ch 25 s0ch 24 s0ch 23 s0ch 22 s0ch 21 s0ch 20 s0ch 19 s0ch 18 s0ch 17 s0ch 16 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name s0ch 15 s0ch 14 s0ch 13 s0ch 12 s0ch 11 s0ch 10 s0ch 09 s0ch 08 s0ch 07 s0ch 06 s0ch 05 s0ch 04 s0ch 03 s0ch 02 s0ch 01 s0ch 00 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-0 s0ch31-s0ch00 name (s0chxx) of each bit indica tes channel number xx of sub frame 0 (e.g. s0ch00 bit controls 0th channel of sub frame 0.) thus, s0ch31 bit controls 31st channel of sub frame 0. 0 the corresponding channel is disabled transmission/reception are not performed to the disabled channel 1 the corresponding channel is enabled transmission/reception are performed to the enabled channel
17-13 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) 17.6.7. i2sxmcr2reg register this register is to control enable and disable functions to each channel of sub frame 1. address ch0 ffee_0014 (h) ch1 ffef_0014 (h) ch2 fff0_0014 (h) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name s1ch 31 s1ch 30 s1ch 29 s1ch 28 s1ch 27 s1ch 26 s1ch 25 s1ch 24 s1ch 23 s1ch 22 s1ch 21 s1ch 20 s1ch 19 s1ch 18 s1ch 17 s1ch 16 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name s1ch 15 s1ch 14 s1ch 13 s1ch 12 s1ch 11 s1ch 10 s1ch 09 s1ch 08 s1ch 07 s1ch 06 s1ch 05 s1ch 04 s1ch 03 s1ch 02 s1ch 01 s1ch 00 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-0 s1ch31-s1ch00 name (s1chxx) of each bit indica tes channel number xx of sub frame 1 (e.g. s1ch00 bit controls 0th channel of sub frame 1.) thus, s1 ch31 bit controls 31st channel of sub frame 1. when frame is 1 sub frame construction (sbf n of cntreg is "0"), this is invalid. 0 the corresponding channel is disabled transmission/reception are not performed to the disabled channel 1 the corresponding channel is enabled transmission/reception are performed to the enabled channel
17-14 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) 17.6.8. i2sxoprreg register address ch0 ffee_0018 (h) ch1 ffef_0018 (h) ch2 fff0_0018 (h) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) rxenb (reserved) txenb r/w r r r r r r r r/w r r r r r r r r/w initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) start r/w r r r r r r r r r r r r r r r r/w initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-25 (reserved) reserved bits. the write access is ignored. the read value of these bits is always "0". 24 rxenb enable/disable functions of receiving operation is set. 0 receiving operation is disabled reception fifo becomes empty with writing "0" to this bit when rxenb is "0", the data received from serial reception bus is not written to reception fifo dma reception channel stops during dma transfer 1 receiving operation is enabled 23-17 (reserved) reserved bits. the write access is ignored. the read value of these bits is always "0". 16 txenb enable/disable functions of transmitting operation is set. 0 transmitting operation is disabled reception fifo becomes empty with writing "0" to this bit when txenb is "0", the data written to txfdat register from cpu or dma is not written to transmission fifo dma reception channel stops during dma transfer 1 transmitting operation is enabled 15-1 (reserved) reserved bits. the write access is ignored. the read value of these bits is always "0". 0 start i2s is enabled/disabled. 0 i2s is stop, and internal transmission/ reception fifo becomes empty by writing "0" to this bit 1 i2s is operable prohibit overwriting cntreg, mcr0reg, mcr1 reg, and mcr2reg registers when start is "1".
17-15 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) 17.6.9. i2sxsrst register this register is to control i2s software reset. address ch0 ffee_001c (h) ch1 ffef_001c (h) ch2 fff0_001c (h) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) srst r/w r r r r r r r r r r r r r r r r/w initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-1 (reserved) reserved bits. the write access is ignored. the read value of these bits is always "0". 0 srst software reset is performed by writing "1". status register and each internal state machine become initial state by software reset, and transmission/reception fi fo becomes empty. there is no influence in registers other th an status, intcnt, and dmaact registers. when read value is "0" after writing "1", it indica tes software reset is completed. "1" indicates software reset is in process.
17-16 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) 17.6.10. i2sxintcnt register address ch0 ffee_0020 (h) ch1 ffef_0020 (h) ch2 fff0_0020 (h) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ? txud1m tberm ferrm txud0m txovm txfdm txfim (reserved) rberm rxudm rxovm eopm rxfdm rxfim r/w r r/w r/w r/w r/w r/w r/w r/ w r r r/w r/w r/w r/w r/w r/w initial 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) tfth (reserved) rptmr rfth r/w r r r r r/w r/w r/w r/w r r r/w r/w r/w r/w r/w r/w initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31 (reserved) reserved bits. the write access is ignored. the read value of these bits is always "0". 30 txud1m this is transmission fifo underflow interrupt mask bit. it becomes "1" by software reset. 0 interrupt to cpu by txudr1 of status register is not masked 1 interrupt to cpu by txudr1 of status register is masked 29 tberm this is interrupt mask bit of bl ock size error of transmission channel. it becomes "1" by software reset. 0 interrupt to cpu by tberr of status register is not masked 1 interrupt to cpu by tberr of status register is masked 28 ferrm this is frame error interrupt mask bit. it becomes "1" by software reset. 0 interrupt to cpu by ferr of status register is not masked 1 interrupt to cpu by ferr of status register is masked. 27 txud0m this is transmission fifo underflow interrupt mask bit. it becomes "1" by software reset. 0 interrupt to cpu by txudr0 of status register is not masked. 1 interrupt to cpu by txudr0 of status register is masked. 26 txovm this is transmission fifo overflow interrupt mask bit. it becomes "1" by software reset. 0 interrupt to cpu by txovm of status register is not masked. 1 interrupt to cpu by txovm of status register is masked. 25 txfdm this is dma request mask register bit. it becomes "1" by software reset. 0 dma transfer is requested when reception data written to transmission fifo is threshold value or more 1 dma transfer is not requested even reception data written to transmission fifo is threshold value or more
17-17 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) bit field no. name description 24 txfim this is transmission fifo interrupt mask bit. it becomes "1" by software reset. 0 interrupt to cpu by txfi of status register is not masked 1 interrupt to cpu by txfi of status register is masked 23-22 (reserved) reserved bits. the write access is ignored. the read value of these bits is always "0". 21 rberm this is interrupt mask bit of reception channel block size error. it becomes "1" by software reset. 0 interrupt to cpu by rberr of status register is not masked 1 interrupt to cpu by rberr of status register is masked 20 rxudm this is reception underflow interrupt mask bit. it becomes "1" by software reset. 0 interrupt to cpu by rxudr of status register is not masked 1 interrupt to cpu by rxudr of status register is masked 19 rxovm this is interrupt mask bit of reception fifo overflow. it becomes "1" by software reset. 0 interrupt to cpu by rxovr of status register is not masked 1 interrupt to cpu by rxovr of status register is masked 18 eopm this is interrupt mask b it by eopi of status register. it becomes "1" by software reset. 0 interrupt to cpu by eopi of status register is not masked 1 interrupt to cpu by eopi of status register is masked 17 rxfdm this is reception dma request mask bit. it becomes "1" by software reset. 0 dma transfer is requested when reception data written to reception fifo is threshold value or more 1 dma transfer is not requested though recep tion data written to reception fifo is threshold value or more 16 rxfim this is reception fifo interrupt mask bit. it becomes "1" by software reset. 0 interrupt to cpu by rxfi of status register is not masked 1 interrupt to cpu by rxfi of status register is masked 15-12 (reserved) reserved bits. the write access is ignored. the read value of these bits is always "0". 11-8 tfth[3:0] threshold value of transmission fifo is set. empty space of transmission fifo is threshold valu e or more and txfim is "0": interrupt to cpu occurs empty space of transmission fifo is threshold value or more and txfdm is "0": dma is requested to dmac tfth is set according to the following expressions. tfth = transmission fifo threshold ? 1
17-18 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) bit field no. name description 7-6 (reserved) reserved bits. the write access is ignored. the read value of these bits is always "0". 5-4 rptmr[1:0] this is packet reception completion timer setting bit which sets time-out value of the internal reception completion timer. reception fifo is not empty and number of its data is smaller than threshold value: the timer always counts up reception fifo is empty or the data value is threshold value or more: the timer is cleared. when the timer becomes time-out, eopi bit of status register is set to "1". the timer becomes "00" by software reset. 00 0 (the timer is not in operation) 01 54000 ahb clock cycles 10 108000 ahb clock cycles 11 216000 ahb clock cycles 3-0 rfth[3:0] threshold value of reception fifo is set. number of reception word written to reception fifo is threshold value or more and rxfim is "0": interrupt to cpu occurs number of reception word written to reception fifo is threshold value or more and rxfdm is "0": dma is requested to dmac rfth is set according to the following expressions. rfth = reception fifo threshold ? 1
17-19 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) 17.6.11. i2sxstatus register address ch0 ffee_0024 (h) ch1 ffef_0024 (h) ch2 fff0_0024 (h) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name tberr rberr ferr txudr1 txudr0 txovr rxudr r xovr (reserved) eopi bsy txfi rxfi r/w r r r/w r/w r/w r/w r/w r/w r r r r r/w r r r initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name txnum rxnum r/w r r r r r r r r r r r r r r r r initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31 tberr in order to set block size of dma transmissi on channel to larger value than i2s transmission fifo threshold (tfth+1) to operate, this bit is set to "1" and i2s stops the transfer. when tberr is "1" and tberm of the intcnt register is "0", interrupt to cpu occurs. this bit becomes "0" by software and hardware reset. 30 rberr in order to set block size of dma receptio n channel to larger value than i2s reception fifo threshold (rfth+1) to operate, this bit is set to "1" and stop the channel. when rberr is "1" and rberm of the intcnt register is "0", interrupt to cpu occurs. this bit becomes "0" by software and hardware reset. 29 ferr occurrence of frame error is indicated. this bit is set to "1" in the following cases: ? frame synchronous signal is not able to be rece ived with the set frame rate in the free-running mode (frun = 0 of cntreg) and the slave mode (msmd = 0 of cntreg) ? the next frame synchronous signal is received during frame transmission/reception in the slave mode (msmd = 0 of cntreg), not free -running mode (frun = 1 of cntreg) when ferr is "1" and ferrm of intcnt register is "0", interrupt to cpu occurs. writing "1" from cpu clears the value to "0". this becomes "0" by software reset. 28 txudr1 when transmission fifo underflows at the top of frame, the value is set to "1". writing "1" from cpu clears the value to "0". this becomes "0" by software reset. 27 txudr0 when transmission fifo underflows during fra me transmission (from 2nd bit word to the last frame of the word), the value is set to "1". writing "1" from cpu clears the value to "0". this becomes "0" by software reset. 26 txovr when transmission fifo overflows, the value is set to "1" indicati ng transmission data is written in the condition that transmission fifo is full. the value "1" indicates 1 word or more of transmission data is deleted. when txovr is "1" and txovm of intcnt register is "0", interrupt to cpu occurs. writing "1" from cpu clears the value to "0". this becomes "0" by software reset. 25 rxudr when reception fifo underflows, the value is set to "1" indicating read access is carried out to reception fifo in the condition that reception fifo is empty. writing "1" from cpu clears the value to "0". this becomes "0" by software reset. 24 rxovr when reception fifo overflows, the value is se t to "1" indicating reception is carried out in the condition that reception fifo is full. the value "1" indicates 1 word or more of reception data is deleted. when rxovr is "1" and rxovm of intcnt regi ster is "0", interrupt to cpu occurs. writing "1" from cpu clears the value to "0". this becomes "0" by software reset. 23-20 (reserved) reserved bits. the write access is ignored. the read value of these bits is always "0".
17-20 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) bit field no. name description 19 eopi this is interrupt flag containing reception time r. the timer is enabled when following conditions are met at the same time: ? rxdis of cntreg register is set to "0" ? rxfdm of intcnt register is set to "0" ? msmd of cntreg register is set to "0" ? start bit of oprreg register is set to "1" and rxenb = "1" after the reset, operation starts with the 1st word reception. then the value is cleared every time word is received. when reception fifo is not empty at the time set to rptmr of intcnt register, the value is set to "1". when eopi is "1" and eopm of intcnt re gister is "0", interrupt to cpu occurs. the value is automatically cleared if reception fifo data is threshold or more, or it becomes empty. writing "1" from cpu clears the value to "0". this becomes "0" by software reset. 18 bsy serial transmission control part is busy state. this bit is not affected by software reset. 0 serial transmission control part is in idle 1 serial transmission control part is in busy 17 txfi when empty slot of transmission fifo is larger than the threshold set in tfth of intcnt register, this bit is set to "1". this bit is "1" and txfim bit of intcnt register is "0": interrupt to cpu occurs this bit is "1" and txfdm bit of intcnt register is "0": dma is requested when number of empty slot of reception fifo becomes smaller than the threshold by writing to txfdat register from cpu or dmac, this bit is cleared automatically to "0". the value is also become "0" when start bit of start register is "0" and txenb bit of oprreg register is "0". if software re set is performed at start bit = "1" and txenb bit = "1", the value becomes "0" during software reset then changes to "1" after the process. 16 rxfi when number of reception fifo data is larger than the threshold set in rftf of intcnt register, this bit is set to "1". this bit is "1" and rxfim bit of intcnt re gister is "0": interrupt to cpu occurs this bit is "1" and rxfdm bit of intcnt register is "0": dma is requested when number of data in reception fifo become s smaller than the threshold by reading rxfdat register from cpu or dmac, this bit is automatically cleared to "0". when start bit of start register is "0" or rxenb bit of oprreg register is "0", this bit becomes "0". this becomes "0" by software reset. 15-8 txnum[7:0] the number of data in transmission fifo is indicated. this bit is incremented by write access to txfdat register and decremented by serial word transfer. max. value of 66 can be displayed in the simultaneous transmission and reception mode, and value of 132 in the transmission only mode. this becomes "0" by software reset. 7-0 rxnum[7:0] the number of data in reception fifo is indicated. this bit is incremented by word reception from serial bus and decremented by read access to rxfdat register. max. values of 66 can be displayed in the simu ltaneous transmission and reception mode, and value of 132 in the reception mode. this becomes "0" by software reset.
17-21 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) 17.6.12. i2sxdmaact register address ch0 ffee_0028 (h) ch1 ffef_0028 (h) ch2 fff0_0028 (h) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) tdmact r/w r r r r r r r r r r r r r r r r/w initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) rdmact r/w r r r r r r r r r r r r r r r r/w initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-17 (reserved) reserved bits. the write access is ignored. the read value of these bits is always "0". 16 tdmact transmission channel of dmac (dma controller) is activated. after transfer channel starts, software shoul d write "1" to tdmact to teach i2s that the transfer channel is active. when tdmact is "0", transfer request of transmission channel block is not sent to dmac. i2s automatically clears tdmact every time dma packet transmission completes. writing "0" from cpu clears the value to "0". this becomes "0" by software reset. 0 transmission channel of dmac is stop th at txdreq is unable to be detected 1 transmission channel of dmac is activated that txdreq is able to be detected 15-1 (reserved) reserved bits. the write access is ignored. the read value of these bits is always "0". 0 rdmact the reception channel of dm ac (dma controller) is activated. after reception channel starts, software should write "1" to rdmact to teach i2s that the channel is active. when rdmact is "0", transfer request of reception channel block is not sent to dmac. i2s automatically clears rdmact every time dm a packet reception completes. writing "1" from cpu clears the value to "0". this becomes "0" by software reset. 0 reception channel of dmac is stop that rxdreq is unable to be detected 1 reception channel of dmac is active that rxdreq is able to be detected
17-22 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) 17.7. operation 17.7.1. outline this module is synchronous serial interface which enables full duplex and multiplexer channel. it is also able to correspond to vari ous frame formats by register setting. (refer to " 17.7.3 frame construction" for detail.) thi s module is also able to operate as master and slave. in the master mode, clock (i2s_sckx) and frame synchronous signal (i2s_wsx) are output to the external slave. in the slave mode, they are input from the external master. during the master mode, i2s_sckx clock can be output by dividing external clock (i2s_external clock x) or internal clock (it is selectable at register). frame synchronous signal can be generated by free-running or burst mode (generated only when there is transmission data.) this module equips transmission and reception fi fo, and its depth varies depending on mode: transmission only mode: 132word x 32bit transmission fifo reception only mode: 132wor d x 32bit reception fifo simultaneous transmission and reception mode: 66word x 32bit transmission fifo and 66word x 32bit reception fifo refer to " 17.7.3 frame construction" for more detail. internal tra nsfer between transmission and reception fifo and internal system memory is able to be performed by dma, interrupt, and polling.
17-23 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) 17.7.2. transfer start, stop, and malfunction transmission only mode transfer setting operation master mode (msmd = 1) slave mode (msmd = 0) start free-running mode (frun = 1): after start bit becomes "1" and txenb bit is "1", frame synchr onous signal starts to output when transmission fifo is not empty. from the 2nd tim e, it outputs frame synchronous signal with the frame rate determined by the register setting. if transfer fifo is empty, empty frame is output at the same time of frame synchronous signal output. serial data of the empty frame is able to be set to "0" or "1" by the register setting. burst mode (frun = 0): when start bit is "1" and txenb bit is "1", frame synchronous signal is output if transfer fifo is not empty. always confirm transmission fifo status at the end of 1 frame output or at idle to output the signal if transfer fifo is not empty. free-running mode (frun = 1): the frame rate determined by the register setting inputs frame synchronous signal. if transmission fifo is empty at inputting frame synchronous signal with start bit is "1" and txenb bit is "1", empty frame is output. serial data of the empty frame is able to be set to "0" or "1" by the register setting. burst mode (frun=0): when start bit is "1" and txenb bit is "1", 1 frame is output every time frame synchronous signal is input. when transmission fifo is empty at the time of frame synchronous signal input, empty frame is output. transmission only txdis = 0 rxdis = 1 stop at the time of stop, transmission fifo becomes empty with having no data transfer from internal memory to i2s transmission fifo. to maintain start bit to "1" txenb = "1": keep outputting frame synchronous signal in the free-running mode. when transmission fifo becomes empty, empty frame is output; however, do not output frame synchronous signal in the burst mode. output empty frame bit to serial data bus. txenb = "0": when "0" is written to txenb, transmission fifo becomes empty that the data in the fifo at writing "0" is not sent. although frame synchronous signal continues outputting in the free-running mode, serial bus becomes in high impedance state. in the burst mode, frame synchronous signal is not output and serial data bus becomes in high impedance state. to make start bit "0" write "0" to start bit, then transmission fifo becomes empty. stop clock supply to the serial control part regardless of txenb setting, and do not output clock to external part. frame synchronous signal output should also be stopped. serial data bus becomes in high impedance state. to maintain start bit to "1" txenb = "1": output empty frame data to serial bus. txenb = "0": write "0" to txenb, then transmission fifo becomes empty that the data in the fifo at writing "0" is not sent. data writing to transmission fifo and transmission frame detection are stop. serial data bus becomes in high impedance state. to make start bit "0" write "0" to start bit, then transmission fifo becomes empty. writing to transmission fifo and detection of transmission frame synchronous signal are stop regardless of txenb setting.
17-24 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) transfer setting operation master mode (msmd = 1) slave mode (msmd = 0) abnormality when reading to transmission fifo occurs with having it empty, empty frame is output. when writing to transmission fifo occurs with having it full, set txovr to "1". when reading to transmission fifo occurs with having it empty, empty frame is output. however do not set txudr to "1" for the 1st output frame after bit becomes start = "1" and txenb = "1". when writing to transmission fifo occurs with having it full, set txovr to "1". if it is not input with the frame rate defined frame synchronous signal in the free-running mode, set ferr bit of the status register to "1". if the next frame synchronous signal is input before completing 1 frame transmission in the burst mode, set ferr bit of the status register to "1" note: 1. txdis and rxdis are for setting to enable and disable transmission/reception of cntreg register. 2. start, txenb, and rxenb are opera tion control bits of oprreg register. 3. empty frame bit is determined by mskb of cntreg register.
17-25 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) reception only mode transfer setting operation master mode (msmd = 1) slave mode (msmd = 0) start free-running mode (frun = 1): frame synchronous signal starts to output after start bit becomes "1" and txenb bit is "1" when transmission fifo is not empty. from the 2nd time, output frame synchronous signal with the frame rate determined by the register setting. burst mode (frun = 0): when start bit is "1" and rxenb bit is "1", output frame synchronous signal to receive frame if reception fifo is not full. if the fifo is full, the signal does not output. free-running mode (frun = 1): when start bit is "1" and rxenb bit is "1", input frame synchronous signal with the frame rate determined by the register setting. frame should be received every time the signal is input. burst mode (frun = 0): when start bit is "1" and rxenb bit is "1", perform frame reception every time frame synchronous signal is input. the signal is input with less speed than the frame rate in the free-running mode. stop at the time of stop, frame is not imported from serial bus even though re ception fifo is empty in the condition that data transfer from i2s reception fifo to internal memory is not required. to maintain start bit to "1" write "0" to rxenb and empty reception fifo. although frame synchronous signal is kept outputting in the free-running mode, frame is not received. in the burst mode, frame is not received and the signal is not output. to make start bit "0" write "0" to start bit, then reception fifo becomes empty. clock supply to the serial control part stops regardless of rxenb setting, and i2s_sckx supply to the external part is stop as well. to maintain start bit to "1" reception fifo becomes empty by "0" writing to rxenb. ignore the input frame synchronous signal, and do not receive the frame. to make the start bit "0" write "0" to the start bit, then reception fifo becomes empty. ignore the input frame synchronous signal regardless of rxenb setting, and do not receive the frame. reception only txdis = 1 rxdis = 0 abnormality when writing to reception fifo occurs with having it full, set rxovr of the status register to "1". when read access to reception fifo occurs with having it empty, set rxudr of the status register to "1". when writing to reception fifo occurs with having it full, set rxovr of the status register to "1". when read access to reception fifo occurs with having it empty, set rxudr of the status register to "1". free-running mode: if frame synchronous signal is not input with the frame rate defined by the register setting, set ferr bit of the status register to "1". burst mode: if the next frame synchronous signal is input during 1 frame reception, set ferr bit of the status register to "1". note: 1. txdis and rxdis are for setting to enable and disable transmission/reception of cntreg register. 2. start, txenb, and rxenb are opera tion control bits of oprreg register.
17-26 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) simultaneous transmission and reception mode transfer setting operation master mode (msmd = 1) slave mode (msmd = 0) simultaneous transfer txdis = 0 rxdis = 0 start free-running mode (frun = 1): status of start = 1, txenb = 1, and rxenb = 1: the same operation as transmission only mode. status of start = 1, txenb = 0, and rxenb = 1: the same operation as reception only mode. status of start = 1, txenb = 1, and rxenb = 1: frame synchronous signal is output from the state that transmission fifo is not empty and reception fifo is not full. then output frame synchronous signal with the frame rate defined by the register setting; at the same time, output empty frame if reception fifo is empty. empty frame's serial data is able to be set to "0" or "1" at the register setting. every time frame sy nchronous signal is output, receive frame. burst mode (frun = 0): status of start = 1, txenb = 1, and rxenb = 0: the same operation as transmission only mode. status of start = 1, txenb = 0, and rxenb = 1: the same operation as reception only mode. status of start = 1, txenb = 1, and rxenb = 1: frame synchronous signal is output from the state that transmission fifo is not empty and reception fifo is not full. after completion of 1 frame output or at idle state, always confirm transmission/reception fifo status. if transmission fifo is not empty and reception fifo is not full, output frame synchronous signal to perform frame transmission/reception. free-running mode (frun = 1): status of start = 1, txenb = 1, and rxenb = 0: the same operation as transmission only mode. status of start = 1, txenb = 0, and rxenb = 1: the same operation as reception only mode. status of start = 1, txenb = 1, and rxenb = 1: frame synchronous signal is input with the frame rate defined by the register setting; at the same time, output empty frame if transmission fifo is empty. its serial data is able to be set to "0" or "1" at the register setting. every time frame synchronous signal is input, receive frame. burst mode (frun = 0): every time frame synchr onous signal is input with start bit is "1", transmission and reception for 1 frame is performed. when the signal is input, output empty frame if transmission fifo is empty.
17-27 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) transfer setting operation master mode (msmd = 1) slave mode (msmd = 0) stop stop operation has following states: transmission stop: transmission fifo becomes empty without sending data from internal memory to i2s transmission fifo. reception stop: data does not need to be transferred from i2s reception fifo to internal memory. to maintain start bit to "1" keep outputting frame synchronous signal in the free-running mode. in the burst mode, do not output the signal when transmission fifo becomes empty. transmission stop: txenb = 1: keep outputting empty frame bit when transmission fifo becomes empty. txenb = 0: transmission fifo becomes empty and transmission serial data bus becomes in high impedance. do not send the data in transmission fifo at writing "0" to txenb. writing to transmission fifo stops. reception stop: write "0" to rxenb, then reception fifo becomes empty and frame reception operation stops. to make start bit "0" write "0" to start bit, then transmission/reception fifo becomes empty. the clock supply to the internal serial control part stops regardless of txenb and rxenb statuses as well as i2s_sckx output to the external part and frame synchronous signal output. to maintain start bit to "1" transmission stop: keep outputting empty frame bit after transmission fifo becomes empty in order to maintain this bit to txenb = 1. when the value is changed to "0", transmission fifo becomes empty and transmission serial data bus becomes in high impedance. do not send the data in transmission fifo at writing "0" to txenb. stop writing to transmission fifo. reception stop: write "0" to rxenb, then reception fifo becomes empty and frame reception operation stops. to make start bit "0" write "0" to start bit, then transmission/reception fifo becomes empty. stop transmission/ reception regardless of txenb and rxenb statuses. abnormality when reading to transmission fifo occurs with having it empty, ou tput empty frame bit. when writing to transmission fifo occurs with having it full, set txovr to "1". when read access to reception fifo occurs with having it empty, set rxudr of the status register to "1". when writing to reception fifo occurs with having it full, set rxovr of the status register to "1". when reading to transmission fifo occurs with having it empty, ou tput empty frame bit. when writing to transmission fifo occurs with having it full, set txovr to "1". when read access to reception fifo occurs with having it empty, set rxudr of the status register to "1". when writing to reception fifo occurs with having it full, set rxovr of the status register to "1". if it is not input with the frame rate defined frame synchronous signal in the free-running mode, set ferr bit of the status register to "1". if the next frame synchronous signal is input before completing 1 frame transmission in the burst mode, set ferr bit of the status register to "1". note: 1. txdis and rxdis are for setting to enable and disable transmission/reception of cntreg register. 2. start, txenb, and rxenb are operatio n control bits of oprreg register. 3. empty frame bit is determined by mskb of cntreg register.
17-28 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) 17.7.3. frame construction this module supports frame format of multiplexer channel construction. frame is able to be set to 1 or 2 sub frames; moreover, number of each frame?s channel and word length are able to be set individually. 17.7.3.1. 1 sub frame construction figure 17-2 1 sub frame composite frame description 1. when sbfn bit of cntreg register is "0", frame becomes 1 sub frame composite. 2. number of channel of 1 sub frame is determined by s0chn of mc0reg register. up to 32 channels are settable. 3. each channel bit length (word length) is determined by s0wdl of mc0reg register. 4. sub frame channel starts from 0th, and each channel is settable to vali d/invalid with the corresponding bit of mc1reg register. transmission/reception of data is not performed to invalid channel. 5 dummy bit can be inserted behind sub frame by setting ovhd of cntreg register. 0-1023 bit are insertable. 6. polarity of i2s_wsx is set with fspl bit of cntreg register. 7. pulse width of i2s_wsx can be set to 1 bit or 1 word length by setting fsln bit of cntreg register. 8. timing from the edge i2s_wsx becomes valid to the first bit of frame is settable to "0" or "1" bit. 9. in this construction, setting of s1chn of mc0reg register, s1wdl register and mc2reg register are ignored.
17-29 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) 17.7.3.2. 2 sub frame construction over-head (0-1023bits) 0-1 bit 1 bit i2s_sckx i2s_wsx(fsln=0) i2s_wsx(fsln=1) i2s_sdix/sdox one frame with two sub frames sub frame#0(1-32 channels) sub frame#1(1-32 channels) channel-0(7-32 bits) of sub frame#0 channel-n(7-32 bits) of sub frame#0 channel-0(7-32 bits) of sub frame#1 channel-n(7-32 bits) of sub frame#1 channel(msb justified) don t care data s0wdl s0chl channel(msb justified) don t care data s1wdl s1chl figure 17-3 2 sub frame composite frame description 1. when sbfn bit of cntreg register is "1", frame becomes 2 sub frame composite that first sub frame is 0 and the next one is 1. 2. set number of channel of sub frame 0 to s0chn of mc0reg register, and set num ber of sub frame 1 channel to s1chn of the register. those numbers of channel ar e individual that they do not need to have the same channel. up to 32 channels are settable. 3. channel bit length (word length) of sub frame 0 is determined by s0wdl of mc0reg register. for sub frame 1, they are determined by s1wdl of mc0reg re gister. since channel bit length of the sub frame is individual, those channels (word le ngth) do not need to be the same. 4. sub frame channel starts from 0th. each channel of sub frame 0 is settable to valid/invalid with the corresponding bit of mc1reg register, and corresponding bit of mc2reg regist er for sub frame 1. transmission/reception of data is not performed to invalid channel. 5 dummy bit can be inserted behind s ub frame 1 by setting ovhd of cntreg. 0-1023 bit are insertable. 6. polarity of i2s_wsx is set to fspl bit of cntreg register. 7. pulse width of i2s_wsx can be set to 1 bit or 1 ch annel length by setting fsln bit of cntreg register. channel length setting of 1 channel is determined by the channel length of sub frame 0. 8. timing from the edge i2s_wsx becomes valid to the fi rst bit of frame is settable to "0" or "1" bit.
17-30 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) 17.7.3.3. bit alignment (1) transmission word alignment figure 17-4 transmission word alignment chart when transmission is performed with serial bus, word is sent from m bit when cntreg register's mlsb is "0" and from l bit when the value is "1". when channel length (set to s0chl and s1chl) is longer than the word length (set to s0wdl and s1wdl), remaining bit in the channel becomes cntreg[mskb]. if channel length is sh orter than the word's, setting is prohibited. note: ab0, ab1, ab2, ab3, ah0, ah1, and aw on the a bove chart indicate byte 0, byte 1, byte 2, byte 3, half word 0, half word 1, and word at write acces sing to txfdat on ahb bus. each fb0, fb1, fb2, fb3, fh0, fh1, and fw indicate ab0, ab1, ab2, ab3, ah0, ah1, and aw are written to transmission fifo after they are right justified. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ab0 msb lsb ab1 msb lsb ab2 msb lsb ab3 msb lsb ah0 msb lsb ah1 msb lsb aw msb lsb 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 fb0 msb lsb fb1 msb lsb fb2 msb lsb fb3 msb lsb fh0 msb lsb fh1 msb lsb fw msb lsb s0wdl and s1wdl counts to the left from this bit when s0wdl and s1wdl are 3, ml s0wdl and s1wdl are 7, ? ml image of cpu written to txfdat register image of txfdat written to fifo transmission word transmission word the data written to txfdat re g ister from cpu or dma is written to transmission fifo after ri g ht ad j usted.
17-31 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) (2) reception word alignment figure 17-5 reception word alignment chart this chart shows word alignment example of when word length is 8. the word received from serial bus is always written to reception fifo after right-justified. therefore, read access should be performed from ahb bus to rxfdat in orde r to read as follows: word length ? 8 or less: byte 0 ? 9 ? 16: half word 0 ? 17 ? 32: all words. msb first lsb first serial data input pin's shifting direction b0 b1 b2 b3 b4 b5 b6 b7 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 01 mlsb bit extension and right justification bext = 1 1111111111111111111111111 lsb bext = 1 0000000000000000000000000 lsb bext = 0 0000000000000000000000001 lsb bext = 0 0000000000000000000000000 lsb write to reception fifo 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rxfdat
17-32 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) 17.7.4. fifo structure and description simultaneous transmission and reception mode (txdis = 0 and rxdis = 0) switch fifo wr from receive pin to rxfdat register rw from txfdat register to transmit pin txdis=0, rxdis=0 66word x 32bit 66word x 32bit figure 17-6 simultaneous transmi ssion and reception mode data flow with setting txdis = 0 and rxdi s = 0 of cntreg register, the mode becomes simultaneous transmission and reception mode which operates in 66word x 32bit transmission fifo and reception fifo.
17-33 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) transmission only mode (txdis = 0 and rxdis = 1) switch fifo wr rw to rxfdat register from txfdat register from receive pin to transmit pin txdis=0, rxdis=1 66word x 32bit 66word x 32bit figure 17-7 transmission only mode data flow with setting txdis = 0 and rxdis = 1 of cntreg register, the mode becomes transmission only mode which operates in 132word x 32bit transmis sion fifo, and reception is not performed.
17-34 MB86R01 lsi product specifications fujitsu semiconductor confidential serial audio interface (i2s) reception only mode (txdis = 1 and rxdis = 0) switch fifo wr rw txdis = 1 and rxdis = 0 to rxfdat register from txfdat register from reception pin to transmission pin 66word x 32bit 66word x 32bit figure 17-8 reception only mode data flow with setting txdis = 1 and rxdis = 0 of cntreg register, the mode becomes reception only mode which operates in 132word x 32bit reception fifo, and transmission is not performed.
18-1 MB86R01 lsi product specifications fujitsu semiconductor confidential uart interface 18. uart interface this chapter describes function and operation of uart. 18.1. outline uart is asynchronous transmission/ reception serial interface which is controllable by the program. this lsi equips 6 channels of uart. 18.2. feature uart has following features: ? programmable baud rate (baud rate is sel ectable arbitrarily based on apb clock) ? 16 byte transmission fifo and 16 byte reception fifo 18.3. block diagram figure 18-1 shows block diagram of uart. irc0/1 dmac baud rate generator register transmitter fifo shift modem i/f cpu i/f receiver fifo shift in tr xtxrdy xrxrd y uart_sout0 uart_xrts 0 uart_sin0 uart_xcts0 apb bus uart ch5 uart ch0 uart_sout5 uart_sin5 MB86R01 uart ch1 uart_sout1 uart_sin1 figure 18-1 block diagram of uart
18-2 MB86R01 lsi product specifications fujitsu semiconductor confidential uart interface 18.4. related pin uart uses the following pins. table 18-1 uart related pin pin direction qty. description uart_sin0 uart_sin1 uart_sin2 uart_sin3 uart_sin4 uart_sin5 in 6 input pin of serial data. the umber at the end of pin shows channel number of uart. uart_sout0 uart_sout1 uart_sout2 uart_sout3 uart_sout4 uart_sout5 out 6 output pin of serial data. the number at the end of pin shows channel number of uart. uart_xcts0 in 1 input pin of modem control signal, clear to send. only channel 0 of uart has this pin. uart_xrts0 out 1 output pin of mode m control signal, request to send only channel 0 of uart has this pin. 18.5. supply clock apb clock is supplied to uart. refer to "5. cloc k reset generator (crg)" for frequency setting and control specification of the clock.
18-3 MB86R01 lsi product specifications fujitsu semiconductor confidential uart interface 18.6. register this section describes uart interface module's register. 18.6.1. register list the lsi has 6 channels (3 dedicated channels and 3 ch annels of pin multiplex function) of uart interface unit, and each module has the register shown in table 18-2. t able 18-2 uart register list channel address register description urt0rfr reception fifo register (read only) that is valid in dlab = 0 urt0tfr transmission fifo register (wri te only) that is valid in dlab = 0 fffe1000h urt0dll divider latch (low order byte) register that is valid in dlab = 1 urt0ier interrupt enable that is valid in dlab = 0. fffe1004h urt0dlm divider latch (high order byte) register that is valid in dlab = 1 urt0iir interrupt id register (read only) fffe1008h urt0fcr fifo control (write only) fffe100ch urt0lcr line control register fffe1010h urt0mcr modem control register fffe1014h urt0lsr line status register (read only) uart ch0 fffe1018h urt0msr modem status register (read only) urt1rfr reception fifo register (read only) that is valid in dlab = 0 urt1tfr transmission fifo register (wri te only) that is valid in dlab = 0 fffe2000h urt1dll divider latch register (low or der byte) that is valid in dlab = 1 urt1ier interrupt enable that is valid in dlab = 0. fffe2004h urt1dlm divider latch (high order byte) register that is valid in dlab = 1 urt1iir interrupt id register (read only) fffe2008h urt1fcr fifo control (write only) fffe200ch urt1lcr line control register fffe2010h urt1mcr modem control register fffe2014h urt1lsr line status register (read only) uart ch1 fffe2018h urt1msr modem status register (read only) uart ch2 urt2rfr reception fifo register (read only) that is valid in dlab = 0 urt2tfr transmission fifo register (wri te only) that is valid in dlab = 0 fff50000h urt2dll divider latch (low order byte) register that is valid in dlab = 1 urt2ier interrupt enable that is valid in dlab = 0. fff50004h urt2dlm divider latch (high order byte) register that is valid in dlab = 1 urt2iir interrupt id register (read only) fff50008h urt2fcr fifo control (write only) fff5000ch urt2lcr line control register fff50010h urt2mcr modem control register fff50014h urt2lsr line status register (read only) fff50018h urt2msr modem status register (read only) uart ch3 fff51000h urt3rfr reception fifo register (read only) that is valid in dlab = 0 urt3tfr transmission fifo register (w rite only) that is valid in dlab = 0 urt3dll divider latch (low order byte ) register that is valid in dlab = 1
18-4 MB86R01 lsi product specifications fujitsu semiconductor confidential uart interface channel address register description uart ch3 urt3ier interrupt enable that is valid in dlab = 0. fff51004h urt3dlm divider latch (high order byte) register that is valid in dlab = 1 urt3iir interrupt id register (read only) fff51008h urt3fcr fifo control (write only) fff5100ch urt3lcr line control register fff51010h urt3mcr modem control register fff51014h urt3lsr line status register (read only) fff51018h urt3msr modem status register (read only) urt4rfr reception fifo register (read only) that is valid in dlab = 0 urt4tfr transmission fifo register (wri te only) that is valid in dlab = 0 fff43000h urt4dll divider latch (low order byte) register that is valid in dlab = 1 urt4ier interrupt enable that is valid in dlab = 0. fff43004h urt4dlm divider latch (high order byte) register that is valid in dlab = 1 urt4iir interrupt id register (read only) fff43008h urt4fcr fifo control (write only) fff4300ch urt4lcr line control register fff43010h urt4mcr modem control register fff43014h urt4lsr line status register (read only) uart ch4 fff43018h urt4msr modem status register (read only) urt5rfr reception fifo register (read only) that is valid in dlab = 0 urt5tfr transmission fifo register (wri te only) that is valid in dlab = 0 fff44000h urt5dll divider latch (low order byte) register that is valid in dlab = 1 urt5ier interrupt enable that is valid in dlab = 0. fff44004h urt5dlm divider latch (high order byte) register that is valid in dlab = 1 urt5iir interrupt id register (read only) fff44008h urt5fcr fifo control (write only) fff4400ch urt5lcr line control register fff44010h urt5mcr modem control register fff44014h urt5lsr line status register (read only) uart ch5 fff44018h urt5msr modem status register (read only) dlab: bit7 of line control register (lcr)
18-5 MB86R01 lsi product specifications fujitsu semiconductor confidential uart interface note: although uart's register length is 8 bit, each register except rfr, tfr, and dll should be accessed in 32 bit. per, tfr, and dll are able to be accessed in bot h 32 bit and 8bit lengths; however, note that 8 bit length access is different since register address is endian dependent. description format of register following format is used for descri ption of register?s each bit in " 18.6.2 reception fifo register (ur txrfr)" to " 18.6.11 divider latch register (urtxdll&urtxdlm)". address base address + offset bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r/w initial value bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r/w initial value meaning of item and sign address address (base address + offset address) of the register bit bit number of the register name bit field name of the register r/w attribution of read/write of each bit field ? r0:read value is always "0" ? r1: read value is always "1" ? w0: write value is always "0", and write access of "1" is ignored ? w1: write value is always "1", and write access of "0" is ignored ? r: read ? w: write initial value each bit field?s value after reset ? 0: value is "0" ? 1: value is "1" ? x: value is undefined
18-6 MB86R01 lsi product specifications fujitsu semiconductor confidential uart interface 18.6.2. reception fifo register (urtxrfr) address ch0 fffe_1000 + 00h ch1 fffe_2000 + 00h ch2 fff5_0000 + 00h ch3 fff5_1000 + 00h ch4 fff4_3000 + 00h ch5 fff4_4000 + 00h (reading is enabled only at dlab = 0) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) rfr[7:0] r/w r r r r r r r r r r r r r r r r initial value x x x x x x x x 0 0 0 0 0 0 0 0 bit no. bit name function 31:8 unused reserved bit 7-0 rfr[7:0] this is fifo register that is able to maintain up to 16 byte. reception data is acquired and maintained at the end of reception sequence. this register is able to proceed system reset as well as reset by fcr bit 1 (rxf rst.) rfr register becomes valid at dlab = 0, and dll register is assigned at dlab = 1. rfr register becomes valid only at reading register, a nd data is written to tfr register (at dlab = 0) or dll register (at dlab = 1) according to the setting value of dlab when writing. 18.6.3. transmission fifo register (urtxtfr) address ch0 fffe_1000 + 00h ch1 fffe_2000 + 00h ch2 fff5_0000 + 00h ch3 fff5_1000 + 00h ch4 fff4_3000 + 00h ch5 fff4_4000 + 00h (writing is enabled only at dlab = 0) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w w w w w w w w w w w w w w w w w initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) tfr[7:0] r/w w w w w w w w w w w w w w w w w initial value x x x x x x x x 0 0 0 0 0 0 0 0 bit no. bit name function 31:8 unused reserved bit (input "0" at writing) 7:0 tfr[7:0] this is fifo register that is able to maintain up to 16 byte. data is maintained in this register until being transmitted to the transmission shift register. this register is able to proceed system reset as well as reset by fcr bit 2 (rxf rst.) this register is write only; however, reading operation reads rfr register (at dlab = 0) or dll register (at dlab = 1) according to setting value of dlab.
18-7 MB86R01 lsi product specifications fujitsu semiconductor confidential uart interface 18.6.4. interrupt enable register (urtxier) address ch0 fffe_1000 + 04h ch1 fffe_2000 + 04h ch2 fff5_0000 + 04h ch3 fff5_1000 + 04h ch4 fff4_3000 + 04h ch5 fff4_4000 + 04h (accessing is enabled only at dlab = 0) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) (reserved) edssi elsi etbei erbfi r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x 0 0 0 0 0 0 0 0 bit no. bit name function 31:4 unused reserved bit (input "0" at writing) 3 edssi enable modem status interrupt when edssi is set to "1" and bit3:0 of the m odem status register is set, interrupt occurs. 2 elsi enable receiver status interrupt when elsi is set to "1" and bit4:1 of the line status register is set, interrupt occurs. 1 etbei enable transmitter fifo register empty interrupt after etbei is set to "1", interrupt occurs when transfer fifo register becomes empty. 0 erbfi enable receiver fifo register when erbfi is set to "1" and reception fifo reaches to the trigger level, interrupt occurs. (interrupt also occurs when character time-out occurs.) interrupt can be disabled by setti ng "0" to all bits of bit3:0. all interrupt factors of the bit set "1" in bit3:0 become valid.
18-8 MB86R01 lsi product specifications fujitsu semiconductor confidential uart interface 18.6.5. interrupt id register (urtxiir) address ch0 fffe_1000 + 08h ch1 fffe_2000 + 08h ch2 fff5_0000 + 08h ch3 fff5_1000 + 08h ch4 fff4_3000 + 08h ch5 fff4_4000 + 08h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) fifo st1 fifo st0 (reserved) id2 id1 id0 nint r/w r r r r r r r r r r r r r r r r initial value x x x x x x x x 1 1 0 0 0 0 0 1 bit no. bit name function 31:8 unused reserved bit (input "0" at writing) 7:6 fifo1:0 fifo status fixed to "11" 5:4 "00" 3:0 id2:0, nint interrupt setting 0001: no interrupt 0110: reception line status (1) top priority 0100: reception data existed (2) 1100: time-out (2) 0010: transmission fi fo is empty (3) 0000: modem status (4) * bit7:0 = c1h, after the reset * numerical value in ( ) is priority level when character time-out interrupt occu rs with having received data, id2:0, nint is changed from 0100 to 1100. interrupt signal (intr) is cleared by the following operation. priority level: (1) read line status register (lsr) (2) read reception fifo (3) read interrupt id register (iir) or write to transmission fifo (4) read modem status register (msr)
18-9 MB86R01 lsi product specifications fujitsu semiconductor confidential uart interface 18.6.6. fifo control register (urtxfcr) address ch0 fffe_1000 + 08h ch1 fffe_2000 + 08h ch2 fff5_0000 + 08h ch3 fff5_1000 + 08h ch4 fff4_3000 + 08h ch5 fff4_4000 + 08h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w w w w w w w w w w w w w w w w w initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) rcvr1 rcvr0 (reserved) dma mode txf rst rxf rst (reserv ed) r/w w w w w w w w w w w w w w w w w initial value x x x x x x x x 0 0 0 0 0 0 0 0 bit no. bit name function 31:8 unused reserved bit (input "0" at writing) 7:6 rcvr1:0 reception fifo's trigger level 00: 1 byte 01: 4 byte 10: 8 byte 11: 14 byte 5:4 unused reserved bit 3 dma mode dma transfer mode (mode of xtxrdy and xrxrdy pins) 0: single transfer mode 1: demand transfer mode 2 txf rst transmission fifo reset 1: reset 1 rxf rst reception fifo reset 1: reset 0 unused reserved bit * bit7:0 = 00h, after reset
18-10 MB86R01 lsi product specifications fujitsu semiconductor confidential uart interface 18.6.7. line control register (urtxlcr) address ch0 fffe_1000 + 0ch ch1 fffe_2000 + 0ch ch2 fff5_0000 + 0ch ch3 fff5_1000 + 0ch ch4 fff4_3000 + 0ch ch5 fff4_4000 + 0ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) dlab sb sp eps pen stb wls1 wls0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x 0 0 0 0 0 0 0 0 bit no. bit name function 31:8 unused reserved bit (input "0" at writing) 7 dlab divisor latch access bit (divider latch access bit) 0: disable reception fifo register reads with address 0 transmission fifo register writes with address 0 ier register reads and writes with address 1 1: enable dll register reads and wr ites with address 0 dlm register reads and writes with address 1 6 sb set break (break transmission) 1: the sout signal forcibly becomes "0" 5 sp stick parity (fixed parity) 0: parity bit is determined by eps and pen 1: parity bit is fixed as follows depending on the status of eps and pen (checked at transmission, generati on, and reception) parity is "1" at pen = 1 and eps = 0 parity is "0" at pen = 1 and eps = 1 4 eps even parity select (parity selection) 0: odd parity 1: even parity 3 pen parity enable (parity enable) 0: parity is not sent nor checked 1: parity is sent and checked parity bit is added to end of data area, and stop bit comes last 2 stb number of stop bit (stop bit length) 0: 1 bit 1: 1.5 bit (data length: 5) 2 bit (data length: 6 ~ 8) 1:0 wls1:0 word length select (transmi ssion/reception data length) 00: 5 bit 01: 6 bit 10: 7 bit 11: 8 bit * bit7:0 = 00h, after reset
18-11 MB86R01 lsi product specifications fujitsu semiconductor confidential uart interface 18.6.8. modem control register (urtxmcr) address ch0 fffe_1000 + 10h ch1 fffe_2000 + 10h ch2 fff5_0000 + 10h ch3 fff5_1000 + 10h ch4 fff4_3000 + 10h ch5 fff4_4000 + 10h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) (reserved) loop (reserved) rts (*1) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x 0 0 0 0 0 0 0 0 *1) (reserved) bit no. bit name function 31:8 unused reserved bit (input "0" at writing) 7:5 unused reserved bit (input "0" at writing) 4 loop loop back mode (self-diagnostic mode) when loop is set to "1", following is performed. 1. sout becomes "1" 2. sin is separated from input sh ift register of reception 3. transmission shift register output is connecte d to input of the reception shift register 4. modem status is separated (ncts, ndsr, ndcd, and nri) 5. modem control signal is connect ed to modem status input cts ? rts 3 unused reserved bit 2 unused reserved bit 1 rts control signal "1" makes output pin active. 0 unused reserved bit * bit7:0 = 00h, after reset
18-12 MB86R01 lsi product specifications fujitsu semiconductor confidential uart interface 18.6.9. line status register (urtxlsr) address ch0 fffe_1000 + 14h ch1 fffe_2000 + 14h ch2 fff5_0000 + 14h ch3 fff5_1000 + 14h ch4 fff4_3000 + 14h ch5 fff4_4000 + 14h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) errf temt thre bi fe pe oe dr r/w r r r r r r r r r r r r r r r r initial value x x x x x x x x 0 1 1 0 0 0 0 0 bit no. bit name function 31:8 unused reserved bit 7 errf error in rcvr fifo (error in reception fifo) this bit is set even 1 error of parity, flaming, or break de tection is in reception fifo. if data including error (except the one set errf flag) is not in reception fifo at reading lsr register, this is reset. 6 temt transmitter empty (transmission shift register empty) when both transmission shift register and tran smission fifo register become empty, temt is set to "1". 5 thre transmitter fifo register empty (transmission register empty) when transmission fifo register is empty and ready to accept new data, thre is set to "1". this bit is cleared at sending data to transmission shift register. 4 bi break interrupt (break reception) this bit is set when sin is held in "0" more than transmission time (start bit + data bit + parity + stop bit.) bi is reset by cpu reading this register. 3 fe framing error (flaming error) this bit is set when reception data does not have valid stop bit. fe is reset by cpu reading this register. 2 pe parity error (parity error) this bit is set when reception data does not have valid parity bit. pe is reset by cpu reading this register. 1 oe overrun error (overrunning error) this bit is set when reception fifo is full and receives the next reception data. oe is reset by cpu reading this register. 0 dr data ready (reception data existed) this bit shows 1 byte or more of data is in fifo. this bit is set when data is in fifo and reset after reading all data in fifo. * bit7:0 = 60h, after reset
18-13 MB86R01 lsi product specifications fujitsu semiconductor confidential uart interface 18.6.10. modem status register (urtxmsr) address ch0 fffe_1000 + 18h ch1 fffe_2000 + 18h ch2 fff5_0000 + 18h ch3 fff5_1000 + 18h ch4 fff4_3000 + 18h ch5 fff4_4000 + 18h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) (reserved) cts (reserved) dcts r/w r r r r r r r r r r r r r r r r initial value x x x x x x x x x x x x 0 0 0 0 bit no. bit name function 31:8 unused reserved bit 7 unused reserved bit 6 unused reserved bit 5 unused reserved bit 4 cts clear to send loop = 0: inversed input si gnal, xcts is indicated loop = 1: it is equal to rts of mcr 3 unused reserved bit 2 unused reserved bit 1 unused reserved bit 0 dcts delta clear to send this bit is set when cts signal changes after th e last reading by cpu. the bit is reset by reading this register. * bit7:0 = x0h, after reset bit4 is monitor bit of external pin
18-14 MB86R01 lsi product specifications fujitsu semiconductor confidential uart interface 18.6.11. divider latch register (urtxdll&urtxdlm) this register is frequency dividing latch to ge nerate necessary baud rate from clock input. frequency diving latch consists of 16 bit, dlm (high order byte) and dll (low order byte.) [dll] address ch0 fffe_1000 + 00h ch1 fffe_2000 + 00h ch2 fff5_0000 + 00h ch3 fff5_1000 + 00h ch4 fff4_3000 + 00h ch5 fff4_4000 + 00h (accessing is enabled only at dlab = 1) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) dl[7:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x 0 0 0 0 0 0 0 0 [dlm] address ch0 fffe_1000 + 04h ch1 fffe_2000 + 04h ch2 fff5_0000 + 04h ch3 fff5_1000 + 04h ch4 fff4_3000 + 04h ch5 fff4_4000 + 04h (accessing is enabled only at dlab = 1)) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) dl[15:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x 0 0 0 0 0 0 0 0 dll and dlm are read/written when dl ab bit of lcr is set to "1". ? after the reset, dll and dlm are 00h ? dll and dlm values are loaded by writing to either dll or dlm ? baud rate is settable in the range that dlm and dll are ffffh ~ 0001h
18-15 MB86R01 lsi product specifications fujitsu semiconductor confidential uart interface to calculate transfer baud rate transfer baud rate (bps) = (apb clock frequency (hz)/fr equency dividing value)/16 example of frequency dividing value (dlm and dll values) and baud rate is shown in table 18-3. t able 18-3 example of frequency dividing value (dlm and dll values) and baud rate MB86R01 baud rate dll value (decimal) (dlm = 0) apb clock = 41.663(mhz) (external input condition: clk = 33.33mhz, cripm[3:0] = 0011) the other party's baud rate (error range) 2170 1200 1200 (100%) 1085 2400 2400 (100%) 542 4804 4800 (99.9%) 271 9609 9600 (99.9%) 181 14386 14400 (100.1%) 136 19147 19200 (100.3%) 90 28933 28800 (99.5%) 68 38293 38400 (100.3%) 45 57865 57600 (99.5%) 23 113215 115200 (101.8%) transmission baud rate on the other party and baud rate used by macro are able to receive data properly within the permissible error range. out of the range causes reception error. baud rate's permissible error range that macro permits is shown below. 104.1% > macro baud rate (100%) > 95.3% when baud rate used by macro is w ithin the reception baud rate's permissi ble error range of the other party, data is able to be received. out of the range causes error on th e other party side. after the reset (mr = 1), it takes 1/4 bit of time from setting dll and dlm to enable start bit detection. although start bit (sin = 0) is received in the peri od, proper start bit det ection is not performed.
18-16 MB86R01 lsi product specifications fujitsu semiconductor confidential uart interface 18.7. uart operation 18.7.1. example of initial setting set dlab bit of line control register set low order frequency dividing latch set high order frequency dividing latch 1. 2. 3. 4. reset dlab bit of line control register set transmission/reception format in line control register set interrupt enable register 5. 6. reset end figure 18-2 example of initial setting 1. after the power-on, macro's each output pin is undefined. each output pin level becomes the one shown in the table of chapter 5 by inputting "l" to reset (mr) pin. 2. divider latch is able to be accessed by setting "1" to dlab bit in the line control register (lcr register.) 3. set baud rate clock (refer to " 18.6.11 divider latch register (urtxdll&urtxdlm)".) 4. set "0 " to dlab bit in the line control register. 5. set transmission/reception format by setting the line control register. 6. control each interrupt by setting the interrupt enable register (ier register.)
18-17 MB86R01 lsi product specifications fujitsu semiconductor confidential uart interface 18.7.2. example of transfer procedure set transmission data to transmission fifo no 1. 2. yes transmission procedure end transmission fifo is empty figure 18-3 example of transfer procedure 1. check transmission fifo is empty with following method: a. polling process of thre bit in the line status register (lsr) thre bit shows transmission fifo status. when the fifo is empty, the bit becomes "1". b. polling process of temt bit in the line status register (lsr) temt bit shows transmission fifo and transmission shif t register statuses that data in transmission process and empty transmission fifo are able to be confirmed. when they are empty, temt becomes "1". c. transmission fifo empty interrupt process when all data in transmission fifo is moved to the transmission shift register, this interrupt occurs. it is able to control approval/prohibition in the interrupt enable register (urtxier.) note: during transmission fifo empty interrupt process, check thre bit of the lsr is "1" before writing data to transmission fifo. ? thre = 1: transmission fifo is empty that data is able to be written ? thre = 0: transmission fifo is not empty. retry from interrupt process to be fifo empty interrupt status without writing data to transmission fifo. 2. set transmission data to transmission fifo. up to 16 byte is able to be set in the fifo at a time. in this case, thre bit of the lsr becomes "0". note: the last written data is deleted when writing data to transmission fifo while it is full.
18-18 MB86R01 lsi product specifications fujitsu semiconductor confidential uart interface 18.7.3. example of reception procedure interrupt occurs data ready or line status interrupt? reception data ready interrupt 1. 2. 3. 4. line status interrupt interrupt factor check (reception error factor) reading reception fifo reception procedure end figure 18-4 example of reception procedure 1. when certain interrupt is permitted, interrupt o ccurrence is able to be confirmed with interrupt (intr) pin (at intr = "h".) moreover, it is confirmed by polling nint bit in the interrupt id register (iir register) (at nint = "0".) 2. type of interrupt is able to be observed by confirming id0, id1 and id2 bit in the interrupt id register. 3. after interrupt type is judged as reception line status in terrupt with the process in item 2, reception error information is able to be acq uired by reading the line status register which also releases the interrupt (intr= "l".) 4. after interrupt type is judged as reception data ready interrupt with th e process in item 2, read number of character corresponding to the trigger level to acquire reception character. reception data ready status is also able to be confirmed by referring dr bit in the line status register. the interrupt is released when data in fifo becomes less than the trigger level (intr= "l".)
18-19 MB86R01 lsi product specifications fujitsu semiconductor confidential uart interface 18.7.4. basic transmission operation 1 character mark state start bit parity bit data bit stop bit uart_soutx (thre) d0 d1 d2 d3 d4 d5 pt d0 pt (temt) intr xtxrdy this is example of the case, data bit length is 6 bit and stop bit length is 2 bit, and parity apb clk figure 18-5 basic transmission operation when initial reset is completed and transmission data is not written to the transmission shift register in the transmission control part (mark state), state of "h" level continues applying to serial transmission (sout) pin. the data is output from serial transmission (sout) pin with adding start bit, parity bit, and stop bit in the transmission control part as shown in figure 18-5 when transmission data is written from cpu to transm ission fifo. 1 ~ 16 byte of transmission data is able to be consecutively written to transmission fifo at a time. transmission fifo state is able to be confirmed with thre bit of the lsr register. when transmission data is written to transmission fifo though it is full, the last written data is deleted. the data that is already st ored in the transmission fifo is properly transmitted. thre bit becomes "0" by writing to transmission fifo . when the writing data is transferred to the transmission shift register and fifo becomes empty, the value becomes "1". if transmission data buffer interrupt is permitted in that time, interrupt (intr) pin becomes "h" and interrupt occurs. this interrupt is released by writing data to the transmission fifo again or reading the interrupt confirmation register. temt bit becomes "0" at the same timing of thre bit, and the value becomes "1 " after transmission of all written data is completed. xtxrdy is data ready signal that shows possible tran smission to dma controller at using the controller. single transfer mode is supported when bit 3 of the fcr register is "0" and the demand transfer mode is supported when the bit is "1". when transmission baud rate used by macro is with in the reception baud rate pe rmissible error range, the other party is able to receive data. out of the range causes reception error on the other party side.
18-20 MB86R01 lsi product specifications fujitsu semiconductor confidential uart interface 18.7.5. basic reception operation 1 character mark state start bit parity bit data bit stop bit uart_sinx (dr) d0 d1 d2 d3 d4 d5 pt d0 pt intr xrxrdy this is example of the case, data bit length is 6 bit and stop bit length is 2 bit, and parity apb clk figure 18-6 basic reception operation after detecting received start bit ("l" level) from serial input (sin) pin, the bit r eceiving next is regarded as start bit of reception data. then, received data is sampled with reception clock, an d stop bit is detected after receiving data bit and parity bit. when transmission error occurs during th at time, its factor (break detection, flaming error, parity error, and overrunning error) is applied to each data in fifo, and the status is maintained. status can be confirmed by cpu at the first data of fifo. when reception data ready interrupt is permitted, in terrupt (intr) pin becomes "h" and interrupt occurs by reaching the data in reception fifo to the trigger level. this interrupt is released when the data in the fifo becomes less than the trigger level, and interrupt (intr) pin becomes "l". xrxrdy is data ready signal that shows possible reception to dma controller at using the controller. single transfer mode is supported when bit 3 of the fcr register is "0" and the demand transfer mode is supported when the bit is "1". when transmission baud rate of the other party and baud rate used by macro are within the reception baud rate permissible error range, data is able to be received properly. ou t of the range causes reception error. baud rate permissible error range that macro permits is as follows. 104.1% > macro baud rate (100%) > 95.3% after reset (mr = 1), the time reaching to enable detec tion of start bit is 1/4 bit after dll and dlm are set. even if start bit (sin=0) is received during this pe riod, normal start bit detection is not performed.
18-21 MB86R01 lsi product specifications fujitsu semiconductor confidential uart interface 18.7.6. line status thre flag and temt flag operation example of thre flag and temt flag of bit 5 and 6 in the line status register (lsr) is shown in figure 18-7. sout (thre) data1 data2 data3 data4 data5 data2 data4 data5 mark state (temt) transmission buffer write transmission buffer data3 clk figure 18-7 example of operation of thre flag and temt flag thre flag = "1" indicates that there is no data in the transmission fifo buffer register, and transmission character is able to be written. temt flag becomes "1" when there is no data in th e register and transmission shift register in the transmission control part. both flags become "0" at writing "0" to transmission fifo buffer.
18-22 MB86R01 lsi product specifications fujitsu semiconductor confidential uart interface fe flag and bi flag operation example of bi flag and of bit 4 and 3 and fe flag in the line status register (lsr) is shown in figure 18-8. 1 character uart_sinx (fe) d0 d1 d2 d3 d4 sppt (bi) uart_sinx (note) urtxlsr register reading urtxrfr register reading 1 character d0 d1 d2 d3 d4 sp pt d0 d1 d2 d3 d4 sp pt figure 18-8 operation example of fe flag and bi flag if "l" level is received at the stop bit during reception operation, flaming error o ccurs and fe flag becomes "1". the error flag is reset by reading line status register. when "l" level continues during transmission time (start bit, data bit, parity bit, and stop bit) for 1 character, break code is detected. these errors are app lied to each data in fifo, and they are able to be confirmed when cpu reads the first data of fifo. fe and bi flags are able to be confirmed in the status register at reading line status register whose first data includes framing and break detection error. both flags become "0" by reading status register. for the case of break detection error, rece ption data is stored to fifo as 0. when break is detected, macro stops reception, and it re starts the process with detecting sin's falling edge.
18-23 MB86R01 lsi product specifications fujitsu semiconductor confidential uart interface pe flag operation example of pe flag of bit 2 in the line status register (lsr) is shown in figure 18-9. 1 character mark state start bit parity bit data bit stop bit uart_sinx normal completion 1 0 1 0 1 0 1 d0 pt (pe-fifo) urtxlsr register reading abnormal completion d0 d1 d2 d3 d4 d5 pt uart_sinx 1 0 0 0 1 0 1 d0 pt d0 d1 d2 d3 d4 d5 pt (pe) figure 18-9 operation example of pe flag (setting even parity) parity bit is set to "1" or "0" depending on the number of "1" level bit in the 1 data bit. when it is set to even parity with eps in the line control register, the b it is set to "1" or "0" to have total data bit and "1" level parity bit even number. likewise, when parity bit is set to odd parity, total number of "1" level is set to be odd number. on reception side, the number of "1" level bit of 1 data including input parity bit is counted, and polarity of the parity set with eps bit in the line control register is compared. for their discrepancy, pe flag of the register becomes "1" by the judgment that problem occurred in transmitting data. then the flag becomes "0" by reading the line status register. this error is applied to each data in fifo, and is able to be conf irmed when cpu reads first data of fifo.
18-24 MB86R01 lsi product specifications fujitsu semiconductor confidential uart interface oe flag operation example of oe flag of bit 1 in the line status register (lsr) is shown in figure 18-10. uart_sinx (dr) d14 d15 d16 line status d1 d15 d16 d17 (oe) apb reading fifo full d2 figure 18-10 operation example of oe flag when next character is received completely to the recep tion shift register in the st atus that reception fifo is full, overrun error occurs. in this case, oe flag of the line status register is set immediately and interrupt occurs (if it is permitted.) dr flag operation example of dr flag of bit 0 in the line status register (lsr) is shown in figure 18-11. 1 character mark state start bit parity bit data bit stop bit uart_sinx (dr) d0 d1 d2 d3 d4 d5 pt d0 pt urtxrfr register reading figure 18-11 operation example of dr flag when reception data is received and 1 byte or more of da ta is stored in reception fifo, dr flag of the line status register becomes "1". the flag becomes "0" by reading rece ption fifo data and fifo becomes empty. errf flag when error (parity, break detection, and flaming) is in cluded in the data stored in reception fifo, errf flag of bit 7 of the line status register (lsr) is set to "1" during reception operation. if there is no error data in fifo except the one set errf flag when cpu reads the register, this flag is cleared to "0".
18-25 MB86R01 lsi product specifications fujitsu semiconductor confidential uart interface 18.7.7. character time-out interrupt character time-out interrupt o ccurs in the following cases: ? 1 or more data is stored in reception fifo and th e next serial data is still not received after 4 characters of time ? 1 or more data is stored in reception fifo and cp u still does not read the data after 4 characters of time when time-out interrupt occurs, intr pin becomes "h". moreover, xrxrdy signal becomes "l", showing dma controller that reception is ready, and requests to read data. timer and time-out interrupt are reset by cpu (or dma controller) reading 1 byte from reception fifo. if time-out does not occur, it is reset after timer r eceives new data or cpu (or dma controller) reads data from reception fifo.
19-1 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface 19. i 2 c bus interface this chapter describes function and operation of i 2 c bus interface. 19.1. outline i 2 c bus is serial bus advocated by philips semiconducto rs (now nxp) that suppor ts data between multiple devices with 2 signals. MB86R01 equips 2 channels of interface corresponding to i 2 c standard mode (max. 100kbps)/high-speed mode (max. 400kbps.) external pin, i2c_sda0, i2c_sda1, i2c_scl0, and i2c_scl1 uses 3.3v exclusive i/o, so that it is able to be used in 3.3v i 2 c. i2c_sda0/i2c_sda1 are indicated as sda line, and i2c_scl0/i2c_scl1 are indicated as scl line in this document. 19.2. feature i 2 c has following features: ? master transmission/reception function ? slave transmission/reception function ? arbitration function ? clock synchronization function ? slave address detecting function ? general call address detecting function ? transfer direction detecting function ? repeat occurrence and detectin g function of start condition ? bus error detecting function ? corresponding to standard mode (max. 100kbps)/high-speed mode (max. 400kbps)
19-2 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface 19.3. block diagram figure 19-1 shows block diagram of i 2 c. start condition/stop condition detector arbitration lost detector start condition/stop condition detector shift clock generator i2c_sda0 i2c_scl0 noise filter i2c adr apb bus i2c module 0 i2c module 1 i2c_sda1 i2c_scl1 MB86R01 comparator i2c dar i2c bsr i2c bcr i2c ccr i2c bc2r i2c ecsr i2c bcfr figure 19-1 block diagram of i 2 c
19-3 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface block function each block function is described below. table 19-1 i 2 c block function block description start condition/stop condition detector start condition and stop condition are detect ed from transition state of sda and scl lines. start condition/stop condition generator start condition and stop condition are issued from transition state of sda and scl lines. arbitration lost detector output data to sda line and input data from sda line are compared at data transmission. if they are unmatched, arbitration lost occurs. shift clock generator timing count of serial data t transfer clock oc currence and output control of scl line clock are performed with clock control register setting. comparator received address and self-address specified to address register, or received address and global address are compared. i2cxadr 7 bit register that specifies slave address. i2cxdar 8 bit register used for serial data transfer. i2cxbsr 8 bit register with following functions to show i 2 c bus status and others. ? repeated start condition detection ? arbitration lost detection ? acknowledge bit storage ? direction of data transfer ? addressing detection ? general call address detection ? first byte detection i2cxbcr 8 bit register that performs i 2 c bus control and interr upt control has following functions. ? interrupt request/permission ? start condition occurrence ? master/slave selection ? acknowledge occurrence permission i2cxccr 7 bit register that sets clock frequency of serial data transfer. ? operation permission ? frequency setting of serial clock ? standard/high-speed mode selection noise filter this is noise filter composed of 3 stage shift register circuit. when all 3 values consecutively sampled scl/sda line input signals are "1", the filter output becomes "1". when those values are "0", the filter output becomes "0". for other sampling, the stat e 1 clock before is maintained. i2cxbc2r this is the register to drive "l" forc ibly and to confirm the line status after noise filter is passed. i2cxecsr this is the register to enhance cs bit in i2cxccr register. i2cxbcfr this is the register that specifies frequency range of bus clock to be used.
19-4 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface 19.4. related pin i 2 c uses following pins. table 19-2 i 2 c related pin pin direction qty. description i2c_scl0 i2c_scl1 in/out 2 clock pin of i 2 c bus interface. the last number of the pin name indicates channel number of i 2 c. output of this pin is open drain. i2c_sda0 i2c_sda1 in/out 2 data pin of i 2 c bus interface. the last number of the pin name indicates channel number of i 2 c. output of this pin is open drain. 19.5. supply clock apb clock is supplied to i 2 c. refer to "5. clock reset generator (crg)" for frequency setting and control specification of the clock.
19-5 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface 19.6. register this section describes i 2 c bus interface register. 19.6.1. register list this lsi equips 2 channels of i 2 c bus interface, and each module has the register shown in table 19-3. ta ble 19-3 i 2 c register list channel address register description fff56000h i2c0bsr bus status register fff56004h i2c0bcr bus control register fff56008h i2c0ccr clock control register fff5600ch i2c0adr address register fff56010h i2c0dar data register fff56014h i2c0ecsr extension cs register fff56018h i2c0bcfr bus clock frequency register i 2 c ch0 fff5601ch i2c0bc2r bus control 2 register fff57000h i2c1bsr bus status register fff57004h i2c1bcr bus control register fff57008h i2c1ccr clock control register fff5700ch i2c1adr address register fff57010h i2c1dar data register fff57014h i2c1ecsr extension cs register fff57018h i2c1bcfr bus clock frequency register i 2 c ch1 fff5701ch i2c1bc2r bus control 2 register note: access the area of i 2 c ch0 and i 2 c ch1 in 32 bit (word)
19-6 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface description format of register following format is used for descri ption of register?s each bit in " 19.6.2 bus status register (i2cxbsr)" to " 19.6.9 bus clock frequency register (i2cxbcfr)". address base address + offset bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r/w initial value bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r/w initial value meaning of item and sign address address (base address + offset address) of the register bit bit number of the register name bit field name of the register r/w attribution of read/write of each bit field ? r0:read value is always "0" ? r1: read value is always "1" ? w0: write value is always "0", and write access of "1" is ignored ? w1: write value is always "1", and write access of "0" is ignored ? r: read ? w: write initial value each bit field?s value after reset ? 0: value is "0" ? 1: value is "1" ? x: value is undefined
19-7 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface 19.6.2. bus status register (i2cxbsr) address ch0 fff5_6000 + 00h ch1 fff5_7000 + 00h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) bb rsc al lrb trx aas gca fbt r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 all bit of this register is cleare d during en bit of i2cxccr is "0". bit 7: bb (bus busy) this bit shows i 2 c bus state. bb status 0 stop condition is detected 1 start condition is detected (but is in use) bit 6: rsc (repeated start condition) repeated start condition detecting bit. rsc state 0 repeated start cond ition is not detected 1 start condition is detected again during bus is in use this bit is cleared by writing "0" to int bit, start condition detection at bus stop, and stop condition detection as well as addressing is not performed at slave. bit 5: al (arbitration lost) arbitration lost detecting bit al state 0 arbitration lost is not detected 1 arbitration lost occurs during master transmission, or "1" is written to mss bit while other systems are using bus this bit is cleared by writing "0" to int bit. restrictions: in the multi master environment, prohibit other masters to transmit general call address simultaneously with this module, as well as use of arbitration lost by this module at the second byte or later.
19-8 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface bit 4: lrb (last received bit) this bit is to store 9th bit of the data indicating acknowledge (ack)/negative acknowledge (nack). lrb state 0 acknowledge (ack) is detected 1 negative acknowledge (nack) is detected this bit is cleared at start condition detection or stop condition detection. bit 3: trx (transfer/receive) this bit is to indicate transmission/reception state of data transfer. trx state 0 reception state 1 transmission state bit 2: aas (address as slave) this is addressing detection bit. aas state 0 addressing is not performed at slave 1 addressing is performed at slave this is cleared at start condition detection or stop condition detection. bit 1: gca (general call address) this is general call address (00h) detecting bit. gca state 0 general call address is not received at slave 1 general call address is received at slave this bit is cleared at start condition detection or stop condition detection. bit 0: fbt (first byte transfer) this is first byte detecting bit. fbt state 0 reception data is not first byte 1 reception data is the first byte (address data) although this is set to "1" at start condition detec tion, it is cleared if "0" is written to int bit and addressing is not performed at the salve.
19-9 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface 19.6.3. bus control register (i2cxbcr) address ch0 fff5_6000 + 04h ch1 fff5_7000 + 04h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) ber beie scc mss ack gcaa inte int r/w r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 this is cleared during en bit of i2cxccr is "0", except bit 7 and 6 of this register. bit 7: ber (bus error) this is bus error interrupt request flag bit. at writing ber state 0 bus error interrupt request flag is cleared 1 n/a at reading ber state 0 bus error is not detected 1 incorrect start and stop conditions are detected during data transfer when this bit is set, en bit of i2cxccr resister is cleared, this m odule becomes in halt state, and the data transfer is discontinued. bit 6: beie (bus error interrupt enable) this is buss error interrupt permission bit. at reading/writing beie state 0 bus error interrupt is prohibited 1 bus error interrupt is permitted when this bit is "1" and ber bit is "1", interrupt occurs. bit 5: scc (start condition continue) this is start condition generation bit. at writing scc state 0 n/a 1 start condition is generated again at master transfer this bit is automatically cleared after setting "1".
19-10 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface bit 4: mss (master slave select) this is master/slave selection bit. at writing mss state 0 stop condition is generated, and state becomes slave mode after the transfer 1 state becomes master mode, and start c ondition is generated to start transfer this bit is cleared when arbitration lost occurs during master transmission, and state becomes slave mode. restrictions: in the multi master environment, prohibit other masters to transmit general call address simultaneously with this module and to use arbitration lost by this module at the second byte or later. bit 3: ack (acknowledge) this is acknowledge permission bit at receiving data. at reading/writing ack state 0 acknowledge is not occurred. 1 acknowledge is occurred. this bit is disabled at address data reception in the slave mode. bit 2: gcaa (general call address acknowledge) this is acknowledge permission b it at receiving general call address. at reading/writing gcaa state 0 acknowledge is not occurred. 1 acknowledge is occurred. bit 1: inte (interrupt enable) this is interrupt permission bit. at reading/writing inte state 0 interrupt is prohibited 1 interrupt is enabled when this bit is "1" and int bit is "1", interrupt occurs.
19-11 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface bit 0: int (interrupt) this is transfer end interrupt request flag bit. at writing int state 0 transfer end interrupt flag is cleared 1 n/a at reading int state 0 transfer is not completed 1 this is set when following conditions are applied at completion of 1 byte transfer which includes acknowledge bit. ? bus master ? addressed slave ? general call address is received (only at gcaa "1") ? arbitration lost occurs (only at bus acquisition state) ? start condition is attempted while other systems use bus when this bit is "1", scl line is maintained in "l" level. this is cleared by writing "0" to this bit, then scl line opens and the next byte is transferred. moreover, this is cleared to "0" by occurrence of start condition or stop condition at the master mode. competition of scc, mss, and int bits competition of the next byte transfer, start condition, and stop condition occurs by writing scc, mss, and int bits simultaneously. priority order in this case is as follows. 1. occurrence of the next byte transfer and stop condition when writing "0" to int bit and mss bit simultane ously, mss bit is prioritized and stop condition occurs. 2. occurrence of the next byte transfer and start condition when writing "0" to int bit and "1" to scc bit si multaneously, scc bit is prioritized and start condition occurs. 3. occurrence of start condition and stop condition writing "1" to scc bit and "0" to mss bit simultaneously is prohibited.
19-12 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface 19.6.4. clock control register (i2cxccr) address ch0 fff5_6000 + 08h ch1 fff5_7000 + 08h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) (reserved) hsm en cs[4:0] r/w r r r r r r r r r r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 1 0 0 x x x x x bit 7: unused the value is always "1" at reading. bit 6: hsm (high speed mode) this is standard/high-speed setting bit. at reading/writing hsm state 0 standard mode 1 high-speed mode bit 5: en (enable) this is operation permission bit. at reading/writing en state 0 operation is prohibited 1 operation is permitted when this bit is "0", each bit of i2cxbsr regist er and i2cxbcr register (e xcluding ber and beie bits) is cleared. when ber bit is set, this bit is cleared.
19-13 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface bit 4-0: cs4-0 (clock period select 4-0) this bit is to set frequency of serial transfer clock. upper bound of the bus clock frequency is able to be extended by setting i2cxecsr register. refer to " 19.6.8 expansion cs register (i2cxecsr)" for details. wh en i2cxecsr register is not used (using i2cxecsr register in initial state), frequency fscl of serial transfer clock becomes the expression shown below. at standard mode clockapb m fscl _ 2)2( : + = at high-speed mode tpoin decimal afteroffround clockapb m fscl :) int( _ 2)5.1int( : + = be sure to set fscl not to exceed the following values at the master operation. ? at standard mode: 100khz. ? at high-speed mode: 400khz. apb clock of this module should be used within the range shown below. when it is less than the range, transmission by max. transfer rate is not guaranteed. when it exceeds the range, upper bound of the bus clock frequency is able to be extended by setting i2cxecsr register. ? at the master operation: 14mhz ~ 18mhz. ? at the slave operation: 14mhz ~ 18mhz. ? at the register access operation: 14mhz ~ 41.5mhz note: +2 cycle is min. overhead for checking output level change of scl line. when rising edge delay of scl line is large or the clock is enlarged with slave device, the value is lager than the above. the value of m to cs4 ~ 0 is shown in the next page
19-14 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface m cs4 cs3 cs2 cs1 cs0 standard high speed 0 0 0 0 0 65 setting prohibited 0 0 0 0 1 66 setting prohibited 0 0 0 1 0 67 setting prohibited 0 0 0 1 1 68 setting prohibited 0 0 1 0 0 69 setting prohibited 0 0 1 0 1 70 setting prohibited 0 0 1 1 0 71 setting prohibited 0 0 1 1 1 72 setting prohibited 0 1 0 0 0 73 9 0 1 0 0 1 74 10 0 1 0 1 0 75 11 0 1 0 1 1 76 12 0 1 1 0 0 77 13 0 1 1 0 1 78 14 0 1 1 1 0 79 15 0 1 1 1 1 80 16 1 0 0 0 0 81 17 1 0 0 0 1 82 18 1 0 0 1 0 83 19 1 0 0 1 1 84 20 1 0 1 0 0 85 21 1 0 1 0 1 86 22 1 0 1 1 0 87 23 1 0 1 1 1 88 24 1 1 0 0 0 89 25 1 1 0 0 1 90 26 1 1 0 1 0 91 27 1 1 0 1 1 92 28 1 1 1 0 0 93 29 1 1 1 0 1 94 30 1 1 1 1 0 95 31 1 1 1 1 1 96 32
19-15 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface 19.6.5. address register (i2cxadr) address ch0 fff5_6000 + 0ch ch1 fff5_7000 + 0ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) (reserved) a[6:0] r/w r r r r r r r r r r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 1 x x x x x x x bit 7: unused the value is always "1" at reading. bit 6-0: a6-0 (address 6-0) this is slave address storage bit. the comparison with i2cxdar re gister is performed after addr ess data reception at slave. if they are matched, acknowledge is transmitted to master.
19-16 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface 19.6.6. data register (i2cxdar) address ch0 fff5_6000 + 10h ch1 fff5_7000 + 10h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) d[7:0] r/w r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 x x x x x x x x bit 7-0: d7-0 (data 7-0) this is serial data storage bit. this data register is used for serial transfer tran smitted from msb. when data is received (trx = 0), the data output becomes "1". this register's writing side is double buffer that wr iting data is loaded to serial transfer register at transmission of each byte if bus (bb = 1) is in use. since serial transfer register is dir ectly read at reading, received data is valid only when int bit is set.
19-17 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface 19.6.7. two bus control registers (i2cxbc2r) address ch0 fff5_6000 + 1ch ch1 fff5_7000 + 1ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) (reserved) sdas scls (reserved) sdal scll r/w r r r r r r r r r r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 x x 0 0 bit 7 and 6: unused the value is always "00" at reading. bit 5: sdas (sda status) signal level of sda line after passed noise filter is indicated. only reading is valid. sdas state 0 the sda line is "0" 1 the sda line is "1" bit 4: scls (scl status) signal level of scl line after passed noise filter is indicated. only reading is valid. scls state 0 scl line is "0" 1 scl line is "1" bit 3 and 2: unused the value is always "00" at reading. bit 1: sdal (sda low drive) sdao output is forcibly become "l". both reading/writing are valid. sdal state 0 sdal output is in normal operation 1 sdal output is forcibly become "l" bit 0: scll (scl low drive) sclo output is forcibly become "l". both reading/writing are valid. scll state 0 sclo output is in normal operation 1 sclo output is forcibly become "l"
19-18 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface 19.6.8. expansion cs register (i2cxecsr) address ch0 fff5_6000 + 14h ch1 fff5_7000 + 14h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) (reserved) cs[10:5] r/w r r r r r r r r r r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 5-0: cs10-5 (clock period select 10-5) this is set to expand upper bound of bus clock frequency with extending cs4 ~ 0 in the i2cxccr register. initial value of cs10 ~ 5 is "000000", and setting other values goes into frequency upper bound expansion mode. cs10~5 state 000000 no upper bound expansion of bus clock frequency (only cs4 ~ 0 is used) other than 000000 there is upper bound expansion of bus clock frequency
19-19 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface standard mode: 10)10 (: : _ 2)2( csofvalue m clockapb m fscl + = high-speed mode: tpoin decimal afteroffround m m fscl csofvalue apbclock :) int( 2)5.1int( 10)10 (: : + = set fscl not to exceed the following values at master operation. ? standard mode: 100khz ? high-speed mode: 400khz use system clock of this module within the range shown below. when it is less than the range, transfer in max. transfer rate is not guaranteed. when it exceeds the range, the operation is not guaranteed. ? master operation: 14mhz ~ 41.5mhz ? slave operation: 14mhz ~ 41.5mhz ? register access operation: 14mhz ~ 41.5mhz note: +2 cycle is min. overhead for checking output level change of scl line. when rising edge delay of scl pin is large or the clock is enlarged with slave device, the value is lager than the above. when extension cs register is used, m value becomes cs10 ~ 0 + 1.
19-20 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface 19.6.9. bus clock frequency register (i2cxbcfr) address ch0 fff5_6000 + 18h ch1 fff5_7000 + 18h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) (reserved) fs[3:0] r/w r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 bit 7 and 4: unused the value is always "0000" at reading. bit 3-0: fs3-0 (bus clo ck frequency select 3-0) select frequency of the bus clock to be used. char acteristics such as noise filters are set with this register's setting. a standard setting value is shown below; however, adjustment might be required depending on i 2 c buffer characteristics and noise state on i 2 c bus. fs3 fs2 fs1 fs0 frequency [mhz] 0 0 0 0 setting prohibited 0 0 0 1 14 or more ~ less than 20 0 0 1 0 20 or more ~ less than 40 0 0 1 1 40 or more ~ less than 60 0 1 0 0 ? 0 1 0 1 ? 0 1 1 0 ? 0 1 1 1 ? 1 0 0 0 ? 1 0 0 1 ? 1 0 1 0 ? 1 0 1 1 ? 1 1 0 0 ? 1 1 0 1 ? 1 1 1 0 ? 1 1 1 1 ?
19-21 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface 19.7. operation i 2 c bus communicates with 2 interactive bus lines, seri al data line (sda) and serial clock line (scl.) this module is connected to sda and scl lines through open drain io cell by wired logic. 19.7.1. start condition when "1" is written to mss bit with bus open (bb = 0), this module becomes master mode, and start condition occurs at the same time. in the master mode, the start condition can be occurred again by writing "1" to scc bit even if the bus is in use (bb = 1). there are 2 ways of condition to engender start condition. 1. writing "1" to mss bit in status (mss = 0 & bb = 0 & int = 0 & al = 0) that bus is not used 2. writing "1" to scc bit in interrupt status (mss = 1 & bb = 1 & int = 1 & al = 0) at bus master when "1" is written to mss bit at idling, al bit is set to "1". writing "1" to mss bit and scc bit in other states than the above is ignored. start condition on i 2 c bus changing sda line from "1" to "0" while scl line is "1" is called start condition. i2c_sdax i2c_sclx start condition figure 19-2 start condition on i 2 c bus
19-22 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface 19.7.2. stop condition when "0" is written to mss bit at master operation (mss = 1), stop condition occurs and mode becomes slave. following is condition to engender stop condition. 1. writing "0" to mss bit in interrupt status (mss = 1 & bb = 1 & int = 1 & al = 0) at bus master writing "1" to mss bit in other states than the above is ignored. stop condition on i 2 c bus changing sda line from "0" to "1" while scl line is "1" is called stop condition. i2c_sdax i2c_sclx stop condition figure 19-3 stop condition on i 2 c bus
19-23 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface 19.7.3. addressing in the master mode, status is set to bb = "1" and tr x = "1" after start condition occurs, and contents of i2cxdar register is output from msb. when ac knowledge is received from the slave after sending address data, bit 0 of its data (i2cxdar register?s b it 0 after transmission) is reversed and stored to trx bit. in the salve mode, status is set to bb = "1" and trx = "0" after start condition occurs, and transmission data from the master is received to i2cxdar regist er. after receiving address data, i2cxdar register and i2cxadr register are compared . when they are matched, status is set to aas = "1" and acknowledge is sent to the master, then bit 0 of the reception data (i2cxdar register?s bit 0 after reception) is stored to trx bit. transfer format of slave address transfer format of the slave address is shown below. msb lsb slave address r/ a6 a0 a5 a1 a4 a2 a3 ack figure 19-4 slave address's transfer format map of slave address slave address map is shown below. slave address r/w description 0000 000 0 general call address 0000 000 1 start byte 0000 001 x cbus address 0000 010 x reserved 0000 011 x 0000 1xx x reserved 0001 xxx 1110 xxx x available slave address 1111 0xx x 10 bit slave address (*1) 1111 1xx x reserved *1: this module does not support 10 bit slave address
19-24 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface 19.7.4. synchronous arbitration of scl when multiple i 2 c devices become master device almost the same time to operate scl line, each device detects scl line status and automatically adjusts the line?s operation timing with k eeping the pace to slow device. i2c_sclx scl output (before arbitration) macro a macro b take timing from when scl line becomes "h" to the next scl output = "l" take timing from when scl line becomes "h" to the next scl output = "l" scl output (after arbitration) scl output (before arbitration) scl output (after arbitration) figure 19-5 scl output's synchronous arbitration
19-25 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface 19.7.5. arbitration arbitration occurs when other masters also transmit data at the same time. ? when own transfer data is "1" and data on sda line is "0", al = "1" is set regarding that arbitration is lost. ? when start condition is attempted during other master s are using bus, al = "1" is set regarding that arbitration is lost. ? when other masters' start condition is detected be fore starting condition occurs though unused bus is confirmed and mss = "1" is set, al = "1" is set regarding that arbitration is lost. when al bit is set to "1", status becomes mss = "0" and trx = "0" that state becomes slave reception mode. when arbitration is lost (the right to use th e bus is lost.), master discontinues drive of sda. however, drive of scl is not discontinued until 1 byte of transmission ends and the interrupt is cleared. i2c_sdax i2c_sclx sda input sda output sda input sda output macro a macro b since input and output are matched, right to use bus is acquired. since input and output are unmatched, right to use bus is lost. figure 19-6 arbitration
19-26 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface 19.7.6. acknowledge/negative acknowledge 9th bit of data shows acknowledge (ack)/negative acknowledge (nack), status of "0" is acknowledge and "1" is negative acknowledge. the reception side transmits acknowle dge/negative acknowledge to transmission side, and they are stored to lrb bit at data reception. if acknowledge is not received from master rece ption side at slave transmission (when negative acknowledge is received), the state becomes trx = "0 " and mode becomes slave reception mode. as a result, master is able to generate stop condition when slave opens scl. i2c_sdax i2c_sclx sda output macro a (transmission) macro b (reception) reception side returns ack/nack to transmission side transmission side opens bus for ack/nack output on reception side 1 23456789 ack ack scl output sda output scl output master generates clock figure 19-7 acknowledge/negative acknowledge
19-27 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface 19.7.7. bus error when following conditions meet, state is judged as bus error and this module stops. a. detection of basic rule violation on i 2 c bus in data transmission (including ack bit) b. detection of stop condition at master c. detection of basic rule violation on i 2 c bus at bus idle i2c_sdax 1 start 3 i2c_sclx 2 d7 d5 d6 i2c_sdax is changed in i2c_sclx = h during data transfer which leads to bus error figure 19-8 bus error
19-28 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface 19.7.8. initialization start slave address setting clock frequency setting macro enable setting interrupt setting end i2cxadr (offset + 0ch): write i2cxccr (offset + 08h): write cs[4:0]: write en: 1 write i2cxbcr (offset + 04h): write ber: 0 write beie: 1 write int: 0 write inte: 1 write figure 19-9 i 2 c initialization
19-29 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface 19.7.9. one byte transfer from master to slave start start condition address data transfer acknowledge interrupt data transfer acknowledge interrupt stop condition end master i2cxdar (offset + 10h): write mss: 1 write bb set and trx set lrb reset slave int set and trx set dar: write int: 0 write int set lrb reset int set and trx reset ack: 1 write int: 0 write mss: 0 write int reset bb reset and trx reset a as set bb set and trx reset int set i2cxdar (offset + 10h): read int: 0 write bb reset and trx reset aas reset figure 19-10 1 byte transfer example from master to slave
19-30 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface 19.7.10. one byte transfer from slave to master start start condition address data transfer acknowledge interrupt data transfer negative acknowledge interrupt stop condition end master i2cxdar (offset + 10h): write mss: 1 write bb set and trx set lrb reset slave int set and trx reset ack: 0 write int: 0 write int set i2cxdar: read lrb set and trx set int set and trx set i2cxdar(offset+10h): write int: 0 write mss: 0 write int reset bb reset and trx reset a as set bb set and trx reset int set int: 0 write bb reset and trx reset aas reset figure 19-11 1 byte transfer example from slave to master
19-31 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface 19.7.11. recover from bus error start error flag release clock frequency setting macro enable setting interrupt setting end i2cxbcr (offset + 04h): write ber: 0 write beie: 1 write i2cxccr (offset + 08h): write cs[4:0]: write en: 1 write i2cxbcr (offset + 04h): write ber: 0 write beie: 1 write int: 0 write inte: 1 write figure 19-12 setting example for recovering from bus error
19-32 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface 19.7.12. interrupt process and wait request operation to master device when int flag of i2cxbcr register is "h" (during this module engenders interrupt and cpu proceeds interrupt operation), "l" is output to scl line. while slave side sets "l" to scl line, master side is unable to generate the next transfer so that slave side puts wait on master side. 19.8. notice system clock and fscl of this module supply system clock to this module within the followi ng range. the communicati on with system clock of 18mhz or more needs i2cxcsr setting. ? master operation: 14mhz ~ 41.5mhz set i2cxccr not to exceed the following limits on fs cl. if it exceeds the upper bound of each mode, normal transfer is not proceeded since it is timing violation on i 2 c bus. standard: 100khz high-speed: 400khz ? slave operation: 14mhz ~ 41.5mhz ? register access: 14mhz ~ 41.5mhz 10 bit slave address this module does not support 10 bit slave address; therefore, do not specify slave address from 78h to 7bh for the module. when wrong address is specifi ed, acknowledge is return ed at receiving 1byte; however, normal transf er is not proceeded. competition of scc, mss, and int bit simultaneous writing of scc, mss, and int bits cause s competition of start and stop conditions at the next byte transfer. the priority of this case is as follows. 1. occurrence of the next byte transfer and stop condition when "0" is written to int bit and mss bit simulta neously, mss bit is prioritized and stop condition occurs. 2. occurrence of the next byte transfer and start condition when "0" is written to int bit and "1" is written to scc bit simultaneously, scc bit is prioritized and start condition occurs. 3. occurrence of start condition and stop condition writing "1" to scc bit and "0" to mss bit simultaneously is prohibited. serial transfer clock setting when rising edge delay of scl line is large or clock is expanded at the slave device, the value may be smaller than the setting value (calcula ted value) since overhead occurs.
19-33 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface restrictions in global call address transmission at using multi master when this module is used at multi master, it is prohibited that other masters send global call address at the same time of this module and it loses arbitration at the 2nd byte or later. following usage does not fall under this restriction. ? this module is used in the single master environment. ? this module is used in the multi mater environment; however, it does not send general call address. ? this module is used in the multi master environm ent; however, other modules do not use general call address transmission. ? although this module is used in the multi master environment and other masters send general call address simultaneously with this module, it does not lose arbitration at the 2nd byte or later.* *: because the larger transmission data causes arbitr ation lost, the data of the 2nd byte or later must always be smaller than the value of other masters' data.
19-34 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface 19.9. flow charts the example of the flow chart when communicating with this module is shown below. initialization set own address (i2cxadr<=0mmm_mmmmb) send or receive? tra ns mit receive set clock frequency ( i2cxbc fr<=0000_ffffb) set interrupt ( i2cx bcr<=0100_0110b) end clear error set error clear ( i2cx bcr<=0100_0000b) set clock & en ( i2cx ccr<=0h1c_ccccb) set interrupt ( i2cx bcr<=0100_0110b) end master communication set counterpart address & send (i2cxdar<=ssss_sss0b) set counterpart address & receive (i2cxdar<=ssss_sss1b) send start condition & address (i2cxbcr<=0101_0110b) end set expand c s ( i2cxecsr <=00cc_ccccb) set clock & en ( i2cx ccr<=0h1c_ccccb) set en clear (i2cxccr<=0h0c_ccccb) read i2cxbsr read i2cxbcr clear error wa i t (10*pclk) arbitration lost? (!i2cxbcr.mss or i2cxbsr.al) (1) wai t (100*pclk) (0) bus free? ( i2cx bsr.bb) (1) (0) read i2cx bsr * a bus may be hung up in a sda fixed low. when a bus is hung up, return processing or system reset is necessary.
19-35 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface interrupt processing master in communication? (i2cxbcr.mss) read i2cxbcr read i2cxbsr bus error? (i2cxbcr.ber) (1) (0) (1) (0) send master data 3 send slave data 2 send or receive? (bsr.trx) (1) receive master data 5 receive slave data 4 send or receive? (i2cxbsr.trx) (1) (0) (0) arbitration lost? (i2cxbsr.al) (0) (1) slave? (i2cxbsr.aas or .gca) (1) (0) * macro external judgment flag is necessary since bcr and mss are cleared due to bus error detection. master in communication? y es no temporarily clear en setting (i2cxccr<=0h0c_ccccb) clear error wai t (100*pclk) clear error master re-communication end end wa i t (10*pclk) wai t (10*pclk) * a function stopped period is necessary until the bus stabilizes at ?h? to communicate again. * wait from the clear of interrupt until actual interrupt negation. send slave data 2 set data for transmission (i2cxdar<=data for transmission) data sent? y es no clear interrupt & sen d (i2cxbcr<=0100_0010b) receive slave data 3 read received data (received data<= i2cx dar) address? ( i2cx bsr.fbt) (0) (1) clear interrupt & ack in the next reception ( i2cx bcr<=0100_1010b) receive completed in the next data reception? no y es clear interrupt & nack in the next reception ( i2cx bcr<=0100_0010b) end * judges whether it is general address call or normal slave address using gca and ass. wai t (10*pclk) * slave transmit side cannot request termination of the communication. * wait from the clear of interrupt until actual interrupt negation.
19-36 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface master data transmission 4 set transmission data (i2cxdar<=transmission data) transmission completed? no y es clear interrupt & sen d (i2cxbcr<=0101_0110b) master data reception 5 read received data (received data<=i2cxdar) master nack (i2cxbsr.lrb) (0) (1) clear interrupt & ack in the next reception (i2cxbcr<=0101_1110b) reception completed in the next data reception? no ye s clear interrupt & nack in the next reception (i2cxbcr<=0101_0110b) slave nack (i2cxbsr.lrb) (0) (1) end address? (i2cxbsr.ftb) (0) (1) wait (10*pclk) * master can terminate the communication regardless of ack/nack. * wait from the clear of interrupt until actual interrupt negation. transmission completed or start condition continue 6 clear interrupt & stop condition (bcr<=0100_0110b) transmission completed or start condition continue? transmision completed start condition continue read bsr bus free (bsr.bb) (0) (1) end transmission completed or start condition continue 6 wa it (100*pclk) end send or receive ? transmit receive set counterpart address & send (dar<=ssss_sss0b) set counterpart address & receive(dar<=ssss_sss1b) send start condition continue & address (bcr<=0111_0110b) wa it (10*pclk)
19-37 MB86R01 lsi product specifications fujitsu semiconductor confidential i 2 c bus interface return processing of hung up in a sda fixed low start of return processing of hung up exist other master device no ye s continue sdas=?0? and scls=?1? no read bcr2 ye s end *other master device are using a bus end *fail(give up) sdal=?1? *success wait 1bit sdal=?0? sdas=?1? and scls=?1? no read bcr2 ye s end (forced bus error) sdas=?1? no scll=?1? wa it lo w wi dt h scll=?0? wait 1/2 high width wait 1/2 high width read bcr2 ninth no ye s ye s (forced clock output)
20-1 MB86R01 lsi product specifications fujitsu semiconductor confidential serial peripheral interface (spi) 20. serial peripheral interface (spi) this chapter describes function and operat ion of serial imperial interface (spi.) 20.1. outline spi is a serial interface to perform synchronous communication. 20.2. feature spi has following features: ? serial synchronous transmission of the full duplex ? transfer format is settable to programmable a) bit rate b) data length (1 ~ 32 bit) c) clock polarity d) phase ? supporting 2 types of slave select signals ? only 1 slave is connectable example of spi connection figure 20-1 shows spi connection example. spi master (MB86R01) spi slave spi_sck spi_do spi_di spi_ss figure 20-1 example of spi connection note: when slave is active, spi_di pin may be floating.
20-2 MB86R01 lsi product specifications fujitsu semiconductor confidential serial peripheral interface (spi) 20.3. block diagram figure 20-2 shows block diagram of spi. apb clk (bus clock) spi crg state machine control logic 32bit shift register data register apb bus 32bit/41.5mh z sirq spi_sck spi_do spi_di spi_ss irc figure 20-2 block diagram of spi 20.4. supply clock apb clock is supplied to spi. refer to "5. cloc k reset generator (crg)" for frequency setting and control specification of the clock.
20-3 MB86R01 lsi product specifications fujitsu semiconductor confidential serial peripheral interface (spi) 20.5. transition state figure 20-3 shows spi transition state chart. reset sleep senb = 0 sbsy = 0 serr = 0 error senb = 1 sbsy = 0 serr = 1 setup senb = 1 sbsy = 0 serr = 0 busy senb = 1 sbsy = 1 serr = 0 hresetn = 1 spe = 1 spe = 0 write data normal end error spe = 0 figure 20-3 spi state transition chart detail of each state shown in figure 20-3 is as follows. spi moves to reset state with hardware reset (hresetn = 0) from all conditions (broken line in the chart.) spi state description sleep (sleep) initial state of spi. clock is not supplied except to state machine. while setup or transition from error state, internal logic is initialized except certain part. setup (setup) stand-by state of communication between master and slave. spi changes state in the following cases. ? spe bit of spi slave control register (spiscr) is set to "1" in the sleep state ? communication completes properly in the busy state received data should be read in the setup state. busy (busy) communicating state with spi slave. writing spi data register (spidr) in the setup state moves to this state; in that time, transmission/reception of the data are performed simultaneously. when 1 bit is output to spi_do pin, 1 bit is input from spi_di pin. set sirq at the normal termination of the communication. error (error) performing prohibited regi ster access in the busy state moves to this state. clearing spe bit of spi slave control register (spiscr) returns to sleep (sleep) state.
20-4 MB86R01 lsi product specifications fujitsu semiconductor confidential serial peripheral interface (spi) 20.6. register this section describes spi register. 20.6.1. register list spi is controlled by the register shown in table 20-1. t able 20-1 spi register list address base offset register abbreviation description + 00 h spi control register spicr this sets common setting with spi + 04 h spi slave control register spiscr this sets spi slave fixed setting + 08 h spi data register spidr this writes and reads data to be transmitted/received to spi slave fff4_0000 h + 0c h spi status register spisr this maintains spi state description format of register following format is used for description of register?s each bit in " 20.6.2 spi control register (spicr)" to " 20.6.5 spi status register (spisr)". address base address + offset bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r/w initial value bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r/w initial value meaning of item and sign address address (base address + offset address) of the register bit bit number of the register name bit field name of the register r/w attribution of read/write of each bit field ? r0:read value is always "0" ? r1: read value is always "1" ? w0: write value is always "0", and write access of "1" is ignored ? w1: write value is always "1", and write access of "0" is ignored ? r: read ? w: write initial value each bit field?s value after reset ? 0: value is "0" ? 1: value is "1" ? x: value is undefined
20-5 MB86R01 lsi product specifications fujitsu semiconductor confidential serial peripheral interface (spi) 20.6.2. spi control register (spicr) this register is to set common setting of spi. spicr setting should be carried out in the sleep or setup states, and do not write to this register in the busy state. each bit of spicr is not cleared even the state is changed to sleep by spe = 0 of spi slave control register (spiscr.) address fff4_0000 h + 00 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? spl0 r/w r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r/w r/w r/w initial value x x x x x x x x x x x x x 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ? ? ? ? ? cdv2 cdv1 cdv0 ? ? ? ? ? ? cpol cpha r/w r0 r0 r0 r0 r0 r/w r/w r/w r0 r0 r0 r0 r0 r0 r/w r/w initial value x x x x x 0 0 0 x x x x x x 0 0 (note) this register should be accessed in 32 bit unit. bit field no. name description 31-19 ? unused bits. the write access is ignored. the read value of these bits is always "0". 18-17 ? unused bits. the write access is ignored. 16 spl0 polarity of spi_ss pin (slave selection pin) is specified. 0 active-high (initial value) 1 active-low 15-11 ? unused bits. the write access is ignored. the read value of these bits is always "0". 10-8 cdv2-0 frequency dividing ratio of serial clock (sck) to bus clock (pclk) is specified. cdv2 cdv1 cdv0 frequency dividing ratio 0 0 0 pclk 1/2 (initial value) 0 0 1 pclk 1/4 0 1 0 pclk 1/8 0 1 1 pclk 1/16 1 0 0 pclk 1/32 1 0 1 pclk 1/64 1 1 0 pclk 1/128 1 1 1 pclk 1/256 7-2 ? unused bits. the write access is ignored. the read value of these bits is always "0". 1 cpol polarity of serial clock (sck) is selected. 0 positive pulse (initial value) 1 negative pulse 0 cpha timing of i/o serial data (di/do) and serial clock (s ck) are specified. timing at cpha = 0 or 1, and cpol = 0 is shown in figure 20-4 t iming at cpha = 0 or 1, and cpol = 1 is shown in figure 20-5
20-6 MB86R01 lsi product specifications fujitsu semiconductor confidential serial peripheral interface (spi) spi_sck (cpha=0) spi_sck (cpha=1) spi_di shift in spi_do shift out bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 figure 20-4 timing of serial data and serial clock (at cpol = 0) spi_sck (cpha=0) spi_sck (cpha=1) spi_di shift in spi_do shift out bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 figure 20-5 timing of serial data and serial clock (at cpol = 1)
20-7 MB86R01 lsi product specifications fujitsu semiconductor confidential serial peripheral interface (spi) 20.6.3. spi slave control register (spiscr) this register maintains unique setting of spi slave. all bits are cleared by moving state to sleep. set this register at sleep or setup state. address fff4_0000 h + 04 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ? ? ? spe ? ? ? drvs ? ? ? ? stl3 stl2 stl1 stl0 r/w r0 r0 r0 r/w r0 r0 r0 r/w r0 r0 r0 r0 r/w r/w r/w r/w initial value x x x 0 x x x 0 x x x x 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ? ? ? dln4 dln3 dln2 dln1 dln0 ? ? smod saut ? ? ssp1 ssp0 r/w r0 r0 r0 r/w r/w r/w r/w r/w r0 r0 r/w r/w r0 r0 r/w r/w initial value x x x 0 0 0 0 0 x x 0 0 x x 0 0 (note) this register should be accessed in 32 bit unit. bit field no. name description 31-29 ? unused bits. the write access is ignored. the read value of these bits is always "0". 28 spe spi's clock supply is controlled. 0 clock supply to internal logic stops except certain part (initial value) 1 clock is supplied to all the circuits write "1" to operate spi. its state changes from sleep to setup by setting spe bit. it changes to sleep by clear; at the same time, internal logic is reset except certain part. 27-25 ? unused bits. the write access is ignored. the read value of these bits is always "0". 24 drvs transfer order of serial data is specified. 0 msb --> lsb (initial value) 1 lsb --> msb 27-25 ? unused bits. the write access is ignored. the read value of these bits is always "0". 19-16 stl3-0 strobe width is specifi ed at pulse mode selection (smod = 1) in the range of sck 1 ~ 16 cycles. 0000 sck 1cycle (initial value) 0001 sck 2cycles : : 1110 sck 15cycles 1111 sck 16cycles 15-13 ? unused bits. the write access is ignored. the read value of these bits is always "0".
20-8 MB86R01 lsi product specifications fujitsu semiconductor confidential serial peripheral interface (spi) bit field no. name description 12-8 dln4-0 data length of transmission/reception serial data is specified in the range of 1 ~ 32 bit. 00000 1 bit (initial value) 00001 2 bit 00010 3 bit : : 11101 30 bit 11110 31 bit 11111 32 bit 7-6 ? unused bits. the write access is ignored. the read value of these bits is always "0". 5 smod operation mode of slave selection is specifie d. slave selection signal is output to spi_ss pin. 0 selection mode (always active while communication) (initial value) 1 pulse mode (after communicating, this becomes active) 4 saut operation timing of slave selection is specified according to the combination of smod bit. 0 slave selection synchronizes with ssp b it's setting value regardless of smod (see figure 20-6) (initial value) 1 1sck of wait is added from spi data re gister (spidr) writing to serial data transmission, and from the last data tr ansmission to asserting/negating salve selection (see figure 20-7) 3-2 ? unused bits. the write access is ignored. the read value of these bits is always "0". 1-0 ssp1-0 slave selection pin to be active is specified. 00 slave selection pin become s non-active (initial value) 01 spi_ss pin becomes active 10 reserved (setting prohibited) 11 reserved (setting prohibited)
20-9 MB86R01 lsi product specifications fujitsu semiconductor confidential serial peripheral interface (spi) first last sirq spi_ss spi_do ssp assert spidr write ssp ne g ate spisr read busy figure 20-6 timing chart of spi_ss pin (at saut = 0) first last sirq spi_ss smod=0 dpi_do spidr write busy 1sck 1sck sirq spi_ss smod=1 stl busy figure 20-7 timing chart of spi_ss pin (at saut = 1)
20-10 MB86R01 lsi product specifications fujitsu semiconductor confidential serial peripheral interface (spi) 20.6.4. spi data register (spidr) this register is used to write/read data to be transmitted to/received from spi slave. address fff4_0000 h + 08 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (note) this register should be accessed in 32 bit unit. do not operate this register in the busy state. bit field no. name description 31-0 d31-0 transmission/reception da ta to spi slave is stored. spidr is reset at moving to the sleep state. writing to this register in the setup state starts transmission/reception of the data length specified in dln[4:0] bit of spi slave control register (spiscr), and lsb is fixed regardless of the data length.
20-11 MB86R01 lsi product specifications fujitsu semiconductor confidential serial peripheral interface (spi) 20.6.5. spi status register (spisr) this register is to maintain spi state, and it is not able to be written. address fff4_0000 h + 0c h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ? ? ? ? ? ? ? ? sirq ? ? ? ? serr sbsy senb r/w r0 r0 r0 r0 r0 r0 r0 r0 r r r r r r r r initial value x x x x x x x x 0 x x x x 0 0 0 (note) this register should be accessed in 32 bit unit bit field no. name description 31-8 ? unused bits. the write access is ignored. the read value of these bits is always "0". 7 sirq proper completion of communication between master slaves is indicated. 0 it is under the communication or stand-by (initial value) 1 communication is completed sirq pin outputs this bit. it is cleared by reading spisr register. figure 20-6 and figure 20-7 show timing chart. 6-3 ? unused bits. the write access is ignored. the read value of these bits is always "0". 2 serr operation error is indicated. 0 normal operation is in process (initial value) 1 prohibited operation occurs clear spe bit of spi slave control register (spiscr) serr bit is set to "1" by processing other ope rations than reading spicr, spiscr, and spisr in the busy state. moreover, this bit is cleared by changing state to sleep with clearing spe bit of spiscr. 1 sbsy communication with spi slave is in process. 0 it is standing-by (initial value) 1 it is communicating sbsy is set to "1" by writing to spi data register (spidr.) do not clear spe bit of spiscr in the busy state. this bit is released by either of followings: ? sirq bit setting ? serr bit setting 0 senb spi circuit is active. 0 clock supply to internal logic is stop ex cept to certain part (initial value) 1 clock is supplied to all the circuits
20-12 MB86R01 lsi product specifications fujitsu semiconductor confidential serial peripheral interface (spi) 20.7. setup procedure flow figure 20-8 shows spi setup procedure flow. start state = sleep yes no start state = sleep state = error ? write spiscr (spe set/clear) write spicr state = setup ? data communication n o yes yes no state = busy ? read spisr (sirq clear) write spidr (txrx start) state = setup ? n o yes data communication start delete received data? read spidr continue data communication without setting change? data communication end yes n o yes n o figure 20-8 spi setup flow chart
21-1 MB86R01 lsi product specifications fujitsu semiconductor confidential can interface (can) 21. can interface (can) this chapter describes can interface. refer following website for can module specification. url: http://www.semiconductors.bosch. de/en/20/can/ products/ccan.asp 21.1. outline MB86R01 equips 2 ports of can interface which is in compliance with can protocol version 2.0 part a and b. 21.2. block diagram figure 21-1 shows block diagram of can. apb slave apb bus 0ch i/o port MB86R01 can core can_tx0 and can_rx0 apb slave i/o port can core can_tx1 and can_rx1 1ch irc figure 21-1 block diagram of can
21-2 MB86R01 lsi product specifications fujitsu semiconductor confidential can interface (can) 21.3. supply clock apb clock is supplied to can interface. refer to "5 . clock reset generator (crg)" for frequency setting and control specification of the clock. 21.4. register register mapping of this lsi is in byte address (8 bit.) 16 bit length of register is allocated by word address unit (32 bit) for local address of can; thus valid data in 32 bit width data of apb bus is 16 bit. table 21-1 can 0ch register map register address can 0ch register address apb bus data[31:0] fff5_4000h 00h {0x0000, 16 bit data} fff5_4004h 02h {0x0000, 16 bit data} fff5_4008h 04h {0x0000, 16 bit data} table 21-2 can 1ch register map register address can 1ch register address apb bus data [31:0] fff5_5000h 00h {0x0000, 16 bit data} fff5_5004h 02h {0x0000, 16 bit data} fff5_5008h 04h {0x0000, 16 bit data}
22-1 fujitsu semiconductor confidential medialb interface MB86R01 lsi product specifications 22. medialb interface this chapter describes medialb interface. license needs to be acquired for its specification which is provided by smsc. please contact smsc and requ est the following document: ? os62400 medialb device interface macro advanced product data sheet 22.1. outline MB86R01 equips 1 port of medialb interface which enables using up to 16 channels. 22.2. block diagram figure 22-1 shows block diagram of medialb. ahb slave ahb bus medialb i/o port MB86R01 ahb master medialb macro media local bus medialb controller most network irc mlb_cint mlb_sint mlb_dint ccnt figure 22-1 block diagram of medialb
22-2 fujitsu semiconductor confidential medialb interface MB86R01 lsi product specifications 22.3. supply clock ahb clock is supplied to medialb interface. refer to "5. clock reset generator (crg)" for frequency setting and control specification of the clock. 22.4. register this lsi's register is mapped in word address (32 bit); however, local address of the medialb macro is described by byte address (8 bit.) table 22-1 local address de scription in medialb macro register address medialb local address fff6_0000h 00h fff6_0004h 01h fff6_0008h 02h
23-1 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23. usb host controller this chapter describes function and register spec of usb host controller. see the following website for operation as well. host controller specification with ohci standard 1.0a version url: http://h18000.www1.hp.com/productinfo/development/openhci.html host controller specification with ehci standard 1.0 version url: http://www.intel.com/technology/usb/ehcispec.htm version of this chapter is managed unity with the one of lsi product specifications. 23.1. outline this host controller is in compliance with the usb standard 2.0 editions. it equips phy for 1 port, host controller complying with the ehci standard 1.0 edition, and host controller complying with the ohci standard 1.0a version which corresponds to three modes, hs/fs/ls. 23.2. spec limitation usb host controller has following limitations. 1. out transfer (host => device) for 512 byte or more of packet size is unsupported. limitation is applied to isochronous and interrupt transfers of 512 byte or more (up to 1024 byte) according to the standard. in transfer (device => host) is not limited. 2. buffer depth setting value is fixed to 512 byte. 3. buffer threshold setting value is limited to "buffer size - 2 or less".
23-2 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.3. feature host controller's function list is shown bellow. table 23-1 usb host controller function list item function high-speed transfer in compliance with host co ntroller with the ehci standard 1.0 edition split transfer is supported. full-speed/low-speed transfer in compliance with ho st controller with the ohci standard 1.0a edition number of port 1 debug port n/a port indicator not supported. companion controller host controller w ith the ohci standard 1.0a edition x 1 power control function of port supported. extended capability pointer not supported. asynchronous park mode programma ble (park value is settable.) 64bit addressing not supported. others, original function ? micro frame length is settable. ? packetbuffer threshold is settable. ? packetbuffer size is settable. ? nak reload correction function can be turned on/off. ? sof interval is adjustable by register setting.
23-3 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.4. block diagram figure 23-1 block diagram of usb host controller packet buffer 128 x 32bit list processor sof generation ehci operational registers root hub usb 2.0 ehci host controller usb 1.1 ohci host controller phycnt utmi+ host link ahb i/f ahb bus irc usb2.0 host module host link/function link mux usb phy usb2.0 function module utmi usb MB86R01
23-4 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.5. supply clock ahb clock is supplied to usb host controller. refer to "5. clock reset generator (crg)" for frequency setting and control specification of the ahb clock. 23.6. register this section describes usb host controller register. 23.6.1. register list usb host controller's register is classified into following 3 groups. 1. ehci operational registers 2. ohci operational registers 3. other registers each group has following registers. table 23-2 ehci operational registers address register description fff8_0000 h hccapbase capability register fff8_0004 h hcsparams structural parameter register fff8_0008 h hccparams capability parameter register fff8_000c h reserved access prohibited fff8_0010 h usbcmd usb command register fff8_0014 h usbsts usb status register fff8_0018 h usbintr usb interrupt enable register fff8_001c h frindex usb frame index register fff8_0020 h ctrldssegment 4g segm ent selector register fff8_0024 h periodiclistbase periodic frame list base address register fff8_0028 h asynclistaddr asynchronous list address register fff8_002c h - fff8_004f h reserved access prohibited fff8_0050 h configflag configured flag register fff8_0054 h portsc_1 port status/control register fff8_0058 h - fff8_008f h reserved access prohibited fff8_0090 h insnreg00 programmable micro frame base value register fff8_0094 h insnreg01 programmable packet bu ffer out/in threshold register fff8_0098 h insnreg02 programmable packet buffer depth register fff8_009c h insnreg03 break memory transfer register fff8_00a0 h insnreg04 debug register fff8_00a4 h insnreg05 utmi control status registers fff8_00a8 h - fff8_0fff h reserved access prohibited
23-5 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller table 23-3 ohci operational registers address register description fff8_1000 h hcrevision revision register fff8_1004 h hccontrol control register fff8_1008 h hccommandstatus comma nd/status register fff8_100c h hcinterruptstatus interrupt status register fff8_1010 h hcinterruptenable interrupt enable register fff8_1014 h hcinterruptdisable inte rrupt disable register fff8_1018 h hchcca hcca register fff8_101c h hcperiodcurrented peri od current ed register fff8_1020 h hccontrolheaded control head ed register fff8_1024 h hccontrolcurrented control current ed register fff8_1028 h hcbulkheaded bulk head ed register fff8_102c h hcbulkcurrented bulk current ed register fff8_1030 h hcdonehead done head register fff8_1034 h hcfminterval frame interval register fff8_1038 h hcfmremaining frame remaining register fff8_103c h hcfmnumber frame number register fff8_1040 h hcperiodicstart peri odic start register fff8_1044 h hclsthreshold ls threshold register fff8_1048 h hcrhdescriptora root h ub descriptor a register fff8_104c h hcrhdescriptorb root h ub descriptor b register fff8_1050 h hcrhstatus root hub status register fff8_1054 h hcrhportstatus[1] root hub port status/control register 1 fff8_1058 h - fff8_1fff h reserved access prohibited table 23-4 other registers address register description fff8_2000 h linkmodesetting link m ode setting register fff8_2004 h phymodesetting1 phy mode setting 1 register fff8_2008 h phymodesetting2 phy mode setting 2 register fff8_1058 h - fff8_1fff h reserved access prohibited
23-6 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.2. ehci operational registers 23.6.2.1. hccapbase (capability register) address fff8_0000 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name hciversion r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro initial value 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) caplength r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro initial value 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 bit filed no. name description 31-16 hciversion ehci revision number is indicated. 31-24: major revision number 23-16: minor revision number 15-8 (reserved) reserved filed. 7-0 caplength offset of operationa l register space is indicated.
23-7 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.2.2. hcsparams (structural parameter register) address fff8_0004 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) debug port number (reserved) *1 r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name n_cc n_pcc *2 (reserved) ppc n_ports r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro initial value 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 *1: p_indicator *2: port routing rule bit filed no. name description 31-24 (reserved) reserved filed. 23-20 debug port number in this module, "0 h " is read indicating debug port is not equipped. 19-17 (reserved) reserved filed. 16 p_indicator port indicator in this module, "0" is read indicating port indicator control is not supported. 0b: unsupported 1b: supported 15-12 n_cc number of companion controller number of usb1.1 host controller equipped is indicated. in this module, "1 h " is read indicating one usb1.1 host controller is installed. 11-8 n_pcc number of ports per companion controller number of port supported by usb1.1 host controller is indicated. when this field is read, "2 h " is read indicating usb1.1 ho st controller supports 2 ports. however, this module actually supports only 1 port1. 7 port routing rule how all ports are allocated in usb1.1 host controller is indicated. 0b: from the smaller port number 1b: according to the first n_ports element in the hcsp-portroute array in this module, "0" is read indicating port number is allocated fro m the smaller number. 6-5 (reserved) reserved filed. 4 ppc port power control whether host controller is able to control power is indicated. 0b: disabled 1b: enabled in this module, "1" is read indicating ho st controller is able to control power. 3-0 n_ports number of accessible port registers in the operational register space is indicated. when this field is read, "2 h " is read indicating there are 2 accessible port registers. however, this module actually supports only 1 port1.
23-8 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.2.3. hccparams (capability parameter register) address fff8_0008 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name eecp *1 *2 *3 *4 *5 r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro initial value 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 *1: isochronous scheduling threshold *2: (reserved) *3: asynchronous sche dule park capability *4: programmable frame list flag *5: 64bit addressing capability bit field no. name description 31-16 (reserved) reserved filed. 15-8 eecp ehci extended capabilities pointer offset in the pci configuration space is indicated. 7-4 isochronous scheduling threshold "0" in bit[7] indicates available micro frame fo r the software to update isochronous schedule. 3 (reserved) reserved filed. 2 asynchronous schedule park capability in this module, "1" is read indicating host cont roller supports park feature to hi-speed queue head of the asynchronous schedule. 0b: unsupported 1b: supported 1 programmable frame list flag in this module, "1" is read indicating size can be specified with frame list size in the usbcmd register. 0b: fixed to 1024 1b: size is specified with frame list size in the usbcmd register 0 64bit addressing capability in this module, "0" is read indicating it is 32bit addre ss data structure. 0b: data structure using 32bit address pointer 1b: data structure using 64bit address pointer
23-9 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.2.4. usbcmd (usb command register) address fff8_0010 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) interrupt threshold control r/w ro ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) *1 *2 *3 *4 *5 *6 *7 *8 *9 rs r/w ro ro ro ro r/w ro r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 *1: asynchronous schedule park mode enable *2: (reserved) *3: asynchronous schedule park mode count *4: light host controller reset *5: interrupt on async advance doorbell *6: asynchronous schedule enable *7: periodic schedule enable *8: frame list size *9: hcreset bit field no. name description 31-24 (reserved) reserved filed. 23-16 interrupt threshold control frame interval for host controller to issue interrupt is set. 00 h : (reserved) 01 h : 1 micro frame 02 h : 2 micro frame 04 h : 4 micro frame 08 h : 8 micro frame (= 1ms) 10 h : 16 micro frame (= 2ms) 20 h : 32 micro frame (= 4ms) 40 h : 64 micro frame (= 8ms) writing other values is prohibited. 15-12 (reserved) reserved filed. 11 asynchronous schedule park mode enable in this module, asynchronous park capability bit of the hccparams register is "1"; therefore, this is readable/writable bit. 0b: park mode is disabled 1b: park mode is enabled 10 (reserved) reserved filed. 9-8 asynchronous schedule park mode count in this module, asynchronous park capability bit of the hccparams register is "1"; therefore, this is readable/writable bit. valid values are 1 h - 3 h . writing 0 h is prohibited. 7 light host controller reset ehci host controller is reset without affecting to port stat e and ohci host controller. [at reading] 0b: reset of light host controller is completed 1b: light host controller is in reset 6 interrupt on async advance doorbell this bit sets to issue interrupt notifying the host controller to go to the next asynchronous schedule. after setting "1" to interrupt of interrupt on as ync advance bit of the usbsts register, host controller sets "0" in this bit. when the asynchronous schedule is disabled , "1" cannot be written in this bit. 5 asynchronous schedule enable this bit controls whether host controller s hould skip the asynchronous schedule process. 0b: asynchronous schedule process is skipped. 1b: asynchronous schedule is processed. 4 periodic schedule enable this bit controls whether host controller should skip the periodic schedule process. 0b: periodic schedule process is skipped 1b: periodic schedule is processed.
23-10 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller bit field no. name description 3-2 frame list size in this module, programmable frame list flag of the hccparams register is "1"; therefore, this is readable/writable bit. this bit specifies frame list size. 00b: 1024 elements (4096bytes) 01b: 512 elements (2048bytes) 10b: 256 elements (1024bytes) 11b: reserved 1 hcreset host controller reset when "1" is written in this bit, host controller st arts initiali zation of pipeline, timer, counter, state machine, and others. in addition, initial value is se t to the port register and the port state machine. then ownership of the port returns to usb1.1 host controller. after the reset, this bit is set to "0" by the controller. when hchalted bit of the usbsts register is "0", do not write "1" in this bit. 0 rs run/stop when "1" is written to this bit, host controll er executes the schedule. when "0" is written, the controller stops the process after completing current transaction. 0b: stop 1b: run if hchalted bit of the usbsts register is "0", do not write "1" in this bit.
23-11 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.2.5. usbsts (usb status register) address fff8_0014 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name *1 *2 *3 *4 (reserved) *5 *6 *7 *8 *9 *10 r/w ro ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w initial value 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 *1: asynchronous schedule status *2: periodic schedule status *3: reclamation *4: hchalted *5: interrupt on async advance *6: host system error *7: frame list rollover *8: port change detect *9: usberrint *10: usbint bit field no. name description 31-16 (reserved) reserved field. 15 asynchronous schedule status current state of the asynchr onous schedule is indicated. 0b: asynchronous schedule is disabled 1b: asynchronous schedule is enabled 14 periodic schedule status current state of the period ic schedule is indicated. 0b: periodic schedule is disabled 1b: periodic schedule is enabled 13 reclamation whether the asynchronous schedule is empty is indicated. 12 hchalted when rs (run/stop) bit of the usbcmd register is "1", this bit becomes "0". in this case, host controller stops the process after completing curr ent transaction and sets "1" to this bit. 11-6 (reserved) reserved field. 5 interrupt on async advance when "1" is written to async advance doorbell bit of the usbcmd register, host controller issues interrupt at the next asynchronous schedule process. this bit is cleared by writing "1". 4 host system error when host controller accesses to memory and error response occurs, or "1" is set to sys_interrupt bit of the ccnt module's usb setting register (cusb), th is bit is set to "1". in this case, "0" is set to the rs (run/stop) bit of the usbcmd register to prevent host controller from executing the schedule. this bit is cleared by writing "1". 3 frame list rollover when frame list index value returns to "0" from the max. value, host controller sets "1" to this bit. this bit is cleared by writing "1". 2 port change detect host controller sets "1" to this bit in the following conditions: ? when the port, whose port owner bit is set to "0" is changed from "0" to "1" ? when force port resume bit value is changed from "0" to "1" as a result of detecting j-k transition in the suspending port ? when ehci releases the port by writing "1" to port owner bit this bit is cleared by writing "1". 1 usberrint usb error interrupt when usb transfer ends due to error, host controller sets this bit to "1". if the td on which the error interrupt occurred also had its ioc bit set, both this bit and usbint bit are set to "1". this bit is cleared by writing "1".
23-12 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller bit field no. name description 0 usbint when usb transfer is completed and transfer descriptor where ioc bit is set retires, host controller sets this bit to "1". the host controller also sets this bit to "1" when short packet is detected. this bit is cleared by writing "1".
23-13 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.2.6. usbintr (usb interrupt enable register) address fff8_0018 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) *1 *2 *3 *4 *5 *6 r/w ro ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 *1: interrupt on async advance enable *2: host system error enable *3: frame list rollover enable *4: port change interrupt enable *5: usb error interrupt enable *6: usb interrupt enable bit field no. name description 31-6 (reserved) reserved field. 5 interrupt on async advance enable interrupt by interrupt on async advance bi t of the usbsts register is enabled. 0b: disabled 1b: enabled 4 host system error enable interrupt by host system error bit of the usbsts register is enabled. 0b: disabled 1b: enabled 3 frame list rollover enable interrupt by frame list rollover bit of the usbsts register is enabled. 0b: disabled 1b: enabled 2 port change interrupt enable interrupt by port change detect bit of the usbsts register is enabled. 0b: disabled 1b: enabled 1 usb error interrupt enable interrupt by usberrint bit of the usbsts register is enabled. 0b: disabled 1b: enabled 0 usb interrupt enable interrupt by usbint bit of the usbsts register is enabled. 0b: disabled 1b: enabled
23-14 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.2.7. frindex (usb frame index register) address fff8_001c h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) frame index r/w ro ro r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-14 (reserved) reserved field. 13-0 frame index value of the register is incremented at the end of each frame. bits [n:3] are used for current frame list number. n value is determined in accordance with frame list size value of the usbcmd register as shown below. frame list size number elements n 00b (1024) 12 01b (512) 11 10b (256) 10 11b reserved - 23.6.2.8. ctrldssegment (4g segment selector register) address fff8_0020 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ctrldssegment r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ctrldssegment r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-0 ctrldssegment control data structure segment register this register corresponds to the address b it [63:32] of the ehci data structure. in this module, 64bit addressing capability bit of the hccparams register is "0". therefore, this regi ster is not usable.
23-15 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.2.9. periodiclistbase (periodic fram e list base address register) address fff8_0024 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name base address r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name base address (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-12 base address base addre ss of periodic frame list in the memory area is set. 11-0 (reserved) reserved field. be sure to write "0" to these bits. the reading value always becomes "0". 23.6.2.10. asynclistaddr (asynchronous list address register) address fff8_0028 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name link pointer low r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name link pointer low (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-5 link pointer low queue head address of the asyn chronous schedule to be executed next is stored. 4-0 (reserved) reserved field.
23-16 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.2.11. configflag (configured flag register) address fff8_0050 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r?w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) cf r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-1 (reserved) reserved field. be sure to write "0" to these bits. the reading value always becomes "0". 0 cf configure flag this bit controls the port routing. set this bit to "1" at the end of the host controller setting. 0b: the ohci controller owns the port routing control. 1b: the ehci controller owns the port routing control.
23-17 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.2.12. portsc_1 (port status/control register 1) address fff8_0054 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) *1 *2 *3 port test control r/w ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name *4 *5 pp line status *6 *7 *8 *9 *10 *11 *12 *13 *14 *15 r/w r/w r/w r/w r/w ro ro ro r/w r/w r/w r/w ro r/w r/w r/w ro initial value 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 *1: wkoc_e *2: wkdscnnt_e *3: wkcnnt_e *4: port indicator control *5: port owner *6: (reserved) *7: port reset *8: suspend *9: force port resume *10: over-current change *11: over-current active *12: port enable/disable change *13: port enable/disable *14: connect status change *15: current connect status bit field no. name description 31-23 (reserved) reserved field. 22 wkoc_e wake on over-current enable setting "1" to this bit enables to use over-current status as wake-up event. when port power is "0", this field is "0". 21 wkdscnnt_e wake on disconnect enable setting "1" to this bit enables to us e disconnect event as wake-up event. when port power is "0", this field is "0". 20 wkcnnt_e wake on connect enable setting "1" to this bit enables to use connect event as wake-up event. when port power is "0", this field is "0". 19-16 port test control this field specifies whether port mode should be test mode. when this field is "0000b", the port mode is not test mode. when this field is other than the value, the port operates as the test mode shown below. bits test mode 0000b test mode not enable 0001b test j_state 0010b test k_state 0011b test se0_nak 0100b test packet 0101b test force_enable 0110b ? 1111b (reserved)
23-18 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller bit field no. name description 15-14 port indicator control in this module, p_indicator bit of the hcparams register is "0". writing "1" to these bits is prohibited. bits meaning 00b port indicators are off 01b amber 10b green 11b undefined when port power is "0", this field is "0". 13 port owner host controller w ith port ownership is indicated. when cf (configure flag) bit of the configflag register changes from "0" to "1", the value of this bit becomes "0". when cf bit is "0", this bit becomes "1". 0b: ehci host controller owns the port 1b: ohci host controller owns the port 12 pp port power the bit function depends on ppc (port power control) bit value of the hcsparams register. ppc pp operation 0b 1b host controller is unable to control port power. 1b 1b/0b host controller is ab le to control port power. pp=0b: port power control is off. pp=1b: port power control is on. when power of the port is off, the port does not function. moreover, the event such as device connection/disconnection is not notified. if over-current is detected , this bit becomes "0". 11-10 line status state of usb po rt's signal wire is indicated. bits[11:10] usb state 00b se0 10b j_state 01b k_state 11b undefined when port power is "0", valu e of this field is undefined. 9 (reserved) reserved field. 8 port reset when software writes a "1" to this bit, the bus reset sequence is started. software writes a "0" to this bit to terminate the bus reset sequence. 0b: not reset 1b: reset when port power is "0", this field is "0". 7 suspend the port state is defined as follows by the port enable/disable bit and suspend bit of this register. bits port enable/disable suspend port state 0 x disable 1 0 enable 1 1 suspend writing "0" to suspend bit is invalid. when port power is "0", this field is "0". 6 force port resume writing "1" when this bit is "0" starts resume. on the other hand, writing "0" when this bit is "1" terminates resume. 0b: no resume (k-state) 1b: resume detection/driven on port when port power is "0", this field is "0". 5 over-current change when over-current active bit value changes, this bit is set to "1". this bit is cleared to "0" by writing "1".
23-19 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller bit field no. name description 4 over-current active whether the state is over-current is indicated. 0b: not over-current status 1b: over-current status 3 port enable/disable change this bit is set to "1" only when port status is disabled at eof2 point due to a port error. when this bit is set, port enable/disable bit is cleared to "0". this bit is cleared to "0" by writing "1". when port power is "0", this field is "0". 2 port enable/disable port can only be enabled by host controller. soft ware cannot enable a port by writing "1" to this bit. only when the device connected with reset sequ ence is recognized as high-speed, host controller sets this bit to "1". 0b: port is disabled. 1b: port is enabled. when port power is "0", this field is "0". 1 connect status change current connect status changed at port is indicated. this bit is cleared to "0" by writing "1". 0b: no change in current connect status 1b: change in current connect status when port power is "0", this field is "0". 0 current connect status device connection state on the port is indicated. 0b: device is not connected. 1b: device is connected.
23-20 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.2.13. insnreg00 (programmable micr oframe base v alue register) address fff8_0090 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w - - - - - - - - - - - - - - - - initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) - - r/w - - - - - - - - - - - - - - - - initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-14 (reserved) reserved field. 13-1 - the length of 1 micro frame is set. example) when "1d4c h " is set to this field, 1 micro frame becomes 125 s. 0 - this register function is enabled. 0b: disabled 1b: enabled 23.6.2.14. insnreg01 (programmable p acket buffer out/in threshold register) address fff8_0094 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name out threshold r/w - - - - - - - - - - - - - - - - initial value 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name in threshold r/w - - - - - - - - - - - - - - - - initial value 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 bit field no. name description 31-16 out threshold host controller starts transfer to usb wh en number of byte of the data set to this field is gotten from the system memory. unit: dword min. value: 16 bytes (0004 h ) max. value: [insnreg02 setting value - 2] example) when 80 h is set to insnreg02, the maximum valu e that can be set to this field is 7e h . 15-0 in threshold host controller starts transfer to memory when number of byte of the data set to this field is stored to packet buffer. unit: dword min. value: 16 bytes (0004 h ) max. value: [insnreg02 setting value - 2] example) when 80 h is set to insnreg02, the maximum valu e that can be set to this field is 7e h .
23-21 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller insnreg01/insnreg02 register setting value and host controller operation 1. bulk transfer out transfer insnreg01[31:16] insnreg02 host controller operation 0080 h 80 h this setting is not able to be used. 0040 h 80 h host controller starts transfer to usb when the data of 256bytes is gotten from the memory. in transfer insnreg01[15:0] insnreg02 host controller operation 0080 h 80 h this setting is not able to be used. 0040 h 80 h host controller starts transfer to memory when the data of 256bytes is stored to packet buffer. 0004 h 80 h host controller starts transfer to memory when the data of 16bytes is stored to packet buffer. 2. isochronous/interrupt transfer out transfer insnreg01[31:16] insnreg02 host controller operation 0080 h 80 h this setting is not able to be used. 0040 h 80 h host controller starts transfer to usb when the data of 256bytes is gotten from the memory. in transfer insnreg01[15:0] insnreg02 host controller operation 0080 h 80 h this setting is not able to be used. 0040 h 80 h host controller starts transfer to memory when the data of 256bytes is stored to packet buffer. 3. control transfer out transfer insnreg01[31:16] insnreg02 host controller operation 0080 h 80 h this setting is not able to be used. 0004 h 80 h host controller starts transfer to usb when the data of 16bytes is gotten from the memory. in transfer insnreg01[15:0] insnreg02 host controller operation 0080 h 80 h this setting is not able to be used. 0004 h 80 h host controller starts transfer to memory when the data of 16bytes is stored to packet buffer. transfer timing from packet buffer of short packet that is less than the threshold set to insnreg01 ? out transfer: after the short packet data is writte n from the memory on the ahb bus to the packet buffer, transferring from the packet buffer to usb is started. ? in transfer: after the short packet data is written fr om usb to the packet buffer, transferring from the packet buffer to the memory on the ahb bus is started.
23-22 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.2.15. insnreg02 (programmable packet buffer depth register) address fff8_0098 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w - - - - - - - - - - - - - - - - initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) insnreg02 r/w - - - - - - - - - - - - - - - - initial value 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 bit field no. name description 31-12 (reserved) reserved field. 11-0 insnreg02 packet buffer dept h is defined in dword unit.
23-23 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.2.16. insnreg03 (time-available offset register) address fff8_009c h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w - - - - - - - - - - - - - - - - initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) time-available offset *1 r/w - - - - - - - - - - - - - - - - initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 *1: (reserved) bit field no. name description 31-9 (reserved) reserved field. 8-1 time-available offset reserved field. writing the value other than "00 h " is prohibited. 0 (reserved) reserved field. writing "1" is prohibited. 23.6.2.17. insnreg04 (debug register) address fff8_00a0 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w - - - - - - - - - - - - - - - - initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) - - - - - r/w - - - - - - - - - - - - - - - - initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-5 (reserved) reserved field. 4 - nak reload fix is controlled. 0b: nak reload fix is enabled. 1b: nak reload fix is disabled. 3 (reserved) reserved field. 2 - measurement function at the port enumeration time when this function is enabled, the device chirp detection time becomes about 3.5 s and the width of host chirp becomes about 400ns. if device chirp continues about 19 s or more when this function is valid, host controller is not detected as device chirp. therefore, se t the duration of device chirp within 19 s. 0b: measurement f unction is invalid. (normal operation) 1b: measurement f unction is valid. (simulation etc.) 1 - writing control function of hccparams register 0b: writing is not possible. 1b: writing is possible. 0 - writing control function of hcsparams register 0b: writing is not possible. 1b: writing is possible.
23-24 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.2.18. insnreg05 (utmi control status register) address fff8_00a4 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) *1 *1 r/w - - - - - - - - - - - - - - ro r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) *1 (reserved) (reserved) r/w r/w r/w r/w r/w r/w r/ w r/w r/w ro ro ro ro ro ro ro ro initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 *1: (reserved) bit field no. name description 31-18 (reserved) reserved field. 17 (reserved) reserved field. 16-13 (reserved) reserved field. 12 (reserved) reserved field. 11-8 (reserved) reserved field. 7-0 (reserved) reserved field.
23-25 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.3. ohci operational registers 23.6.3.1. hcrevision (revision register) address fff8_1000 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) rev r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 bit field no. name description 31-8 (reserved) reserved field. 7-0 rev version of ohci specification is indicated.
23-26 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.3.2. hccontrol (control register) this register sets an operating mode of host controller. bits other than remotewakeupconnected are rewritable only by host controller driver. address fff8_1004 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w - - - - - - - - - - - - - - - - initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) rwe rwc ir hcfs ble cle ie ple cbsr r/w - - - - - r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-11 (reserved) reserved field. be sure to write "0" to these bits. the reading value always becomes "0". 10 rwe remotewakeupenable when host controller supports the remote wake up signal, this bit enables its operation. 9 rwc remotewakeupconnected this bit indicates whether host controlle r supports the remote wake up signal. 8 ir interruptrouting this bit determines the route of generating an interrupt. 0b: normal interrupt route 1b: smi (system manage ment interrupt) route 7-6 hcfs hostcontrollerfunctionalstate this field indicates the operation status of host controller. when the resume signal from downport is detected, host controller change s the value of this field from usbsuspend to usbresume. hcfs operation status 00b usbreset 01b usbresume 10b usboperational 11b usbsuspend 5 ble bulklistenable writing "1" to this bit enables bulk list processing. 4 cle controllistenable writing "1" to this bit enables control list processing. 3 ie isochronousenable even if periodiclistenable is "1" when this bi t is cleared, the isochronous list processing is disabled. in this case, in terrupt ed is processed. host controller checks this bit be fore processing isochronous ed. 2 ple periodiclistenable writing "1" to this bit enables periodic (in terrupt and isochronous) list processing. host controller checks this bit before the periodic transfer of the frame. 1-0 cbsr controlbulkserviceratio the number of times of the service of each bu lk endpoint to control endpoint is specified. n-1 indicates the service of n times to control endpoint. example) "00b"=1 control endpoint, "11b"=4 control endpoint
23-27 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.3.3. hccommandstatus (command/status register) this register reflects the state of host controller. mo reover, this register is used to receive the command from which host controller is issued by host controller driver. address fff8_1008 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) soc r/w - - - - - - - - - - - - - - r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) ocr blf clf hcr r/w - - - - - - - - - - - - r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-18 (reserved) reserved field. be sure to write "0" to these bits. the reading value always becomes "0". 17-16 soc schedulingoverruncount this field is incremented every time scheduleoverrun bit of hcinterruptstatus register is set. when the count value reaches to "11b", it returns to "00b". 15-4 (reserved) reserved field. be sure to write "0" to these bits. the reading value always becomes "0". 3 ocr ownershipchangerequest when "1" is written to this bit by software, host controller sets ownershipchange of hcinterruptstatus register. this bit is cleared by software. 2 blf bulklistfilled this bit is set to "1" by software or host controlle r, and indicates that active ed exists in the bulk list. when this bit is "1", host controller starts the pr ocessing of the head of bulk list, and clears this bit to "0" every time it is processed. 1 clf controllistfilled this bit is set to "1" by software or host cont roller, and indicates that active ed exists in the control list. when this bit is "1", host controller starts the processing of the head of control list, and clears this bit to "0" every time it is processed. 0 hcr hostcontrollerreset when "1" is written to this bit, host controller starts software reset. when the reset process is completed, this bit is cleared to "0".
23-28 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.3.4. hcinterruptstatus (interrupt status register) this register indicates the state of the hardware in terrupt factor. to generate the hardware interrupt, masterinterruptenable bit of hcinterruptenable register is set. host controller can set each bit of this register, but it can not be cleared. host controller driver can clear the bit by writing "1" to each bit of this register, but it can not be set. address fff8_100c h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name *1 oc (reserved) r/w - r/w - - - - - - - - - - - - - - initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) rhsc fno ue rd sf wdh so r/w - - - - - - - - - r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 *1: (reserved) bit field no. name description 31 (reserved) reserved field. always write "0" to this bit. the reading value always becomes "0". 30 oc ownershipchange when ownershipchangerequest bit of the hccommandstat us register is set, this bit is set to "1". 20-7 (reserved) reserved field. always write "0" to this bit. the reading value always becomes "0". 6 rhsc roothubstatuschange when hcrhstatus or hcrhportstatus register contents are changed, this bit is set to "1". 5 fno framenumberoverflow when bit 15 of framenumber is changed, this bit is set to "1". 4 ue unrecoverableerror when host controller accesses to memory and an error response occurs, or sys_interrupt bit of the ccnt module's usb setting register (cus b) is set, this bit is set to "1". 3 rd resumedetected when this module detects the resume signal in the port, this bit is set to "1". 2 sf startofframe when the frame management block generates the even t signal of "start of frame", this bit is set to "1". 1 wdh writebackdonehead when writing the content of the hcdonehead register to the hccadonehead is completed, this bit is set to "1". 0 so schedulingoverrun when listprocessor detects the generation of scheduleoverrun, this bit is set to "1".
23-29 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.3.5. hcinterruptenable (interrupt enable register) this register controls the generation of the hardware interrupt. the hardware interrupt becomes valid by setting the interrupt factor, and setting the mie bit. address fff8_1010 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name mie oc (reserved) r/w r/w r/w - - - - - - - - - - - - - - initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) rhsc fno ue rd sf wdh so r/w - - - - - - - - - r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31 mie masterinterruptenable this bit enables the interrupt of the entire ohci. writing "1" to this bit enables the interrupt due to other bits of this register. 30 oc ownershipchangeenable 0b: invalid 1b: interrupt due to "ownership change" is enabled. 29-7 (reserved) reserved field. 6 rhsc roothubstatuschangeenable 0b: invalid 1b: interrupt due to "root hub status change" is enabled. 5 fno framenumberoverflowenable 0b: invalid 1b: interrupt due to "frame nu mber overflow" is enabled. 4 ue unrecoverableerrorenable 0b: invalid 1b: interrupt due to "unrecoverableerror" is enabled. 3 rd resumedetectedenable 0b: invalid 1b: interrupt due to "resume detected" is enabled. 2 sf startofframeenable 0b: invalid 1b: interrupt due to "start of frame" is enabled. 1 wdh writebackdoneheadenable 0b: invalid 1b: interrupt due to "writeba ck done head" is enabled. 0 so schedulingoverrunenable 0b: invalid 1b: interrupt due to "schedule overrun" is enabled.
23-30 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.3.6. hcinterruptdisable (interrupt disable register) this register is coupled with the hcinterruptenable register. writing "1" to a bit in this register clears the corresp onding bit in the hcinterruptenable register, whereas writing "0" to a bit in this register leaves the corresp onding bit in the hcinterruptenable register unchanged. when this register is read, the value of the hcinterruptenable register is returned. address fff8_1014 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name mie oc (reserved) r/w r/w r/w - - - - - - - - - - - - - - initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) rhsc fno ue rd sf wdh so r/w - - - - - - - - - r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31 mie this bit disables the interrupt of the entire ohci. writing "1" to this bit disables the interrupt due to other bits of this register. 30 oc 0b: invalid 1b: interrupt due to "ownership change" is disabled. 29-7 (reserved) reserved field. 6 rhsc 0b: invalid 1b: interrupt due to "root hub status change" is disabled. 5 fno 0b: invalid 1b: interrupt due to "frame nu mber overflow" is disabled. 4 ue 0b: invalid 1b: interrupt due to "unrecove rable error" is disabled. 3 rd 0b: invalid 1b: interrupt due to "resum e detected" is disabled. 2 sf 0b: invalid 1b: interrupt due to "start of frame" is disabled. 1 wdh 0b: invalid 1b: interrupt due to "writeba ck done head" is disabled. 0 so 0b: invalid 1b: interrupt due to "sche dule overrun" is disabled.
23-31 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.3.7. hchcca (hcca register) this register indicates the phys ical address of the host contro ller communication area. the minimum alignment is 256 bytes; therefore, low order 7-0 bits are fixed to 00 h . for host controller communication area, refer to chapter 4 of "openhci specifications". address fff8_1018 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name hcca r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hcca (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-8 hcca hcca this is a pointer to the hcca base address. 7-0 (reserved) reserved field. 23.6.3.8. hcperiodcurrented (periodic current ed register) this register indicates the physical address of the current isochronous or interrupt endpoint descriptor. address fff8_101c h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pced r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pced (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w - - - - initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-4 pced periodcurrented this is a pointer to the current periodic list ed. 3-0 (reserved) reserved field. be sure to write "0" to these bits. the reading value always becomes "0".
23-32 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.3.9. hccontrolheaded (control head ed register) this register indicates the physical address of the first endpoint descriptor of the control list. address fff8_1020 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ched r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ched (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w - - - - initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-4 ched controlheaded this is a pointer to th e control list head ed. 3-0 (reserved) reserved field. be sure to write "0" to these bits. the reading value always becomes "0". 23.6.3.10. hccontrolcurrented (control current ed register) this register indicates the physi cal address of the current endpoint descriptor of the control list. address fff8_1024 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cced r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cced (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w - - - - initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-4 cced controlcurented this is a pointer to the current control list ed. only when bulklistenable of the hccontrol register is "0", writing to these bits is available. when controllistenable of the hccontrol regist er is "1", these bits become a read only. 3-0 (reserved) reserved field. be sure to write "0" to these bits. the reading value always becomes "0".
23-33 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.3.11. hcbulkheaded (bulk head ed register) this register indicates the physical address of the first endpoint descriptor of the bulk list. address fff8_1028 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bhed r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bhed (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w - - - - initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-4 bhed hcbulkheaded this is a pointer to the bulk list head ed. 3-0 (reserved) reserved field. be sure to write "0" to these bits. the reading value always becomes "0". 23.6.3.12. hcbulkcurrented (bulk current ed register) this register indicates the physi cal address of the current endpoint descriptor of the bulk list. address fff8_102c h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bced r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bced (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w - - - - initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-4 bced bulkcurrented this is a pointer to th e current bulk list ed. only when bulklistenable of the hccontrol register is "0", writing to these bits is available. when controllistenable of the hccontrol regist er is "1", these bits become a read only. 3-0 (resereved) reserved field. be sure to write "0" to these bits. the reading value always becomes "0".
23-34 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.3.13. hcdonehead (done head register) this register indicates the physical address of the last completed transfer descriptor that was added to the done queue. address fff8_1030 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dh r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dh (reserved) r/w r r r r r r r r r r r r - - - - initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-4 dh donehead this is a pointer to the done head ed. 3-0 (reserved) reserved field. be sure to write "0" to these bits. the reading value always becomes "0". 23.6.3.14. hcfminterval (frame interval register) bit13-0 of this register indicates the bit time interv al in a frame, (i.e., between two consecutive sofs), and bit30-16 indicates the maximum pack et size that can be transferred without causing schedule overrun. address fff8_1034 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name fit fsmps r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) fi r/w - - r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 1 0 1 1 1 0 1 1 0 1 1 1 1 1 bit field no. name description 31 fit frameintervaltoggle host controller driver toggles this bit value when ever it loads a new value into the frameinterval field. 30-16 fsmps fslargestdatapacket this field specifies a value which is loaded into the la rgest data packet count er at the beginning of each frame. 15-14 (reserved) reserved field. be sure to write "0" to these bits. the reading value always becomes "0". 13-0 fi this field specifies the length of the frame. frame length = bit time - 1 example) when one frame is 12, 000 bit time, 11,999 is specified.
23-35 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.3.15. hcfmremaining (frame remaining register) this register is a 14bit down counter indicating the bit time remaining in the current frame. address fff8_1038 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name frt (reserved) r/w r - - - - - - - - - - - - - - - initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) fr r/w - - r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31 frt frameremainingtoggle this bit is loaded from the frameintervaltoggle bit value of hcfminterval register whenever frameremaining field reaches "0". 30-14 (reserved) reserved field. be sure to write "0" to these bits. the reading value always becomes "0". 13-0 fr frameremaining when this module is usbo prerational state, this 14bit field is decremented at 12mhz clock cycle. when the count value reaches "0" (end of the frame), the frameinterva l field value of the hcfminterval register is loaded into this field. when entering the usboprerational state, the frameinterval field value is loaded into this field. 23.6.3.16. hcfmnumber (frame number register) this register is a 16bit counter. it provides a timing reference among events happening in the host controller and the host controller driver. address fff8_103c h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w - - - - - - - - - - - - - - - - initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fn r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-16 (reserved) reserved field. be sure to write "0" to these bits. the reading value always becomes "0". 15-0 fn framenumber this field is 16bit increment counter which is in cremented whenever the frameinterval field value of the hcfminterval register is loaded into the frameremaining field of the hcfmremaining register. it will be rolled over to 0 h after ffff h .
23-36 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.3.17. hcperiodicstart (periodic start register) a 14bit value of this register determines the earliest time that host controller should start the processing of periodic list. address fff8_1040 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w - - - - - - - - - - - - - - - - initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) ps r/w - - r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-14 (reserved) reserved field. be sure to write "0" to these bits. the reading value always becomes "0". 13-0 ps this field does the time setting that host cont roller starts the processing of periodic list in the frame. 23.6.3.18. hclsthreshold (ls threshold register) an 11bit value of this register is used to determine whether host controller transmits an 8bytes ls packet before eof. address fff8_1044 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w - - - - - - - - - - - - - - - - initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) lst r/w - - - r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 bit field no. name description 31-12 (reserved) reserved field. be sure to write "0" to these bits. the reading value always becomes "0". 11-0 lst lsthreshold this field sets the value to determine whether host controller starts low speed transaction in a current frame. the transaction is started only if the frameremaining field value of the hcfmremaining register is larger than this field value.
23-37 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.3.19. hcrhdescriptora (root h ub descriptor a register) this register is the first register of two describing the setting of the root hub. address fff8_1048 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name potpgt (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w - - - - - - - - initial value 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) nocp ocpm dt nps psm ndp r/w - - - r/w r/w r r/w r/w r r r r r r r r initial value 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 bit field no. name description 31-24 potpgt powerontopowergoodtime this field specifies the duration host controller driver has to wait before accessing a powered-on port of the root hub. the unit of time is 2ms. 23-13 (reserved) reserved field. be sure to write "0" to these bits. the reading value always becomes "0". 12 nocp noovercurrentprotection this bit specifies how the over-current stat us for the root hub port is reported. 0b: over-current status is reported. 1b: over-current status is not reported. 11 ocpm overcurrentprotectionmode this bit is valid only if the no overcurrentprotection bit is "0". 0b: over-current status is repor ted collectively for all ports. 1b: over-current status is reported per port. 10 dt devicetype this bit specifies that the r oot hub is not a compound device. the root hub is not permitted to be a compound device. this bit is fixed to "0". 9 nps nopowerswitching this bit specifies whether root hub port's pow er switching is supported or port is always powered. 0b: port's power can be switched. 1b: port is always powered on. 8 psm powerswitchingmode this bit specifies the method of root hub port' s power switching. this bit is valid only if the nopowerswitching bit is "0". 0b: all ports are powered at the same time. 1b: each port is powered individually. 7-0 ndp numberdownstreamports this field indicates th e number of downstream ports of root hub. read value of this field is 2 h (indicating 2 ports are supported); however, this module actually supports only port1.
23-38 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.3.20. hcrhdescriptorb (root h ub descriptor b register) this register is the second register of two describing the setting of the root hub. address fff8_104c h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ppcm r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-16 ppcm portpowercontrolmask this field indicates if a port is aff ected by a global power control command. when nopowerswitching bit is "0" and powerswitc hingmode bit is "1", this field becomes valid. 0b: port is affected by a global power control command. 1b: port is not affected by a global power control command. correspondence of bit in the port and the field is as follows. bit port 16 reserved 17 port1 18 this bit indicates port2; how ever, this module actually supports only port1. 19-31 not supported by this module. be sure to write "0" to these bits. the reading value always becomes "0". 15-0 dr deviceremovable whether the device connected to the root hub port is detachable is specified. 0b: device is detachable. 1b: device is not detachable. correspondence of bit in the port and the field is as follows. bit port 0 reserved 1 port1 2-15 not supported by this module. be sure to write "0" to these bits. the reading value always becomes "0".
23-39 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.3.21. hcrhstatus (root hub status register) this register is divided into two parts. the lower 16bit represents the hub status field and the upper 16bit represents the hub status change field. address fff8_1050 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name crwe (reserved) ocic lpsc r/w w - - - - - - - - - - - - - r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name drwe (reserved) oci lps r/w r/w - - - - - - - - - - - - - r r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31 crwe (write) clearremotewakeupenable 0b: invalid. 1b: deviceremotewakeupenable bit is cleared to "0". 30-18 (reserved) reserved field. be sure to write "0" to these bits. the reading value always becomes "0". 17 ocic overcurrentindicatorchange this bit is set to "1" when overcu rrentidicator bit value is changed. 0b: invalid. 1b: overcurrentidicator bit is cleared to "0". 16 lpsc (read) localpowerstatuschange unsupported. the reading value always becomes "0". (write) setglobalpower 0b: invalid. 1b: setglobalpower command is issued. 15 drwe (read) deviceremotewakeupenable this bit enables a connectstatuscha nge bit as a remotewakeup event. 0b: disable 1b: enable (write) setremotewakeupenable 0b: invalid. 1b: setremotewakeupenable bit is set to "1". 14-2 (reserved) reserved field. be sure to write "0" to these bits. the reading value always becomes "0". 1 oci overcurrentindicator this bit reflects the app_prt_ovrcur bit value of ccnt module's usb set register (cusb). when noovercurrentprotection bit and overcurren tprotectionmode bit of the hcrhdescriptora register are "0", this field becomes valid. 0b: over-current condition is not detected. (app_prt_ovrcur = 0) 1b: over-current condition is detected. (app_prt_ovrcur = 1) 0 lps (read) localpowerstatus unsupported. the reading value always becomes "0". (write) clearglobalpower 0b: invalid. 1b: clearglobalpower command to the port is issued.
23-40 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.3.22. hcrhportstatus[1] (root hub port s tatus/control register 1) this register is used for the control and the event notification of each port. hcrhportstatus[1] is for port1. the lower 16bit is used to reflect the port status, wh ereas the upper 16bit reflects the status change bits. some status bits are implemented with special write behavior. refer to the de scription of each bit for details. if a transaction is in progress when rewriting port status, the resulting port status change must be postponed until the transaction completes. address fff8_1054 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) prsc ocic pssc pesc csc r/w - - - - - - - - - - - r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) lsda pps (reserved) prs poci pss pes ccs r/w - - - - - - r/w r/w - - - r/w r/w r r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-21 (reserved) reserved field. be sure to write "0" to these bits. the reading value always becomes "0". 20 prsc portresetstatuschange this bit indicates the end of the port reset signal. (read) 0b: port reset is not completed. 1b: port reset is completed. (write) 0b: invalid. 1b: this bit is cleared to "0". 19 ocic portovercurrentindicatorchange when portovercurrentindicator bit is changed, this bit is set to "1". (read) 0b: no change in portovercurrentindicator. 1b: portovercurrentindicator has changed. (write) 0b: invalid. 1b: this bit is cleared to "0". 18 pssc portsuspendstatuschange this bit indicates completion of the resume processing to the port. when resetstatuschange bit is set to "1", this bit is cleared to "0". (read) 0b: resume is not completed. 1b: resume is completed. (write) 0b: invalid. 1b: this bit is cleared to "0".
23-41 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller bit field no. name description 17 pesc portenablestatuschange when portenablestatus bit is cha nged, this bit is set to "1". if portenablestatus bit is changed by software, this bit is not set. (read) 0b: no change in portenablestatus. 1b: change in portenablestatus. (write) 0b: invalid. 1b: this bit is cleared to "0". 16 csc connectstatuschange when the event of connection or disconnection is generated, this bit is set to "1". (read) 0b: no change in connectstatuschange 1b: change in connectstatuschange (write) 0b: invalid. 1b: this bit is cleared to "0". 15-10 (reserved) reserved field. be sure to write "0" to these bits. the reading value always becomes "0". 9 lsda (read) lowspeeddeviceattached this bit indicates the speed of the device attached to the port. this bit is valid only if the currentconnectstatus bit is "0". 0b: full speed device is attached. 1b: low speed device is attached. (write) clearportpower 0b: invalid. 1b: portpowerstatus bit is cleared to "0". 8 pps (read) portpowerstatus this bit indicates the port?s power status , regardless of the power switching mode. when the over-current status (portovercurrentindica tor=1) is detected, this bit is cleared to "0". 0b: port power is off. 1b: port power is on. (note) when nopowerswitching bi t is set, the reading value of this bit is always "1". (write) setportpower 0b: invalid. 1b: portpowerstatus bit is set to "1". 7-5 (reserved) reserved field. be sure to write "0" to these bits. the reading value always becomes "0". 4 prs (read) portresetstatus when reset is completed, this bit is cleared to "0". when currentconnectstatus is "0", this bit is not set. 0b: port reset signal is not active. 1b: port reset signal is active. (write) setportreset 0b: invalid. 1b: portresetstatus bit is set to "1".
23-42 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller bit field no. name description 3 poci (read) portovercurrentindicator this bit reports over-current condition per port. this bit reflects the app_prt_ovrcur bit value of the ccnt module's usb set register (cusb). when noovercurrentprotection bit of the hcrhdescriptora register is "0" and overcurrentprotectionmode bit of the hcrhdescri ptora register is "1", this field becomes valid. 0b: no over-current condition. (app_prt_ovrcur = 0) 1b: over-current condition is detected. (app_prt_ovrcur = 1) (write) clearsuspendstatus 0b: invalid. 1b: resume processing is executed to the port. 2 pss (read) portsuspendstatus this bit is not able to be set, if currentconnectstatus bit is "0". this bit is cleared to "0", when the port reset is completed or when the host controller is placed in the usbresume state. 0b: port is not suspended. 1b: port is suspended. (write) setportsuspend if currentconnectstatus bit is "0", portsuspendsta tus bit cannot be set by writing in this bit; instead it sets conn ectstatuschange bit. 0b: invalid. 1b: portsuspendstatus bit is set to"1". 1 pes (read) portenablestatus this bit is not able to be set, if currentconnectstatus bit is "0". this bit is set to "1", when the port reset or the port suspend is completed. 0b: port is disabled. 1b: port is enabled. (write) setportenable if currentconnectstatus bit is "0", portenablestatus bit cannot be set by writing in this bit; instead it sets conn ectstatuschange bit. 0b: invalid. 1b: portenablestatus bit is set to "1". 0 ccs (read) currentconnectstatus 0b: device is not c onnected to this port at this time. 1b: device is connected to this port at this time. (note) when deviceremovable bit of hcrhdescri ptorb register is "1", this bit always becomes "1". (write) clearportenable 0b: invalid. 1b: portenablestatus bit is cleared to "0".
23-43 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.4. other registers 23.6.4.1. linkmodesetting (link mode setting register) address fff8_2000 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name lma lmb lmc lmd r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name lme lmf lmg lmh lmi r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 bit field no. name description 31-28 lma this field is fixed to "0000b". do not change the value of this field. 27-24 lmb this field is fixed to "0000b". do not change the value of this field. 23-22 lmc this field is fixed to "01b". do not change the value of this field. 21-16 lmd this field is fixed to "20 h ". do not change the value of this field. 15-10 lme this field is fixed to "20 h ". do not change the value of this field. 9 lmf this field is fixed to "0". do not change the valu e of this field. 8 lmg this field is fixed to "1". do not change the valu e of this field. 7-2 lmh this field is fixed to "00 h ". do not change the value of this field. 1-0 lmi this field is fixed to "00b". do not change the value of this field.
23-44 fujitsu semiconductor confidential MB86R01 lsi product specifications usb host controller 23.6.4.2. phymodesetting1 (phy mode setting 1 register) address fff8_2004 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) pm1a pm1b pm1c pm1d (reserved) pm1e r/w r r r r r/w r/w r/w r/w r r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pm1f pm1g pm1h pm1i pm1j r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 0 0 0 1 1 0 0 0 0 0 1 1 0 1 1 *1: rpdmen *2: rpdpen bit field no. name description 31-28 (reserved) reserved field. 27 pm1a this field is fixed to "0". do not change the valu e of this field. 26 pm1b this field is fixed to "0". do not change the valu e of this field. 25 pm1c this field is fixed to "1". do not change the valu e of this field. 24 pm1d this field is fixed to "1". do not change the valu e of this field. 23-22 (reserved) reserved field. 21-16 pm1e this field is fixed to "0d h ". do not change the value of this field. 15-12 pm1f this field is fixed to "1000b". do not change the value of this field. 11-8 pm1g this field is fixed to "1100b". do not change the value of this field. 7-4 pm1h this field is fixed to "0001b". do not change the value of this field. 3-1 pm1i this field is fixed to "101b". do not change the value of this field. 0 pm1j this field is fixed to "1". do not change the valu e of this field. 23.6.4.3. phymodesetting2 (phy m ode setting 2 register) address fff8_2008 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) pm2a r/w r r r r r r r r r r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name *1 pm2b (reserved) pm2c r/w r r/w r/w r/w r/w r/w r/w r/w r r r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 *1: (reserved) bit field no. name description 31-18 (reserved) reserved field. 17-16 pm2a this field is fixed to "11b". do not change the value of this field. 15 (reserved) reserved field. 14-8 pm2b this field is fixed to "00 h ". do not change the value of this field. 7-3 (reserved) reserved field. 2-0 pm2c this field is fixed to "000b". do not change the value of this field.
24-1 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24. usb function controller this chapter describes function and operation of usb function controller. version of this chapter is managed unity with the one of lsi product specifications. 24.1. outline the function controller, compliant with "high speed/full speed" of the usb standard edition 2.0 equips phy with 1 port. 24.2. feature ? usb 2.0 hs/fs protocol handling basic usb communication protocol is processed to reduce load on the application (software) side. notes: following items should be handled on the application side.(*) 1- class/vendor request processes 2- set_descriptor/get_descriptor/synch_frame processes of the standard request (*): this command is handled as transfer to endpoint 0. after reading and analyzing command data from fifo, the system should be ready for required data transfer at data stage. ? built-in exclusive dmac (corresponding to ep1 and ep2) ? fifo for endpoint table 24-1 endpoint composition endpoint type in/out buffer size access method out 64 bytes 1 ep0 control in 64 bytes 1 cpu ep1 bulk in/out 512 bytes 2 ep2 bulk in/out 512 bytes 2 cpu or dmac ep3 interrupt in 64 bytes 1 cpu
24-2 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.3. block diagram figure 24-1 block diagram of usb function controller usb protocol engine endpoint control ram ram ram function link ahb i/f function link dmac m odule utmi utmi+ usb ahb bus irc usb 2.0 function module host link/function link mux usb 2.0 host module usb phy
24-3 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.4. supply clock ahb clock is supplied to usb function controller. refer to "5. clock reset generator (crg)" for frequency setting and control specification of the clock. 24.5. register 24.5.1. register list table 24-2 register list address register description fff7_0000 h ufcpac access method control from cpu fff7_0004 h ufdvc usb control fff7_0008 h ufdvs usb status display fff7_000c h ufepic interrupt control per each endpoint fff7_0010 h ufepis interrupt status display per each endpoint fff7_0014 h ufepdc dma transfer control of endpoint fff7_0018 h ufepds dma transfer status display of endpoint fff7_001c h uftstamp time stamp register fff7_0020 h ufeptcsel selection regi ster of transfer count fff7_0024 h ufeptc1 byte count register for endpoint1 fff7_0028 h ufeptc2 byte count register for endpoint2 fff7_0070 h ufeprs0 data reception amount display of endpoint0 fff7_0078 h ufeprs1 data reception amount display of endpoint1 fff7_0080 h ufeprs2 data reception amount display of endpoint2 fff7_0088 h ufeprs3 data reception amount display of endpoint3 fff7_00f0 h ufcuscnt operation setting register fff7_00f4 h ufcalb timeout adjustment register fff7_00f8 h ufeplpbk loop back test register fff7_00fc h ufintfaltnum register for setting number of alternate in use unsupported fff7_0100 h ufepc0 control register for endpoint0 fff7_0104 h ufeps0 status register for endpoint0 fff7_0108 h ufepc1 control register for endpoint1 fff7_010c h ufeps1 status register for endpoint1 fff7_0110 h ufepc2 control register for endpoint2 fff7_0114 h ufeps2 status register for endpoint2 fff7_0118 h ufepc3 control register for endpoint3 fff7_011c h ufeps3 status register for endpoint3 fff7_0180 h ufepib0 in transmission buffer of endpoint0 fff7_0184 h ufepib1 in transmission buffer of endpoint1
24-4 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller address register description fff7_0188 h ufepib2 in transmission buffer of endpoint2 fff7_018c h ufepib3 in transmission buffer of endpoint3 fff7_01c0 h ufepob0 out transmission buffer of endpoint0 fff7_01c4 h ufepob1 out transmission buffer of endpoint1 fff7_01c8 h ufepob2 out transmission buffer of endpoint2 fff7_0200 h | fff7_0213 h ufconfig make-up area of usb function fff7_0404 h ufepdc1 control/status register of dma channel for endpoint1 fff7_0408 h ufepdc2 control/status register of dma channel for endpoint2 fff7_0414 h ufepda1 start address register of dma channel for endpoint1 fff7_0418 h ufepda2 start address register of dma channel for endpoint2 fff7_0424 h ufepds1 data size register of dma channel for endpoint1 fff7_0428 h ufepds2 data size register of dma channel for endpoint2
24-5 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.2. usb function cpu access control register (ufcpac) address fff7_0000 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) cfwe r/w r r r r r r r r r r r r r r r r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) sr bo cbw r/w r r r r r r r r r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 bit field no. name description 31-17 (reserved) reserved field. 16 cfwe write access to make-up area is controlled. 0: writing to the area is invalidated 1: writing to the area is validated 15-4 (reserved) reserved field. 3 sr when 1 is written to this field, software reset of usb function unit is performed and the value of this field returns to 0 after the reset. 0: software reset is not performed 0: software reset is performed 2 bo byte ordering is specified when cpu and dmac access to the register. 0: little endian 1: big endian 1-0 cbw keep this field value as initial value.
24-6 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.3. usb function device control register (ufdvc) address fff7_0004 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/wr r/w r/w r/w r/w r/w r /w r/w r r r r r/w r/w r/w r initial value 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) r/w r r/w r r r r r r r r r/w r/w r/w r/w r/w r/w initial value 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 bit field no. name description 31 mskerraticerr mask bit of erraticerr interrupt. 0 h erraticerr interrupt is not masked 1 h erraticerr interrupt is masked 30 msksetconf mask bit of setconfigure interrupt. 0 h setconfigure interrupt is not masked 1 h setconfigure interrupt is masked 29 mskusbrstb mask bit of usb reset start interrupt. 0 h usb reset start interrupt is not masked 1 h usb reset start interrupt is masked 28 mskusbrste mask bit of usb reset end interrupt. 0 h usb reset end interr upt is not masked 1 h usb reset end interrupt is masked 27 msksetup mask bit of setup interrupt. 0 h setup interrupt is not masked 1 h setup interrupt is masked 26 msksof mask bit of sof interrupt. 0 h sof interrupt is not masked 1 h sof interrupt is masked 25 msksuspendb mask bit of suspend start interrupt. 0 h suspend start interrupt is not masked 1 h suspend start interrupt is masked 24 msksuspende mask bit of suspend end interrupt. 0 h suspend end interrupt is not masked 1 h suspend end interrupt is masked 23-20 (reserved) reserved field. 19 l_mode this is for test. set the value to 0 h . 18 p_mode this is for test. set the value to 0 h .
24-7 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller bit field no. name description 17 lpbkphy setting phy to loopback test mode is specified. normally, set the value to 0 h . 0 h phy performs in normal operation 1 h phy shifts to loopback test mode 16-15 (reserved) reserved field. 14 physusp setting phy forcibly to suspend mode is specified. 0 h phy performs in normal operation 1 h phy shifts to suspend mode 13-6 (reserved) reserved field. 5 disconnect whether to output "non-driving" state to phy is specified. 0 h phy performs in normal operation 1 h "non-driving" state is output 4 selfpower power supply of the device is set. 0 h power supply is bus power 1 h power supply is self power 3 enrmtwkup remote wake-up function is controlled. 0 h remote wake-up function is di sabled (in this case, resume function is disabled) 1 h remote wake-up function is enabled 2 reqresume resume request output is specified. 0 h resume request is not output 1 h resume request is output field value is automatically returned to 0 h this setting is valid only when enrmtwkup field value is 1 h 1-0 reqspeed phy type is specified for connection. 0 h connection in highspeed is requested when host or hub of connection destination corresponds to highspeed mode, highspe ed mode is applied for the connection; if not, fullspeed m ode is applied. 1 h connection in fullspeed is requested although host or hub of connection destination corresponds to highspeed mode, fullspeed mode is applied for the connection when this is set, device chirp is not output during usb reset 2 h , 3 h do not set this register in this lsi
24-8 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.4. usb function device status register (ufdvs) address fff7_0008 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name conf (reserved) crtspeed r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) (reserved) r/w r r r r r r r r r r r r r r r r initial value 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 bit field no. name description 31 interraticerr whether phy is hung up is indicat ed. when the value of this field becomes 1 h and this is not masked, erraticerr interrupt occurs. 0 h phy is not hung up 1 h phy is hung up this field is cleared by writing 0 h ; however, hardware reset or software reset is required to return phy to normal state 30 intsetconf whether configuration value is set by se tconfiguration is indicated. when the value of this field becomes 1 h and this is not masked, setconfi gure interrupt occurs (even though configuration value is the same as before, the value of this field also becomes 1 h .) 0 h setconfiguration is not performed 1 h setconfiguration is performed this field is cleared by writing 0 h 29 intusbrstb whether to detect usb reset start is indicated. when the value of this field becomes 1 h and this is not masked, usb reset start interrupt occurs. 0 h usb reset start is not detected 1 h usb reset start is detected this field is cleared by writing 0 h 28 intusbrste whether to detect usb reset end is indicated. when the value of this field becomes 1 h and this is not masked, usb reset end interrupt occurs. 0 h usb reset end is not detected 1 h usb reset end is detected this field is cleared by writing 0 h 27 intsetup whether to detect setup stage start is i ndicated. when the value of this field becomes 1 h and this is not masked, setup interrupt occurs. 0 h setup stage start is not detected 1 h setup stage start is detected this field is cleared by writing 0 h 26 intsof whether to detect sof reception is indicated. when the value of this field becomes 1 h and this is not masked, sof interrupt occurs. 0 h sof reception is not detected 1 h sof reception is detected this field is cleared by writing 0 h
24-9 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller bit field no. name description 25 intsuspendb whether to detect suspend state is indicated. when the value of this field becomes 1 h and this is not masked, suspend start interrupt occurs. 0 h suspend state is not detected 1 h suspend state is detected this field is cleared by writing 0 h 24 intsuspende whether to detect completi on of suspend state is indicated. when the value of this field becomes 1 h and this is not masked, suspend end interrupt occurs. 0 h completion of suspend state is not detected 1 h completion of suspend state is detected this field is cleared by writing 0 h 23-20 conf current configuration value is indicated. 19-18 (reserved) reserved field. 17-16 crtspeed usb connection speed is indicated. 0 h it is connected in highspeed mode 1 h it is connected in fullspeed mode 2 h , 3 h reserved 15 phyreset this is stat us bit indicating interface between pyh - link. 0 h interface reset between phy ? link is released and the operation starts 1 h interface between phy ? link is in reset and operation of entire usb function unit is not started 14-10 (reserved) reserved field. 9 busreset this is status bit i ndicating usb reset operation status. 0 h usb is not reset 1 h usb is reset 8 suspend this is status bit indicatin g whether device is in suspended. 0 h device is not in suspend state 1 h device is in suspend state 7-0 (reserved) reserved field.
24-10 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.5. usb function endpoint interrupt control register (ufepic) address fff7_000c h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) r/w r r r r r r r r r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 bit field no. name description 31-4 (reserved) reserved field. 3 mskep3 this is mask bit to the interrupt notified from endpoint3. 0 h the interrupt notified from endpoint3 is not masked 1 h the interrupt notified from endpoint3 is masked 2 mskep2 this is mask bit to the interrupt notified from endpoint2. 0 h the interrupt notified from endpoint2 is not masked 1 h the interrupt notified from endpoint2 is masked 1 mskep1 this is mask bit to the interrupt notified from endpoint1. 0 h the interrupt notified from endpoint1 is not masked 1 h the interrupt notified from endpoint1 is masked 0 mskep0 this is mask bit to the interrupt notified from endpoint0. 0 h the interrupt notified from endpoint0 is not masked 1 h the interrupt notified from endpoint0 is masked
24-11 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.6. usb function endpoint interrupt status register (ufepis) address fff7_0010 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-4 (reserved) reserved field. 3 intep3 whether notifying interrupt from endpoint3 is indicated. 0 h interrupt is not notified from endpoint3 1 h interrupt is notified from endpoint3 2 intep2 whether notifying interrupt from endpoint2 is indicated. 0 h interrupt is not notified from endpoint2 1 h interrupt is notified from endpoint2 1 intep1 whether notifying interrupt from endpoint1 is indicated. 0 h interrupt is not notified from endpoint1 1 h interrupt is notified from endpoint1 0 intep0 whether notifying interrupt from endpoint0 is indicated. 0 h interrupt is not notified from endpoint0 1 h interrupt is notified from endpoint0
24-12 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.7. usb function endpoint dma control register (ufepdc) address fff7_0014 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r/w r/w r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) r/w r r r r r r r r r r r r r r/w r/w r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 bit field no. name description 31-19 (reserved) reserved field. 18 dmamode2 utilization of dma transf er at endpoint2 is indicated. 0 h dma transfer is not used at endpoint2 1 h dma transfer is used at endpoint2 17 dmamode1 utilization of dma transf er at endpoint1 is indicated. 0 h dma transfer is not used at endpoint1 1 h dma transfer is used at endpoint1 16-3 (reserved) reserved field. 2 mskdmareq2 whether to mask dma transfer request from endpoint2 is specified. 0 h dma transfer request from endpoint2 is not masked 1 h dma transfer request from endpoint2 is masked 1 mskdmareq1 whether to mask dma transfer request from endpoint1 is specified. 0 h dma transfer request from endpoint1 is not masked 1 h dma transfer request from endpoint1 is masked 0 (reserved) reserved field.
24-13 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.8. usb function endpoint dma status register (ufepds) address fff7_0018 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-3 (reserved) reserved field. 2 dmareq2 dma transfer request from endpoint2 is indicated. 0 h dma transfer is not requested from endpoint2 1 h dma transfer is requested from endpoint2 1 dmareq1 dma transfer request from endpoint1 is indicated. 0 h dma transfer is not requested from endpoint1 1 h dma transfer is requested from endpoint1 0 (reserved) reserved field. 24.5.9. usb function time stamp register (uftstamp) address fff7_001c h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) timstamp r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-11 (reserved) reserved field. 10-0 timstamp frame number at sof reception is indicated.
24-14 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.10. ufeptcsel register address fff7_0020 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-3 (reserved) reserved field. 2 tcselusb2 total transfer count value (cpu side or usb side) is specified at reading eptc2 register. 0 h total transfer count value on cpu side is read from the eptc2 register 1 h total transfer count value on usb side is read from the eptc2 register 1 tcselusb1 total transfer count value (cpu side or usb side) is specified at reading eptc1 register. 0 h total transfer count value on cpu side is read from the eptc1 register 1 h total transfer count value on usb side is read from the eptc1 register 0 (reserved) reserved field. 24.5.11. usb function endpoint1 terminal count register (ufeptc1) address fff7_0024 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name tcnt1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tcnt1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 bit field no. name description 31-0 tcnt1 number of byte of dma transfer performed at endpoint1 is set. when number of byte of dma transfer over multiple packets reaches to the value specified in tcnt1, intdend is set to notify interrupt and mskdmareq1 is set to stop dma transfer. setting 00000000 h to tcnt1 is prohibited.
24-15 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.12. usb function endpoint2 terminal count register (ufeptc2) address fff7_0028 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name tcnt2 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tcnt2 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 bit field no. name description 31-0 tcnt2 number of byte of dma transfer performed at endpoint2 is set. when number of byte of dma transfer over multiple packets reaches to the valu e specified in tcnt2, intdend is set to notify interrupt and mskdmareq2 is set to stop dma transfer. setting 00000000 h to tcnt2 is prohibited. 24.5.13. usb function endpoint0 rx size register (ufeprs0) address fff7_0070 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name size0i size0o r/w r/w r r r r r r r r/w r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-16 (reserved) reserved field 15 seltx0i function of size0i bit is selected. 0 h : rxsize0i 1 h : txsize0i 14-8 size0i number of transmission data byte written in endpoint0i is displayed. it is valid until 1 h is written in ready0i. or, number of read data byte in process from endpoint0i is displayed for sending protocol engine. this becomes invalid after reading and transmission. 7 seltx0o function o size0 o bit is selected. 0 h : rxsize0o 1 h : txsize0o 6-0 size0o number of reception data byte written in/read from endpoint0o is displayed. valid data volume is displayed when intready0o is set.
24-16 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.14. usb function endpoint1 rx size register (ufeprs1) address fff7_0078 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) size1 r/w r/w r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-16 (reserved) reserved field 15 seltx1 function of size 1 bit is selected. 0 h : rxsize1 1 h : txsize1 14-11 (reserved) reserved field 10-0 size1 setting to out transfer buf fer with rxsize1 (seltx1 = 0h): number of reception data byte written in endpoint1 is displayed. valid data volume is displayed when intready1 is set. setting to in transfer buffer with rxsize1 (seltx1 = 0h): number of transmission data byte written in endpoint1 is displayed. valid data volume is displayed until 1 h is written in ready1i. setting to out transfer buffer with txsize1 (seltx1 = 1h): number of reception data byte read from endpoint1 is displayed. valid data volume is displayed when intready1 is set. 24.5.15. usb function endpoint2 rx size register (ufeprs2) address fff7_0080 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) size2 r/w r/w r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-16 (reserved) reserved field 15 seltx2 function of si ze2 bit is selected. 0 h : rxsize2 1 h : txsize2 14-11 (reserved) reserved field 10-0 size2 setting to out transfer buf fer with rxsize2 (seltx2 = 0h): number of reception data byte written in endpoint2 is displayed. valid data volume is displayed when intready2 is set. setting to in transfer buffer with rxsize2 (seltx2 = 0h): number of transmission data byte written in endpoint2 is displayed. valid data volume is displayed until 1 h is written in ready2i. setting to out transfer buffer with txsize2 (seltx1 = 1h): number of reception data byte read from endpoint2 is displayed. valid data volume is displayed when intready2 is set.
24-17 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.16. usb function endpoint3 rx size register (ufeprs3) address fff7_0088 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) size3 r/w r/w r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-16 (reserved) reserved field 15 seltx3 function of size 3 bit is selected. 0 h : rxsize3 1 h: txsize3 14-11 (reserved) reserved field 10-0 size3 setting to out transfer buffer with rxsize3 (seltx3 = 0 h ): number of reception data byte written in endpoint3 is displayed. valid data volume is displayed when intready3 is set. setting to in transfer buffer with rxsize3 (seltx3 = 0 h ): number of transmission data byte written in endpoint3 is displayed. valid data volume is displayed until 1 h is written in ready3i. setting to out transfer buffer with txsize3 (seltx3 = 1 h ): number of reception data byte read from endpoint3 is displayed. valid data volume is displayed when intready3 is set.
24-18 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.17. ufcuscnt register address fff7_00f0 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name tadd[6:0] (reserved) r/w r r/w r/w r/w r/w r/w r/w r/w r r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r/w r r r r r r r r/w r r r r r r/w r/w r/w initial value 0 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 writing other values than initial value to bi t 15, 14, 12 ~ 9, 7 ~3 is not guaranteed. bit field no. name description 31 (reserved) reserved field. 30-24 tadd[6:0] leave this value as default. 23-22 (reserved) reserved field. 21 testse0nack leave this value as default. 20 testk leave this value as default. 19 testj leave this value as default. 18 testp leave this value as default. 17 setconfig leave this value as default. 16 setadd leave this value as default. 15-9 (reserved) reserved field. 8 eninififo the function of inififo0o.inififo0i of the ufepc0 register and inififo1/2/3 of the ufepc1/2/3 register is validated. 0 h invalid 1 h valid 3-7 (reserved) reserved field. 2-1 (reserved) reserved field. write "0" to these bits. note: do not write "1". 0 extrpu whether to use pull-up resistance of built-in lsi is set. 0 h used 1 h not used
24-19 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.18. ufcalb register address fff7_00f4 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) hscalib fscalib r/w r r r r r r r r r r/w r/w r/w r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 bit field no. name description 31-7 (reserved) reserved field. 6-4 hscalib timeout adjustment bit of hs protocol that is to adjust this macro's response time (until timeout occurs) from host in 33.333ns per unit. 000: 736 bit time initial value 010: 768 bit time normally, this register does not need setting. 3 (reserved) reserved field. 2-0 fscalib timeout adjustment bit of fs protocol that is to adjust this macro's response time (until timeout occurs) from host in 33.333ns per unit. 000: 16 bit time initial value 011: 17.2 bit time normally, this register does not need setting.
24-20 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.19. ufeplpbk register address fff7_00f8 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) eplpbko0 eplpbki0 r/w r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-7 (reserved) reserved field. 7-4 eplpbko0 endpoint on loopback0 out is set. 0000 h loopback is not tested. 0001h endpoint1 setting (valid when it is set to makeup area as endpoint out) 0010h endpoint2 setting (valid when it is set to makeup area as endpoint out) 0011 h -1111 h setting prohibited 3-0 eplpbki0 endpoint on loopback0 in is set. 0000 h loopback is not tested. 0001 h endpoint1 setting (valid when it is set to makeup area as endpoint in) 0010 h endpoint2 setting (valid when it is set to makeup area as endpoint in) 0011 h endpoint3 setting 0100 h -1111 h setting prohibited
24-21 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.20. ufintfaltnum register address fff7_00fc h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) numintf r/w r r r r r r r r r r r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name numaltintf3 numaltintf2 numaltintf1 numaltintf0 r/w r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 this lsi does not s upport this register. bit field no. name description 31-19 (reserved) reserved field. 18-16 numintf leave this value as default. 15 (reserved) reserved field. 24-12 numaltintf3 leave this value as default. 11 (reserved) reserved field. 10-8 numaltintf2 leave this value as default. 7 (reserved) reserved field. 6-4 numaltintf1 leave this value as default. 3 (reserved) reserved field. 2-0 numaltintf0 leave this value as default.
24-22 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.21. usb function endpoint0 co ntrol register (ufepc0) address fff7_0100 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) (reserved) r/w r r r r r r r r r/w r/w r/w r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) (reserved) r/w r/w r/w r r r r r r r/w r r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-24 (reserved) reserved field 23 mskclstall this is mask bit to intclstall interrupt. 0 h intclstall interrupt is not masked 1 h intclstall interrupt is masked 22 msknack this is mask bit to intnack interrupt. 0 h intnack interrupt is not masked 1 h intnack interrupt is masked 21 mskstalled this is mask bit to intstalled interrupt. 0 h intstalled interrupt is not masked 1 h intstalled interrupt is masked 20-19 (reserved) reserved field 18 mskping0o this is mask bit to intping0o interrupt. 0 h intping0o interrupt is not masked 1 h intping0o interrupt is masked 17 mskready0o this is mask bit to intready0o interrupt. 0 h intready0o interrupt is not masked 1 h intready0o interrupt is masked 16 mskready0i this is mask bit to intready0i interrupt. 0 h intready0i interrupt is not masked 1 h intready0i interrupt is masked 15 inififo0o when the value of eninifif o field of customcnt register is 1 h , this register becomes valid. moreover, fifo surroundings of endpoint0o are initialized. 0 h initialization is not performed 1 h initialization of out transfer fifo at endpoint0 is performed intready0o field and ready0o field of ufeps0 register, and size0o field of ufeprs0 register are also initialized the value of this field automatically returns to 0 h
24-23 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller bit field no. name description 14 inififo0i this becomes valid when enin ififo field of customcnt register is 1 h . moreover, fifo surroundings of endpoint0o are initialized. 0 h initialization is not performed. 1 h initialization of in transfer fifo at endpoint0 is performed. intready0i field and ready0i field of ufeps0 register, and size0i field of ufeprs0 register are also initialized. the value of this field automatically returns to 0 h. 13-8 (reserved) reserved field 7 testmode0 loopback test mode of endpoint0 is set. 0 h endpoint0 performs normal operation. 1 h endpoint0 shifts to the loopback test mode which is from in to out transfer buffer. 6-3 (reserved) reserved field 2 reqstall stall response from e ndpoint0 to host is specified. 0 h stall response is not performed. 1 h stall response is performed. 1 init0o initialization of out transfer buffer at endpoint0 is instructed. 0 h buffer is not initialized. 1 h buffer is initialized the value of this field is automatically returned to 0 h. 0 init0i initialization of in transfer buffer at endpoint0 is instructed. 0 h buffer is not initialized. 1 h buffer is initialized the value of this field is automatically returned to 0 h.
24-24 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.22. usb function endpoint0 status register (ufeps0) address fff7_0104 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 bit field no. name description 31-24 (reserved) reserved field 23 intclstall intcistall interrupt request is indicated. when stalled field becomes 0 h, the value of this field becomes 1 h . this field is cleared by writing 0 h . 0 h intclstall interrupt is not requested 1 h intclstall interrupt is requested 22 intnack intnack interrupt request is indicated. when nack packet is sent wit hout distinction of in/out transfer, the value of this field becomes 1 h . the distinction should be carried out by using bmrequesttype of the receive d data in setup stage. this field is cleared by writing 0 h . 0 h intnack interrupt is not requested 1 h intnack interrupt is requested 21 intstalled intstalled interrupt request is indicated. when stalled field becomes 1 h, the value of this field becomes 1 h . this field is cleared by writing 0 h . 0 h intstalled interrupt is not requested 1 h intstalled interrupt is requested 20-19 (reserved) reserved field 18 intping0o intping0o interrupt request is indicated. when ping is sent to endpoint0o, the value of this field becomes 1 h . this field is cleared by writing 0 h . 0 h intping0o interrupt is not requested 1 h intping0o interrupt is requested 17 intready0o intready0o interrupt reques t is indicated. when data is ab le to be read from endpoint0o buffer, the value of this field becomes 1 h . this field is cleared by writing 0 h . 0 h intready0o interrupt is not requested 1 h intready0o interrupt is requested 16 intready0i intready0i interrupt request is indicated. when data is able to be read from endpoint0i buffer, the value of this field becomes 1 h . this field is cleared by writing 0 h . 0 h intready0i interrupt is not requested 1 h intready0i interrupt is requested 15-5 (reserved) reserved field
24-25 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller bit field no. name description 4 ready0o whether endpoint0o buffer is busy is indicated. 0 h buffer is busy that data is unable to be read. 1 h buffer is not busy that the data in received buffer by out transfer is able to be read. the value of this field is cleared by writing 1 h , and buffer is able to be received new data by out transfer. when new data is received and its read ing is ready, the value of this field becomes 1 h again. 3 ready0i whether endpoint0i buffer is busy is indicated. 0 h buffer is busy that data is unable to be written. 1 h buffer is not busy that the data sent by in transfer is able to be written to buffer. the value of this field is cleared by writing 1 h ; at the same time, the data in buffer is sent to usb by in transfer. when data is able to be written to the buffer again, the value of this field becomes 1 h . 2 stalled whether the state is stall is indicated. 0 h state is not stall. 1 h state is stall. 1-0 (reserved) reserved field.
24-26 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.23. usb function endpoint1 co ntrol register (ufepc1) address fff7_0108 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) testalt r/w r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r/w r/w r/w r/w r r/w r/w r/w r/w r/w r/w r/w r/w r/w r r/w r/w initial value 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 bit field no. name description 31-28 (reserved) reserved field 27-24 testalt1 this field is to directly set alternate value for testing. writing is enabled when testmode1 field value is 1 h . 23 mskclstall1 this is mask bit to intclstall1 interrupt. 0 h intclstall1 interrupt is not masked. 1 h intclstall1 interrupt is masked. 22 msknack1 this is mask bit to intnack1 interrupt. 0 h intnack1 interrupt is not masked. 1 h intnack1 interrupt is masked. 21 mskstalled1 this is mask bit to intstalled1 interrupt. 0 h intstalled1 interrupt is not masked. 1 h intstalled1 interrupt is masked. 20 mskempty1 this is mask bit to intempty1 interrupt. 0 h intempty1 interrupt is not masked. 1 h intempty1 interrupt is masked. 19 mskdend1 this is mask bit to intdend1 interrupt. 0 h intdend1 interrupt is not masked. 1 h intdend1 interrupt is masked. 18 mskachg1 this is mask bit to intachg1 interrupt. 0 h intachg1 interrupt is not masked. 1 h intachg1 interrupt is masked. 17 mskping1 this is mask bit to intping1 interrupt. 0 h intping1 interrupt is not masked. 1 h intping1 interrupt is masked. 16 mskready1 this is mask bit to intready1 interrupt. 0 h intready1 interrupt is not masked. 1 h intready1 interrupt is masked.
24-27 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller bit field no. name description 15 inififo1 when the value of eninififo field of customcnt register is 1 h , this register becomes valid. fifo surroundings of endpoint1 are initialized. 0 h initialization is not performed 1 h initialization of fifo at endpoint1 is performed. intready1, ready1, empty1, intempty1 of ufeps1 register, dmareq1, dmareq2 of ufepds register, tcnt1, tcnt2 of ufeptc1 register, and size1 of ufeprs1 register are also initialized. after writing 1 h , the value of this bit automatically returns to 0 h . 14 mskspdd1 this is mask bit to intspdd interrupt. 0 h intspdd interrupt is not masked. 1 h intspdd interrupt is masked. 13 mskspr1 this is mask bit to intspr interrupt. 0 h intspr interrupt is not masked. 1 h intspr interrupt is masked. 12 (reserved) reserved field 11 enspdd1 short packet dma done mode is set. 0 h endpoint1 is not in the short packet dma done mode. 1 h endpoint1 is in the shor t packet dma done mode. setting this mode simultaneously with short packet reception mode is prohibited. 10 enspr1 short packet re ception mode is set. 0 h endpoint1 is not in the short packet reception mode. 1 h endpoint1 is in the short packet reception mode. this mode should be proceeded with masking dma transfer request. moreover, setting this mode simultaneously with short pack et dma done mode is prohibited. 9 nackresp1 nac response is instru cted to bulk in/out transfer. 0 h endpoint1 performs normal response. 1 h endpoint1 performs nac response to bulk in/out transfer. 8 nullresp1 null response is instructed to bulk in/interrupt in transfer. when the value of this field is 1 h , null response is carried out though data is in fifo. 0 h endpoint1 performs normal response. 1 h endpoint1 performs null response to bulk in/interrupt in transfer. 7 testmode1 test mode setting to endpoint1 is specified. 0 h endpoint1 performs normal response. 1 h endpoint1 shifts to the test mode th at alternate value is able to be set directly. 6 stalldis1 when host issues setinte rface, and alternation se tting is specified to e ndpoint1 interface, whether to perform stall initialization automatically is specified. 0 h stall is automatically initialized. 1 h stall is not automatically initialized.
24-28 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller bit field no. name description 5 toggledis1 when host issues setinte rface, and alternation setting is spec ified to endpoint1 interface, whether to perform toggle in itialization automatic ally is specified. 0 h toggle is automatically initialized. 1 h toggle is not automatically initialized. 4 inistall1 this field is to instruct stall initialization of endpoint1. 0 h stall is not initialized. 1 h stall is initialized. the value of this field automatically returns to 0 h. 3 initoggle1 this field is to instru ct toggle initialization of endpoint1. 0 h toggle is not initialized. 1 h toggle is in itialized. the value of this field automatically returns to 0 h. 2 (reserved) reserved field. 1 reqstall1 whether to perform stall res ponse to host from endpoint1 is specified. 0 h stall response is not performed. 1 h stall response is performed. 0 init1 this field is to instruct buffer initialization of endpoint1. 0 h buffer is not initialized. 1 h buffer is initialized. the value of this field automatically returns to 0 h.
24-29 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.24. usb function endpoint1 status register (ufeps1) address fff7_010c h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name crtintf crtalt r/w r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) r/w r r/w r/w r r r r r r r r r r/w r/w r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-28 crtintf1 current interface value of endpoint1 is indicated . 27-24 crtalt1 current alternate value of endpoint1 is indicated . 23 mskclstall1 intcistall1 interrupt request is indicated. when stalled1 field becomes 0 h , the value of this field becomes 1 h . this field is cleared by writing 0 h . 0 h intclstall1 interrupt is not requested. 1 h intclstall1 interrupt is requested. 22 intnack1 intnack1 interrupt request is indicated. when nack packet is sent, the value of this field becomes 1 h . this field is cleared by writing 0 h . 0 h intnack1 interrupt is not requested. 1 h intnack1 interrupt is requested. 21 intstalled1 intstalled1 interrupt request is indicated. when stalled1 field becomes 1 h , the value of this field becomes 1 h . this field is cleared by writing 0 h . 0 h intstalled1 interrupt is not requested. 1 h intstalled1 interrupt is requested. 20 intempty1 intempty1 interrupt request is indicated. when buffer in e ndpoint1 becomes empty, the value of this field is 1 h . this field is cleared by writing 0 h . 0 h intempty1 interrupt is not requested. 1 h intempty1 interrupt is requested. 19 intdend1 intdend1 interrupt request is indicated. when total count transf er ends at endpoint1, the value of this field becomes 1 h . this field is cleared by writing 0 h . 0 h intdend1 interrupt is not requested. 1 h intdend1 interrupt is requested. 18 intachg1 intachg1 interrupt request is indicated. when interface's alternate value including endpoint1 is updated by setinterface from the host, the value of this field becomes 1 h . when the alternate value before and after the upda te is the same, the value of this field also becomes 1 h . this field is cleared by writing 0 h . 0 h intachg1 interrupt is not requested. 1 h intachg1 interrupt is requested. 17 intping1 intping1 interrupt request is indicated. when ping is sent to endpoint1, the value of this field becomes 1 h . this field is cleared by writing 0 h . 0 h intping1 interrupt is not requested. 1 h intping1 interrupt is requested.
24-30 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller bit field no. name description 16 intready1 intready1 interrupt request is indicated. wh en endpoint1 is set as in transfer endpoint, data is able to be written to endpoint1 buffer and the value of this field becomes 1 h . when endpoint1 is set as out transfer endpoint, data is able to be read from endpoint1 buffer and the value of this field becomes 1 h . in both cases, this field is cleared by writing 0 h . 0 h intready1 interrupt is not requested. 1 h intready1 interrupt is requested. 15 (reserved) reserved field 14 intspdd1 intspdd1 interrupt request is indicated. 0 h intspdd1 interrupt is not requested. 1 h intspdd1 interrupt is requested. 13 intspr1 intspr1 interrupt request is indicated. when the packet which is able to be read from endpoint1 buffer is short packet, the value of this field becomes 1 h . this is valid when endpoint1 is set to bulk out. 0 h intspr1 interrupt is not requested. 1 h intspr1 interrupt is requested. 12 empty1 whether endpoint1 buffe r is empty is indicated. 0 h buffer is not empty. 1 h buffer is empty. 11-4 (reserved) reserved field 3 ready1o whether out transfer buffer of endpoint1 is busy is indicated. 0 h buffer is busy that data is unable to be read. 1 h buffer is not busy that the data received in buffer by out transfer is able to be read. the value of this field is cleared by writing 1 h , and buffer is able to receive new data by out transfer. when new data is received and its reading is ready, the value of this field becomes 1 h again. 2 ready1i whether in transfer buffer of endpoint1 is busy is indicated. 0 h buffer is busy that data is unable to be written. 1 h buffer is not busy that the data to be sent by in transfer is able o be written. the value of this field is cleared by writing 1 h ; at the same time, the data in buffer is sent to usb by in transfer. when data is able to be written to the buffer again, the value of this field becomes 1 h . 1 stalled1 whether the state of endpoint1 is stall is indicated. 0 h the state is not stall. 1 h the state is stall. 0 (reserved) reserved field
24-31 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.25. usb function endpoint2 co ntrol register (ufepc2) address fff7_0110 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) testalt2 r/w r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r/w r/w r/w r/w r r/w r/w r/w r/w r/w r/w r/w r/w r/w r r/w r/w initial value 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 bit field no. name description 31-28 (reserved) reserved field. 27-24 testalt2 this field is to directly set alternate value for testing. writing is enabled when testmode2 field value is 1 h . 23 mskclstall2 this is mask bit to intclstall2 interrupt. 0 h intclstall2 interrupt is not masked 1 h intclstall2 interrupt is masked 22 msknack2 this is mask bit to intnack2 interrupt. 0 h intnack2 interrupt is not masked. 1 h intnack2 interrupt is masked. 21 mskstalled2 this is mask bit to intstalled2 interrupt. 0 h intstalled2 interrupt is not masked. 1 h intstalled2 interrupt is masked. 20 mskempty2 this is mask bit to intempty2 interrupt. . 0 h intempty2 interrupt is not masked. 1 h intempty2 interrupt is masked. 19 mskdend2 this is mask bit to intdend2 interrupt. 0 h intdend2 interrupt is not masked. 1 h intdend2 interrupt is masked. 18 mskachg2 this is mask bit to intachg2 interrupt. 0 h intachg2 interrupt is not masked. 1 h intachg2 interrupt is masked. 17 mskping2 this is mask bit to intping2 interrupt. 0 h intping2 interrupt is not masked. 1 h intping2 interrupt is masked. 16 mskready2 this is mask bit to intready2 interrupt. 0 h intready2 interrupt is not masked. 1 h intready2 interrupt is masked.
24-32 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller bit field no. name description 15 inififo2 when the value of eninifif o field of customcnt register is 1 h , this register becomes valid. moreover, fifo surroundings of endpoint2 are initialized. 0 h initialization is not performed 1 h initialization of fifo at endpoint2 is performed. intready2, ready2, empty2, intempty2 of ufeps2 register, dmareq1, dmareq2 of ufepds register, tcnt1, tcnt2 of ufeptc2 register, and size2 of ufeprs2 register are also initialized. after writing 1 h , the value of this bit automatically returns to 0 h . 14 mskspdd2 this is mask bit to intspdd2 interrupt. 0 h intspdd2 interrupt is not masked. 1 h intspdd2 interrupt is masked. 13 mskspr2 this is mask bit to intspr2 interrupt. 0 h intspr2 interrupt is not masked. 1 h intspr2 interrupt is masked. 12 (reserved) reserved field 11 enspdd2 short packet dma done mode is set. 0 h endpoint2 is not in the short packet dma done mode. 1 h endpoint2 is in the shor t packet dma done mode. setting this mode simultaneously with short packet reception mode is prohibited. 10 enspr2 short packet re ception mode is set. 0 h endpoint2 is not in the short packet reception mode. 1 h endpoint2 is in the short packet reception mode. this mode should be proceeded with masking dma transfer request. moreover, setting this mode simultaneously with short packet dma done mode is prohibited. 9 nackresp2 nac response is instru cted to bulk in/out transfer. 0 h endpoint2 performs normal response. 1 h endpoint2 performs nac response to bulk in/out transfer. 8 nullresp2 null response is instructed to bulk in/interrupt in transfer. when the value of this field is 1 h, null response is carried out though data is in fifo. 0 h endpoint2 performs normal response. 1 h endpoint2 performs null response to bulk in/interrupt in transfer. 7 testmode2 test mode setting to endpoint2 is specified. 0 h endpoint1 performs normal operation. 1 h endpoint2 shifts to the test mode th at alternate value is able to be set directly. 6 stalldis2 when host issues setinte rface and altern ation setting is specified to endpoint2 interface, whether to perform stall initialization automatically is specified. 0 h stall is automatically initialized. 1 h stall is not automatically initialized.
24-33 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller bit field no. name description 5 toggledis2 when host issues setinte rface and altern ation setting is specified to endpoint2 interface, whether to perform toggle initi alization automatically is specified. 0 h toggle is automatically initialized. 1 h toggle is not automatically initialized. 4 inistall2 this field is to instruct stall initialization of endpoint2. 0 h stall is not initialized. 1 h stall is initialized. the value of this field automatically returns to 0 h. 3 initoggle2 this field is to instru ct toggle initialization of endpoint2. 0 h toggle is not initialized. 1 h toggle is initialized. the value of this field automatically returns to 0 h. 2 (reserved) reserved field. 1 reqstall2 whether to perform stall respon se to host from endpoint2 is indicated. 0 h stall response is not performed. 1 h stall response is performed. 0 init2 this field is to instruct buffer initialization of endpoint2. 0 h buffer is not initialized. 1 h buffer is initialized. the value of this field automatically returns to 0 h.
24-34 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.26. usb function endpoint2 status register (ufeps2) address fff7_0114 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name crtintf2 crtalt2 r/w r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) r/w r r/w r/w r r r r r r r r r r/w r/w r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-28 crtintf2 current interface valu e of endpoint2 is indicated. 27-24 crtalt2 current alternate valu e of endpoint2 is indicated. 23 mskclstall2 intcistall2 interrupt request is indicated. when stalled2 field becomes 0 h , the value of this field becomes 1 h . this field is cleared by writing 0 h . 0 h intclstall2 interrupt is not requested. 1 h intclstall2 interrupt is requested. 22 intnack2 intnack2 interrupt request is indicated. when nack packet is sent, the value of this field becomes 1 h . this field is cleared by writing 0 h . 0 h intnack2 interrupt is not requested. 1 h intnack2 interrupt is requested. 21 intstalled2 intstalled2 interrupt request is indicated. when stalled2 field becomes 1 h , the value of this field becomes 1 h . this field is cleared by writing 0 h . 0 h intstalled2 interrupt is not requested. 1 h intstalled2 interrupt is requested. 20 intempty2 intempty2 interrupt request is indicated. when buffer in endpoint2 b ecomes empty, the value of this field is 1 h . this field is cleared by writing 0 h . 0 h intempty2 interrupt is not requested. 1 h intempty2 interrupt is requested. 19 intdend2 intdend2 interrupt request is indicated. when total count transf er ends at endpoint2, the value of this field becomes 1 h . this field is cleared by writing 0 h . 0 h intdend2 interrupt is not requested. 1 h intdend2 interrupt is requested. 18 intachg2 intachg2 interrupt request is indicated. when interface's alternate value including endpoint2 is updated by setinterface from the host, the value of this field becomes 1 h . when the alternate value before and after the upda te is the same, the value of this field also becomes 1 h . this field is cleared by writing 0 h . 0 h intachg2 interrupt is not requested. 1 h intachg2 interrupt is requested. 17 intping2 intping2 interrupt request is indicated. when ping is sent to endpoint2, the value of this field becomes 1 h . this field is cleared by writing 0 h . 0 h intping2 interrupt is not requested. 1 h intping2 interrupt is requested.
24-35 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller bit field no. name description 16 intready2 intready2 interrupt request is indicated. when endpoint2 is set as in transfer endpoint, data is able to be written to endpoint2 buffer and the value of this field becomes 1 h . when endpoint2 is set as out transfer endpoint, data is able to be read from endpoint2 buffer and the value of this field becomes 1 h . in both cases, this field is cleared by writing 0 h . 0 h intready2 interrupt is not requested. 1 h intready2 interrupt is requested. 15 (reserved) reserved field. 14 intspdd2 intspdd2 interrupt request is indicated. 0 h intspdd2 interrupt is not requested. 1 h intspdd2 interrupt is requested. 13 intspr2 intspr2 interrupt request is indicated. when the packet which is able to be read from endpoint2 buffer is short packet, the value of this field becomes 1 h . this is valid when endpoint2 is set to bulk out. 0 h intspr2 interrupt is not requested. 1 h intspr2 interrupt is requested. 12 empty2 whether endpoint2 buffe r is empty is indicated. 0 h buffer is not empty. 1 h buffer is empty. 11-4 (reserved) reserved field. 3 ready2o whether out transfer buffer of endpoint2 is busy is indicated. 0 h buffer is busy that data is unable to be read. 1 h buffer is not busy that the data received in buffer by out transfer is able to be read. the value of this field is cleared by writing 1 h , and new data is able to be received to buffer by out transfer. when new data is received in the buffer and its reading is ready, the value of this field becomes 1 h again. 2 ready2i whether in transfer buffer of endpoint2 is busy is indicated. 0 h buffer is busy that data is unable to be written. 1 h buffer is not busy that the data to be sent by in transfer is able to be written. the value of this field is cleared by writing 1 h ; at the same time, the data in buffer is sent to usb by in transfer. when data is able to be writte n to the buffer again, the value of this field becomes 1 h . 1 stalled2 whether the state of endpoint2 is stall is indicated. 0 h the state not is stall. 1 h the state is stall. 0 (reserved) reserved field.
24-36 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.27. usb function endpoint3 co ntrol register (ufepc3) address fff7_0118 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) testalt3 r/w r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r/w r/w r/w r/w r r/w r/w r/w r/w r/w r/w r/w r/w r/w r r/w r/w initial value 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 bit field no. name description 31-28 (reserved) reserved field. 27-24 testalt3 this field is to directly set alternate value for testing. writing is enabled when testmode3 field value is 1 h . 23 mskclstall3 this is mask bit to intclstall3 interrupt. 0 h intclstall3 interrupt is not masked. 1 h intclstall3 interrupt is masked. 22 msknack3 this is mask bit to intnack3 interrupt. 0 h intnack3 interrupt is not masked. 1 h intnack3 interrupt is masked. 21 mskstalled3 this is mask bit to intstalled3 interrupt. 0 h intstalled3 interrupt is not masked. 1 h intstalled3 interrupt is masked. 20 mskempty3 this is mask bit to intempty3 interrupt. 0 h intempty3 interrupt is not masked. 1 h intempty3 interrupt is masked. 19 mskdend3 this is mask bit to intdend3 interrupt. 0 h intdend3 interrupt is not masked. 1 h intdend3 interrupt is masked. 18 mskachg3 this is mask bit to intachg3 interrupt. 0 h intachg3 interrupt is not masked. 1 h intachg3 interrupt is masked. 17 mskping3 this is mask bit to intping3 interrupt. 0 h intping3 interrupt is not masked. 1 h intping3 interrupt is masked. 16 mskready3 this is mask bit to intready3 interrupt. 0 h intready3 interrupt is not masked. 1 h intready3 interrupt is masked.
24-37 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller bit field no. name description 15 inififo3 when the value of eninifif o field of customcnt register is 1 h , this register becomes valid. moreover, fifo surroundings of endpoint3 are initialized 0 h initialization is not performed. 1 h initialization of fifo at endpoint3 is performed. intready3, ready3, empty3, intempty3 of ufeps3 register, dmareq1, dmareq2 of ufepds register, tcnt1, tcnt2 of ufeptc3 register, and size3 of ufeprs3 register are also initialized. after writing 1 h , the value of this bit automatically returns to 0 h . 14 mskspdd3 this is mask bit to intspdd3 interrupt. 0 h intspdd3 interrupt is not masked. 1 h intspdd3 interrupt is masked. 13 mskspr3 this is mask bit to intspr3 interrupt. 0 h intspr3 interrupt is not masked. 1 h intspr3 interrupt is masked. 12 (reserved) reserved field. 11 enspdd3 short packet dma done mode is set. 0 h endpoint3 is not in the short packet dma done mode. 1 h endpoint3 is in the shor t packet dma done mode. setting this mode simultaneously with short packet reception mode is prohibited. 10 enspr3 short packet re ception mode is set. 0 h endpoint3 is not in the short packet reception mode. 1 h endpoint3 is in the short packet reception mode. this mode should be proceeded with masking dma transfer request. moreover, setting this mode simultaneously with short packet dma done mode is prohibited. 9 nackresp3 nac response is instru cted to bulk in/out transfer. 0 h endpoint1 performs normal response. 1 h endpoint1 performs nac response to bulk in/out transfer. 8 nullres3 null response is instructed to bulk in/interrupt in transfer. when the value of this field is 1 h , null response is carried out though data is in fifo. 0 h endpoint3 performs normal response. 1 h endpoint3 performs null response to bulk in/interrupt in transfer. 7 testmode3 test mode setting to endpoint3 is specified. 0 h endpoint3 performs normal operation. 1 h endpoint3 shifts to the test mode th at alternate value is able to be set directly. 6 stalldis3 when host issues setinte rface and alternation setting is speci fied to endpoint3 interface, whether to perform stall initialization automatically is specified. 0 h stall is automatically initialized. 1 h stall is not automatically initialized.
24-38 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller bit field no. name description 5 toggledis3 when host issues setinte rface and alternation setting is speci fied to endpoint3 interface, whether to perform toggle initi alization automatically is specified. 0 h toggle is automatically initialized. 1 h toggle is not automatically initialized. 4 inistall3 this field is to instruct stall initialization of endpoint3. 0 h stall is not initialized. 1 h stall is initialized. the value of this field automatically returns to 0 h. 3 initoggle3 this field is to instru ct toggle initialization of endpoint3. 0 h toggle is not initialized. 1 h toggle is initialized. the value of this field automatically returns to 0 h. 2 (reserved) reserved field. 1 reqstall3 whether to perform stall respon se to host from endpoint3 is indicated. 0 h stall response is not performed. 1 h stall response is performed. 0 init3 this field is to instruct buffer initialization of endpoint3. 0 h buffer is not initialized. 1 h buffer is initialized. the value of this field automatically returns to 0 h.
24-39 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.28. usb function endpoint3 status register (ufeps3) address fff7_011c h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name crtintf3 crtalt3 r/w r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) r/w r r/w r/w r r r r r r r r r r/w r/w r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-28 crtintf3 current interface va lue of endpoint3 is indicated. 27-24 crtalt3 current alternate valu e of endpoint3 is indicated. 23 mskclstall3 intcistall3 interrupt request is indicated. when stalled3 field becomes 0 h , the value of this field becomes 1 h . this field is cleared by writing 0 h . 0 h intclstall3 interrupt is not requested. 1 h intclstall3 interrupt is requested. 22 intnack3 intnack3 interrupt request is indicated. when nack packet is sent, the value of this field becomes 1 h . this field is cleared by writing 0 h . 0 h intnack3 interrupt is not requested. 1 h intnack3 interrupt is requested. 21 intstalled3 intstalled3 interrupt request is indicated. when stalled3 field becomes 1 h , the value of this field also becomes 1 h . this field is cleared by writing 0 h . 0 h intstalled3 interrupt is not requested. 1 h intstalled3 interrupt is requested. 20 intempty3 intempty3 interrupt request is indicated. when buffer in e ndpoint3 becomes empty, the value of this field is 1 h . this field is cleared by writing 0 h . 0 h intempty3 interrupt is not requested. 1 h intempty3 interrupt is requested. 19 intdend3 intdend3 interrupt request is indicated. when total count transf er ends at endpoint3, the value of this field becomes 1 h . this field is cleared by writing 0 h . 0 h intdend3 interrupt is not requested. 1 h intdend3 interrupt is requested. 18 intachg3 intachg3 interrupt request is indicated. when interface's alternate value including endpoint1 is updated by setinterface from the host, the value of this field becomes 1 h . when the alternate value before and after the upda te is the same, the value of this field also becomes 1 h . this field is cleared by writing 0 h . 0 h intachg3 interrupt is not requested. 1 h intachg3 interrupt is requested. 17 intping3 intping3 interrupt request is indicated. when ping is sent to endpoint3, the value of this field becomes 1 h . this field is cleared by writing 0 h . 0 h intping3 interrupt is not requested. 1 h intping3 interrupt is requested.
24-40 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller bit field no. name description 16 intready3 intready3interrupt request is indicated. wh en endpoint3 is set as in transfer endpoint, data is able to be written to endpoint3 buffer and the value of this field becomes 1 h . when endpoint3 is set as out transfer endpoint, data is able to be read from endpoint3 buffer and the value of this field becomes 1 h . in both cases, this field is cleared by writing 0 h . 0 h intready3 interrupt is not requested. 1 h intready3 interrupt is requested. 15 (reserved) reserved field. 14 intspdd3 intspdd3 interrupt request is indicated. 0 h intspdd3 interrupt is not requested. 1 h intspdd3 interrupt is requested. 13 intspr3 intspr3 interrupt request is indicated. when the packet which is able to be read from endpoint3 buffer is short packet, the value of this field becomes 1 h . this is valid when endpoint is set to bulk out. 0 h intspr3 interrupt is not requested. 1 h intspr3 interrupt is requested. 12 empty3 whether endpoint3 buffe r is empty is indicated. 0 h buffer is not empty. 1 h buffer is empty. 11-4 (reserved) reserved field. 3 ready3o whether out transfer buffer of endpoint3 is busy is indicated. 0 h buffer is busy that data is unable to be read. 1 h buffer is not busy that the data received in buffer by out transfer is able to be read. the value of this field is cleared by writing 1 h , and new data is able to be received to buffer by out transfer. when new data is received in the buffer and its reading is ready, the value of this field becomes 1 h again. 2 ready3i whether in transfer buffer of endpoint3 is busy is indicated. 0 h buffer is busy that data is unable to be written. 1 h buffer is not busy that the data to be sent by in transfer is able to be written. the value of this field is cleared by writing 1 h ; at the same time, the data in buffer is sent to usb by in transfer. when data is able to be writte n to the buffer again, the value of this field becomes 1 h . 1 stalled3 whether the state of endpoint3 is stall is indicated. 0 h the state is not stall. 1 h the state is stall. 0 (reserved) reserved field.
24-41 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.29. usb function endpoint0 in buffer register (ufepib0) address fff7_0180 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name epinbuf r/w w w w w w w w w w w w w w w w w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name epinbuf r/w w w w w w w w w w w w w w w w w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-0 epinbuf in transfer buffer for endpoint0. 24.5.30. usb function endpoint1 in buffer register (ufepib1) address fff7_0184 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name epinbuf r/w w w w w w w w w w w w w w w w w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name epinbuf r/w w w w w w w w w w w w w w w w w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-0 epinbuf in transfer buffer for endpoint1. 24.5.31. usb function endpoint2 in buffer register (ufepib2) address fff7_0188 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name epinbuf r/w w w w w w w w w w w w w w w w w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name epinbuf r/w w w w w w w w w w w w w w w w w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-0 epinbuf in transfer buffer for endpoint2.
24-42 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.32. usb function endpoint3 in buffer register (ufepib3) address fff7_018c h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name epinbuf r/w w w w w w w w w w w w w w w w w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name epinbuf r/w w w w w w w w w w w w w w w w w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-0 epinbuf in transfer buffer for endpoint3. 24.5.33. usb function endpoint0 out bu ffer register (ufepob0) address fff7_01c0 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name epoutbuf r/w r r r r r r r r r r r r r r r r initial value - - - - - - - - - - - - - - - - bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name epoutbuf r/w r r r r r r r r r r r r r r r r initial value - - - - - - - - - - - - - - - - bit field no. name description 31-0 epoutbuf out transfer buffer for endpoint0. 24.5.34. usb function endpoint1 out bu ffer register (ufepob1) address fff7_01c4 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name epoutbuf r/w r r r r r r r r r r r r r r r r initial value - - - - - - - - - - - - - - - - bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name epoutbuf r/w r r r r r r r r r r r r r r r r initial value - - - - - - - - - - - - - - - - bit field no. name description 31-0 epoutbuf out transfer buffer for endpoint1.
24-43 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.35. usb function endpoint2 out bu ffer register (ufepob2) address fff7_01c8 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name epoutbuf r/w r r r r r r r r r r r r r r r r initial value - - - - - - - - - - - - - - - - bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name epoutbuf r/w r r r r r r r r r r r r r r r r initial value - - - - - - - - - - - - - - - - bit field no. name description 31-0 epoutbuf out transfer buffer for endpoint2.
24-44 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.36. ufconfig registers address fff7_0200 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name make-up data r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name make-up data r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 endpoint information of the protocol engine is set. be sure to complete the setting before communication starts. bit field no. name description 31-0 make-up data set 01200120 h for the data setting value. address fff7_0204 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name numtr size alt r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alt intf conf type io epnum r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 endpoint0 information of the protocol engine is set. be sure to complete the setting before communication starts. bit field no. name description 31-30 numtr set 2'b00 for the data setting value. 29-19 size max. packet size setting of endpoint0. set followings: 8 byte: 11'b000_0000_1000 or 64 byte: 11'b000_0100_0000. 18-15 alt set 4'b0000 for the data setting value. 14-11 intf set 4'b0000 for the data setting value. 10-7 conf set 4'b0000 for the data setting value. 6-5 type endpoint0 type setting. set 2'b00 of the control transfer. 4 io endpoint0 in/out setting. set 1'b0 of the out setting. 1'b0 setting: out 1'b1 setting: in 3-0 epnum endpoint number setting. set 4'h0 for the data setting value.
24-45 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller address fff7_0208 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name numtr size alt r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alt intf conf type io epnum r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 endpoint1 information of the protocol engine is set. be sure to complete the setting before communication starts. bit field no. name description 31-30 numtr set 2'b00 for the data setting value. 29-19 size max. packet size setting of endpoint1. set followings: 64 byte (full speed): 11'b000_0100_0000 512 byte (high speed): 11'b010_0000_0000. 18-15 alt set 4'b0000 for the data setting value. 14-11 intf set 4'b0000 for the data setting value. 10-7 conf set 4'b0000 for the data setting value. 6-5 type endpoint1 type setting. set 2'b10 of the bulk transfer. 4 io endpoint1 in/out setting. 1'b0 setting: out 1'b1 setting: in 3-0 epnum endpoint number setting. set 4'h1 for the data setting value. address fff7_020c h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name numtr size alt r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alt intf conf type io epnum r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 endpoint2 information of the protocol engine is set. be sure to complete the setting before communication starts. bit field no. name description 31-30 numtr set 2'b00 for the data setting value. 29-19 size max. packet size setting of endpoint2. set followings: 64 byte (full speed): 11'b000_0100_0000 512 byte (high speed): 11'b010_0000_0000. 18-15 alt set 4'b0000 for the data setting value. 14-11 intf set 4'b0000 for the data setting value. 10-7 conf set 4'b0000 for the data setting value. 6-5 type endpoint2 type setting. set 2'b10 of the bulk transfer.
24-46 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller bit field no. name description 4 io endpoint2 in/out setting. 1'b0 setting: out 1'b1 setting: in 3-0 epnum endpoint number setting. set 4'h2 for the data setting value. address fff7_0210 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name numtr size alt r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alt intf conf type io epnum r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 endpoint3 information of the protocol engine is set. be sure to complete the setting before communication starts. bit field no. name description 31-30 numtr set 2'b00 for the data setting value. 29-19 size max. packet size setting of endpoint3. set followings: 8 byte (full speed): 11?b000_0000_1000 64 byte (high speed): 11?b000_0100_0000 18-15 alt set 4'b0000 for the data setting value. 14-11 intf set 4'b0000 for the data setting value. 10-7 conf set 4'b0000 for the data setting value. 6-5 type endpoint3 type setting. set 2'b11 of the interrupt transfer. 4 io endpoint3 in/out setting. settings except in setting are prohibited in the interrupt transfer. 1'b0 setting: out 1'b1 setting: in 3-0 epnum endpoint number setting. set 4'h3 for the data setting value.
24-47 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.37. usb function endpoint1 dma control/status register (ufepdc1) address fff7_0404 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) epnf1 epne1 epai1 epio1 epdf1 epdm1 epdi1 epde1 r/w r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 bit field no. name description 31-8 (reserved) reserved field 7 epnf1 whether null packet is received is indicated. this field is cleared by writing 0 h . 0 h null packet is not received. 1 h null packet is received. if this is not masked, null packet reception interrupt occurs. 6 epne1 this is enable bit to null packet reception interrupt. 0 h null packet reception in terruption does not occur. 1 h null packet reception interruption occurs. 5 epai1 update method of dma transfer address is specified. 0 h the address set to epda1 register is repeatedly used. 1 h dma transfer is performed with incrementing the address. 4 epio1 endpoint1 in/out is specified. 0 h endpoint1 is in endpoint. 1 h endpoint1 is out endpoint. 3 epdf1 this is status bit that shows fail/abort of dma transfer. 0 h fail/abort do not occur. 1 h error occurs and transfer stops. the value of this field is cleared by writing 0 h . writing 1 h forcibly ends the process. 2 epdm1 this is mask bit to dma transfer end interrupt. 0 h dma transfer end interrupt is not masked. 1 h dma transfer end interrupt is masked. 1 epdi1 this is status bit i ndicating occurrence of dma transfer end interrupt request. 0 h dma transfer end interrupt request does not occur. 1 h dma transfer end interrupt request occurs. if this is not masked, dma tr ansfer end interrupt occurs. although the transfer is discontinued by error, the value of this field becomes 1 h. the value of this field is cleared by writing 0 h .
24-48 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller bit field no. name description 0 epde1 this is dma transfer enable bit. 0 h dma transfer is disabled. the transfer is forcibly terminated by writing 0 h to this field during dma transfer. 1 h dma transfer is enabled. when dma transfer is requested from endpoint1 and the value of this field is 1 h , dma transfer is performed.
24-49 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.38. usb function endpoint2 dma control/status register (ufepdc2) address fff7_0408 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) epnf2 epne2 epai2 epio2 epdf2 epdm2 epdi2 epde2 r/w r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 bit field no. name description 31-8 (reserved) reserved field 7 epnf2 whether null packet is received is indicated. the value of this field is cleared by writing 0 h . 0 h null packet is not received. 1 h null packet is received. if this is masked, null packet reception interrupt occurs. 6 epne2 this is enable bit to null packet reception interrupt. 0 h null packet reception in terruption does not occur. 1 h null packet reception interruption occurs. 5 epai2 update method of dma transfer address is specified. 0 h the address set to epda2 register is repeatedly used. 1 h dma transfer is performed with incrementing the address. 4 epio2 endpoint2 in/out is specified. 0 h endpoint2 is in endpoint. 1 h endpoint2 is out endpoint. 3 epdf2 this is status bit that shows fail/abort of the dma transfer. 0 h fail/abort do not occur 1 h error occurs and transfer stops. the value of this field is cleared by writing 0 h . writing 1 h forcibly ends the process. 2 epdm2 this is mask bit to dma transfer end interrupt. 0 h dma transfer end interrupt is not masked. 1 h dma transfer end interrupt is masked. 1 epdi2 this is status bit i ndicating occurrence of dma transfer end interrupt request. 0 h dma transfer end interrupt request does not occur. 1 h dma transfer end interrupt request occurs. if this is not masked, dma tr ansfer end interrupt occurs. although the transfer is discontinued by error, the value of this field becomes 1 h. the value of this field is cleared by writing 0 h .
24-50 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller bit field no. name description 0 epde2 this is dma transfer enable bit. 0 h dma transfer is disabled. the transfer is forcibly terminated by writing 0 h to this field during dma transfer. 1 h dma transfer is enabled. when dma transfer is requested from endpoint2 and the value of this field is 1 h , dma transfer is performed. 24.5.39. usb function endpoint1 dma address register (ufepda1) address fff7_0414 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name epda1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name epda1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-0 epda1 start address of dma transfer to endpoint1 is stored. low order 2 bits are fixed to 0.
24-51 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.40. usb function endpoint2 dma address register (ufepda2) address fff7_0418 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name epda2 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name epda2 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-0 epda2 start address of dma transfer to endpoint2 is stored. the 2 least significant bits are fixed to 0. 24.5.41. usb function endpoint1 dma size register (ufepds1) address fff7_0424 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name epds1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name epds1 r/w r/w r/w r?w r?w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-0 epds1 when endpoint1 is set to in endpoint, numbe r of dma transfer byte - 1 of endpoint1 should be set. if it is set to out endpoint, set 00000000 h .
24-52 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.5.42. usb function endpoint2 dma size register (ufepds2) address fff7_0428 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name epds2 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name epds2 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r?w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name description 31-0 epds2 when endpoint2 is set to in endpoint, number of dma transfer byte - 1 of endpoint2 should be set. if it is set to out endpoint, set 00000000 h .
24-53 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.6. operation 24.6.1. endpoint composition table 24-3 endpoint composition hs fs ep# cf# if# al# type size cf# if# al# type size ep0i - - - ctl-in 64 - - - ctl-in 64 a ep0o - - - ctl-out 64 - - - ctl-out 64 ep0i - - - ctl-in 64 - - - ctl-in 8 b ep0o - - - ctl-out 64 - - - ctl-out 8 ep1~2 1 0 0 blk-out 512 1 0 0 blk-out 64 c ep1~2 1 0 0 blk-in 512 1 0 0 blk-in 64 d ep3 1 0 0 int-in 64 1 0 0 int-in 8 ep0i and ep0o are accessible in all configurations. maxpacketsize of ep0i and ep0o is able to select above a or b column. ep1~2 is able to select 2 settings of c column. ep3 setting is in d column.
24-54 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.6.2. reset sequence reset system chart of function link part is shown in figure 242. figure 24-2 reset system chart of function link part reset is provided to each internal pin of "internal cpu system reset" and "internal utmi system reset" in function link dmac block and function link block as well as "internal phy system reset" in phy. "internal cpu system reset" and "internal phy system reset" are generated from the same generation circuit the same timing. since these internal reset signa ls are held for certain time even after reset release, register access and usb communication are able to start after the reset release. at the same time of asserting reset, usb_hsdp, usb_hsdm, usb_fsdp, and usb_fsdm shift to input state. there are following two cases of the sequences fr om the reset release to usb communication start: 1. disconnect of the ufdvc register is released within 6ms to start communication after internal utmi system reset is released. 2. after internal utmi system reset is released, disc onnect is released after shifting to suspend state without releasing it for 6ms or more. see the following pages for more detail.
24-55 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.6.3. to start communication with releasing disconnect of the ufdvc register w ithin 6ms after internal utmi system reset is released figure 24-3 usb communication's start timing "internal cpu system reset" and "internal phy reset" are asserted continuously for 49 cycle hclk time after reset release. therefore, register access is ab le to perform after "inter nal cpu system reset" is released. "internal utmi system reset" is a sserted continuously for about 3ms with setting "0" to physusp bit of the ufdvc register after releasing "internal phy system reset" and "internal cpu system reset". therefore, usb communication is able to be performed after "internal utmi system reset" is released. judgment of "internal utmi system reset" release is performed by monitoring phyreset bit of the ufdvs register. disconnect bit of the ufdvc register is not able to be reset to "0" until "internal utmi system reset" is released. about 3ms of period that "inter nal utmi system reset" needs is the required time for internal pll, which generates phy clock, to proceed stable oscillation. since this time is managed by usb_cryck48, reference clock of pll, usb_cryck48 input is required at reset. when setting disconnect bit of the ufdvc register to "0" within 6ms after "internal utmi system reset" is released, usb_hsdp is immedi ately connected to pull-up resist or and usb communication starts. if the time exceeds 6ms after "internal utmi system re set" is released, macro shifts to suspend state that usb_hsdp is not connected even disconnect bit is released. this operation is described in the next page. 50 cycle (hclk) 3msec pll oscillation stability waiting time of phy 32cycle 30mhz (phy clock) ufdvc register's disconnect = "1" is unable to be released during this period. hclk internal utmi system reset (phyreset bit) reset internal cpu system reset internal phy system reset phy clock (output from phy block) clock activates clock activates a ccess to internal registe r usb communication control v alid prohibited invalid v alid physusp bit
24-56 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.6.4. to release disconnect after sh if ting the state to suspend without releasing disconnect for 6ms or more after internal utmi system reset is released figure 24-4 timing for usb functi on controller to enter suspend state when disconnect is not released for 6ms or more af ter reset is released by the same sequence as " 24.6.3", th is macro shifts to suspend state and stops phy clock. if disconnect is released after the process, usb_hsdp is not immediately connect ed. it is connected 3ms after the release for phy clock to resume, then usb communication starts. 32 cycles (phyclock 30mhz) 50 cycles (hclk) 3msec pll oscillation stability waiting time of phy 6msec suspend state when disconnect is released in this period, usb_hsdp is immediately pulled-up (same as the fi g ure in 24.6.3 u p to this p rocess ) access to ufdvc register and release disconnect usb_hsdp is pulled-up hclk internal utmi system reset (phyreset bit) reset internal cpu system reset internal phy system reset phy clock (output from phy block) clock activates clock activates 3msec a ccess to internal registe r usb communication control v alid prohibited invalid v alid invalid v alid ufdvc register's disconnect = "1" is unable to be released during this period. clock activates physusp bit
24-57 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.6.5. cpubuswidth and cpubyteoder setting be sure not to change setting value for cpubuswidth bit and cpubyteoder bit of the ufcpac register to other values than the initial value. ? cpubuswidth = 2'b10 (32 bit mode) ? cpubyteoder = 1'b0 (little mode) 24.6.6. cpubyteoder setting value and usb transfer byte order slave and master transfer become as follows by the cpubyteoder setting. ? 32 bit mode and little mode little 31 24 23 16 15 8 7 0 data bus byte 3 byte 2 byte 1 byte 0 transfer order
24-58 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.6.7. access method to function link endpoint buffer (slave interface) 32 bit mode and little mode writing operation writing is proceeded in 32 bit. when fraction byte to 32 bit (4 byte) is needed, its process should be carried out at the last of 1 packet. operation varies depending on transfer volume of 1 packet. 1. writing amount is 4 byte n (n: integer) a) 32 bit writing for n time(s) f_hwdatas no. of writing f_haddrs[1:0] f_hsizes[2:0] [31:24] [23:16] [15:8] [7:0] n 00 010 data (4n-0) data (4n-1) data (4n-2) data (4n-3) 2. writing amount 4 byte n + 1 byte (n: integer) a) 32bit writing for n time(s) + 1 byte writing at the end f_hwdatas no. of writing f_haddrs[1:0] f_hsizes[2:0] [31:24] [23:16] [15:8] [7:0] n 00 010 data (4n-0) data (4n-1) data (4n-2) data (4n-3) n+1 00 000 - - - data (4n+1) 3. writing amount is 4 byte n + 1 byte (n: integer) a) 32bit writing for n time(s) + 2 byte writing for once at the end f_hwdatas no. of writing f_haddrs[1:0] f_hsizes[2:0] [31:24] [23:16] [15:8] [7:0] n 00 010 data (4n-0) data (4n-1) data (4n-2) data (4n-3) n+1 00 001 - - data (4n+2) data (4n+1) b) 32 bit writing for n time(s) + 1 byte writing for twice at the end f_hwdatas no. of writing f_haddrs[1:0] f_hsizes[2:0] [31:24] [23:16] [15:8] [7:0] n 00 010 data (4n-0) data (4n-1) data (4n-2) data (4n-3) n+1 00 000 - - - data (4n+1) n+2 01 000 - - data (4n+2) -
24-59 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 4. writing amount is 4 byte n + 3 byte (n: integer) a) 32 bit writing for n time(s) + 1 byte writing for 3 times at the end f_hwdatas no. of writing f_haddrs[1:0] f_hsizes[2:0] [31:24] [23:16] [15:8] [7:0] n 00 010 data (4n-0) data (4n-1) data (4n-2) data (4n-3) n+1 00 000 - - - data (4n+1) n+2 01 000 - - data (4n+2) - n+3 10 000 - data (4n+3) - - b) 32 bit writing for n time(s) + 2 byte writing for once + 1 byte writing for once at the end f_hwdatas no. of writing f_haddrs[1:0] f_hsizes[2:0] [31:24] [23:16] [15:8] [7:0] n 00 010 data (4n-0) data (4n-1) data (4n-2) data (4n-3) n+1 00 001 - - data (4n+2) data (4n+1) n+2 01 000 - data (4n+3) - - reading operation reading is proceeded in 32 bit. fraction byte to 32 bit needs judgment by software from the read of reception data volume register.
24-60 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.6.8. function link data transfer flow 24.6.8.1. setup stage in control transfer (standard command) most of the case for standard command from host, protocol engine performs all processes automatically to eliminate cpu load on the device side. cpu on the device side does not need any process; moreover, reception of these commands is not notified to the cpu (*). standard command for auto. process is as follows. clear_feature / get_configuration / get_interface / get_status / set_address / set_configuration / set_feature / set_interface (*) when set_configur ation/set_interface is received, intsetconf and intachg occur. figure 24-5 setup stage in control transfer (standard command process) (1) setup state is received from phy i/f. (2) its command is analyzed by protocol engine. when setup to own device is correct and the command is for auto. proces s, writing to endpoint bu ffer is not proceeded, no r status report/interrupt occurrence to register. (3) when setup to own device is correct, protocol engine transfers ack handshake from phy interface. if the setup is not for own device or error is found, the transfer is not carried out (timeout.) protocol en g ine internal bus internal bus i/f endpoint fifo control and status register cpu i/f (1) cpu bus utmi (usb) (2) ( 3 )
24-61 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.6.8.2. setup stage in control transfer (class command, vender command, and a p art of standard command (get_descriptor/set_des criptor/synch_frame)) class command, vender command, and a part of standard command (get_descriptor / set_descriptor / synch_frame) from host are written to endpoint0 out transfer buffer. figure 24-6 setup stage in control transfer (class command, vender co mmand, and a part of standard command processes) (1) setup state is received from phy i/f. (2) its command is analyzed by protocol engine. when setup to own device is correct and the command is not for auto. process, the data in setup st age process is written to endpoint0o buffer. (3) when setup to own device is correct, protocol engine transfers ack handshake from phy interface. if the setup is not for own device or error is found, the transfer is not carried out (timeout.) at the time setup stage is received properly, follo wing status report and display become valid by the report from protocol engine. ? intready0o :set to "1" ? ready0o :set to "1" ? rxsize0o :valid value ? intsetup :set to "1" (4) data reading becomes valid by cpu interface (setting such as "1" writing to ready0o for the next transfer may be required according to need.) protocol engine internal bus internal bus i/f endpoint fifo control and status register cpu i/f (1) cpu bus utmi (usb) ( 3 ) (2) (4)
24-62 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.6.8.3. status stage in control transfer (standard command) standard command (shown below) except get_descriptor/set_descriptor/synch_frame is all processed by protocol engine, and status register in the device does not change. moreover interrupt signal is not asserted. clear_feature / get_configuration / get_interface / get_status / set_address / set_configuration / set_feature / set_interface figure 24-7 status stage in control transfer (standard command process) control writing (1) in token is received from phy i/f. (2) when in token to own device is correct as a result of its analysis by protocol engine, 0 byte data is sent to phy i/f. if the token is incorrect, process becomes timeout. (3) ack handshake is received from host. control reading (1) out token and 0 byte data are received from phy i/f. (2) when the transfer to own device is correct as a result of their analysis by protocol engine, ack handshake is sent to phy i/f. protocol engine internal bus internal bus i/f endpoint fifo control and status register cpu i/f (1) cpu bus utmi (usb) (2) (3)
24-63 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.6.8.4. status stage in control transfer (class command, vender command, and a p art of standard command (get_descriptor/set_des criptor/synch_frame)) figure 24-8 status stage in control transfer (class command, vender command, and a part of standard command processes) control writing (1) in token is received from phy i/f. (2) when in token to own device is correct as a result of its analysis by protocol engine, it proceeds followings according to ufepc0 and ufeps0 registers setting. 1) stall = "1" stall is sent to phy i/f. 2) ready0i = "0" (data is not written, but "1" needs to be written to ready0i) 0 byte data is sent to phy i/f, then intready0i is set to "1" when ready0i is set to "1". 3) ready0i = "1" nack is sent to phy i/f. (3) in the case of item 2 of (2), ack handshake is received from host (setting such as writing "1" to ready0i for the next transfer is required according to need.) (4) protocol engine internal bus internal bus endpoint fifo control and status register cpu i/f (1) cpu bus utmi (usb) (2)
24-64 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller control reading (1) out token and 0 byte data are received from phy i/f. (2) when the transfer to own device is correct as a result of their analysis by protocol engine, it proceeds followings according to ufepc0 and ufeps0 registers setting. 1) stall = "1" stall is sent to phy i/f. 2) ready0o = "0" 0 byte data is received from phy i/f, and ack is sent to the i/f. then intready0o is set to "1" when ready0o is set to "1". rxsize0o shows valid value is "0". 3) ready0o = "1" nack is sent to phy i/f (setting such as writing "1 " to ready0o for the next transfer is required according to need.)
24-65 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.6.8.5. control (data stage)/bulk out transfer transfer data is written to endpoint out fifo and read from cpu i/f. reading from the i/f is also available for transfer to en dpoint with dma interface. figure 24-9 control (data stag e)/bulk out transfer processes (1) out token and data reception start from phy i/f. (2) when out token is analyzed by protocol engine, and it is correct endpoint transfer to own device, reception endpoint address is outp ut to internal bus. then outpu t to the internal bus of the reception data starts. (3) followings are processed with the setting of ufepcx and ufepsx registers (x = applied endpoint bulkinterrupt) at the time of (2). 1) stall = "1" after data reception from phy i/f, stall is sent to the i/f. 2) readyxo = "0" (note) data is received from phy i/f and written to endpoint buffer in series. 3) readyxo = "1" (note) after data reception from phy interf ace, nack is sent to the i/f. note) in the case of double buffer's endpoint, step 2 and 3 may be different by 2 phases of buffer data's reception status even though readyxo = "1" of the data is able to be read. ? when 2 phases are able to be received (readyxo = "0"), item 2 is proceeded. after the reception, ack is sent to phy i/f. ? when 1 more phase is able to be received (readyxo = "1"), item 2 is proceeded. after the reception, nyet is sent to phy i/f. ? when 2 phases are already received (r eadyxo = "1"), item 3 is proceeded. after the reception, nack is sent to phy i/f. (4) protocol engine internal bus internal bus endpoint fifo control and status register cpu i/f (1) cpu bus utmi (usb) (3) (2)
24-66 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller (4) when data is received 1) when data is not normal, status of (3) becomes timeout, not ack/nyet/nack. in this case, writing data to endpoint buffer is deleted. moreover, intreadyxo and readyxo are not set to "1". 2) although the data is normal, intreadyxo is set to "1" when readyxo is set to "1" after data reception. moreover, reception data volume is displayed as valid value so that slave i/f is able to detect after the reception. in addition, endpoint with master i/f is able to read data from the i/f after data reception. (note) in the case of double buffer endpoint, timing of setting "1" to intreadyxo and readyxo as well as valid timing of rxsizexo may change accord ing to the reading status of the previously received data. (note) setting such as writing "1" to ready0o for th e next transfer is required according to need.
24-67 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.6.8.6. control (data stage)/bulk/interrupt in transfer writing data from local bus i/f to endpoint in transfer fifo is forwarded to usb bus protocol engine. figure 24-10 control (data stage)/bu lk/interrupt in transfer processes (1) before starting transmission data's in transfer, wr ite data to in transfer endpoint fifo in writing operation from cpu i/f or dma i/f. (2) in token is received from phy i/f. (3) when in token is analyzed by protocol engine, and it is correct endpoint transfer to own device, transmission endpoint address is ou tput to internal bus. then output to the internal bus of the reception data starts. (4) followings are processed with the setting of ep cx and epsx registers (x = applied endpoint bulkinterrupt) at the time of (3). 1) stall = "1" protocol engine sends stall to phy i/f. 2) readyxi = "0" (note) protocol engine reads data from endpoint buffer in series, then sends it to phy i/f. 3) readyxi = "1" (note) nack is sent to phy i/f. (note) in the case of double buffer endpoint, pr ocess may change according to the transmission status of the 2 phase buffer data though readyxi = "1" of data is writable. ? when 2 phases are sendable (read yxi = "0"), item 2 is proceeded. then the data is sent to phy i/f. ? when 1 more phase is sendable (readyxi = "1"), item 2 is proceeded. then the data is sent to phy i/f. ? when both 2 phases are already sent (readyxi = "1"), item 3 is proceeded. nack is send to phy i/f. (1) protocol engine internal bus internal bus i/f endpoint fifo control and status register cpu i/f (2) cpu bus utmi (usb) ( 4 ) (3) (5)
24-68 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller (5) followings should be processed according to reception status on usb host side. 1) reception is processed properly on usb host side ack is received by phy i/f. after the reception, intreadyxi is set to "1" when readyxi is set to "1" so that cpu i/f is able to detect the completion of the reception. after the data transfer, dreq is asserted in endpoint with dma i/f that data is able to be written from the interface. 2) reception is not processed pr operly on usb host side protocol engine becomes timeout and it leads to j udgment that transfer is invalid with timeout. then reading pointer of transmission endpoint buffer is returned to the state before the transmission, and the same data is used for the next in transfer. in this case, intreadyxi and readyxi are not set to "1".
24-69 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.6.9. reception's basic operation (d at a reading by slave i/f) basic operation of reception is as follows. 1. when reception data is already written to receptio n endpoint (bulkinterrupt) and is readable, the data is read. then completion of reading is in structed by writing "1" to readyxo (x = applied endpoint bulkinterrupt.) this instruction also indicates permission of r eceiving the next packet. 2. when the next packet reception is permitted, data is received to applied endpoint (bulkinterrupt) buffer unless out token from usb host and the next data do not have error. 3. when reception is completed, intreadyxo is set to "1"; at the same time, readyxo is set to "1". moreover, rxsizexo displays reception data volume as valid value. the flow shows example of opera tion including reception process. applied endpoint is intready reception data volume check reception data reading interrupt process except reception no yes interrupt occurs no applied endpoint is received applied endpoint ready bit is "1" writing to applied endpoint ready bit no no ye s ye s ye s figure 24-11 usb reception operation flow example
24-70 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.6.10. reception operation and status relation of reception operation and intread yxo, readyxo, rxsizexo is shown below. figure 24-12 relation of reception oper ation, intreadyxo, readyxo, and rxsizexo end of reception notification to cpu i/f "0" writing to intreadyxo. or, reading start from endpoint readyxo intreadyxo rxsizexo "1" writing to readyxo (reading completion instruction) when another phase of double buffer endpoint is already received at the end of reading operation, "1" is set to intreadyxo and readyxo again immediately after reading com p letion instruction. valid reading process reception receiving another phase of double buffer reception completion of another phase of double buffer endpoint is not notified until reading completion of the previous packet is instructed.
24-71 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.6.11. basic transmission operation (data writing by the slave i/f) basic operation of transmission is as follows. 1. write transmission data to transmission endpoint (b ulkinterrupt) buffer, if writable. then write "1" to readyxi (x = applied endpoint bulkinterr upt) and instruct completion of writing. this instruction also indicates transmission permission of the packet. 2. when the packet transmission is permitted, it is sent as the next data of in token from usb host. 3. when transmission ends without error, intreadyxi is set to "1"; at the same time, readyxi is set to "1". the flow shows example of opera tion including transmission process. write transmission data write "1" to applied endpoint ready bit interrupt process except transmission applied endpoint's intready interrupt start transmission (in transfer) ye s ye s no no applied endpoint ready bit is 1 ye s interrupt occurs no ye s figure 24-13 usb transfer operation flow example
24-72 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.6.12. transmission operation and status relation of transmission operation and intreadyxi and readyxi is shown below. figure 24-14 relation of transfer operation, intreadyxi, and readyxi end of transmission notification to cpu i/o "0" writing to intreadyxi or, start writing to endpoint buffe r readyxi intreadyxi writing "1" to readyxi (writing completion instruction) when another phase of double buffer endpoint is already sent at the end of writing operation, "1" is set to intreadyxi and readyxi again immediately after writing completion instruction. writing process transmission sending another phase of double buffer transmission completion of another phase of double buffer endpoint is not notified until writing completion of the previous packet is instructed.
24-73 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.6.13. notice of control transfer process following should be noted to process device request (*) which does not respond automatically in the control transfer. (*) set_descriptor/get_d escriptor/synch_frame, class command, and vendor command 1. end point0o (epob0) is initialized at the beginning of setup stage of the control transfer, and 8 byte of setup stage data is written to ufepob0 after initialization. 2. when 8 byte of setup stage data in the control tran sfer is written to ufepob0, intsetup bit is set and ufepob0 temporarily masks access from cpu. after in tsetup bit is cleared, intready0o is set and access from cpu is able to be performed properly. 3. the period of setting intsetup b it is initialization period of end point0i (ufepib0 ) that access from cpu is masked. after intsetup b it is cleared, access from cpu is able to be performed properly. clearing intsetup bit enables writing to uf epib0; and intready0i is set as well. time ufepob0 invalid data reading period ufepib0 writing invalid period usb setup-token data ack setup stage data ufepob0 initialization signal (internal signal) ufepob0 contents intsetup intready0o initial state ufepib0 contents ufepb initialization signal (internal signal) intready0i clear intsetup figure 24-15 process for device request which do es not respond automatica lly in control transfer this operation is to correspond to "w hen setup is received before comple ting the previous control transfer, it is deleted and the new setup should be proceeded" of usb standard 5.5.5 (such condition does not occur with proper usb host.) always receive new setup data with this operation, and the data in in direction buffer (epib0) is initialized which prevents sending response data to old control tran sfer when in transfer is requested after new setup. since initialization state of buffer (epib0) continues until intsetup release, writing response data for old control transfer is also prevented when se tup is received in buffer (epib0) writing. for that reason, delete previous transfer processes and response process should be carried out every time setup is received when intsetup inte rrupt occurs in control transfer.
24-74 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.6.14. dmac operation (data transfer by master interface) in this macro, dmac (master interface) is mounted to endpoint bulk1 and bulk2 which are able to use dmac by setting dma (setting to register ufepdc) and dmac (register ufepdcn/ufepdan/ ufepdsn) of function link. dma mode access to endpoint buffer is able to pro cess through master interface signal pin. for null packet transmi ssion/reception, slave interface should be used. for dmac mode, the next packet transmission/r eception are able to pro ceed only by writing/reading necessary transfer volume from function link dm ac register. reading/writing completion notice (ready bit control) is no t required. slave interface is used for null packet transmission/reception. in transfer when packet is in writing process to endpoint buff er, write "1" to dmamode* after packet data writing is completed, then write "1" to ready*i bit. out transfer when packet is in reading process from endpoint buffer, write "1" to dm amode* after packet data writing is completed, then write "1" to ready*o bit. simultaneous access to the same endpoint buffer from slave i/f and master i/f is prohibited.
24-75 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller table 24-4 dma mode and normal mode dma mode (*1) normal mode in transfer endpoint dmareq[*] bit operation of ufepds register endpoint[*] bit outputs ready*i bit value of ufeps* register since endpoint* setting is for in transfer. ready*i bit is asserted in configured state when data is writable to endpoint*. same as on the left out transfer endpoint dmareq[*] bit operation of ufepds register dmareq[*] bit outputs ready*o bit value of ufeps* register since endpoint* setting is for out transfer. ready*o bit is asserted in configured state when data is readable from endpoint*. same as on the left in transfer endpoint transfer request operation to dmac transfer request to dmac occurs when the state is configured and mskdmareq[*] is "0" as well as data is writable to endpoint* buffer. same as on the left out transfer endpoint transfer request operation to dmac transfer request to dmac occurs when the state is configured and mskdmareq[*] is "0" as well as data, except nullpacket is readable from endpoint* buffer. same as on the left out transfer endpoint reception notice operation of nullpacket reception is notified when nullpacket reception information is ready to be read to endopoint* buffer in the condition that the state is configured and mskdmareq[*] bit is "0". after the notice, dmac clears the endpoint buffer automatically. same as on the left ready bit control reception/transmission of the next packet is able to proceed by reading/writing data from dmac interface so that reading/writing notification (ready bit control) is not required. do not process ready bit control in the dmac mode. reading/writing completion notice (ready bit control) should be issued every time reading/writing a packet is completed, ot herwise the next packet is not received/written. intready bit operation when writing/re ading process becomes available, intready bit is asserted. it is cleared automatically by accessing to endpoint buffer with master i/f or slave i/f. in order to control asserting c_intr by asserting intready bit in dmac transfer, set "1" to mskready bit of ufepc * register. when writing/reading processes are enabled, intready bit is asserted. intready bit is cleared automatically by accessing to endpoint buffer with master i/f or slave i/f. other endpoint interrupt signal operation when set requirement is met, endpoint interrupt signal bit is asserted. same as on the left (*1) refer 24.6.14.2, " dma interface" for reading/writing operation of dmac mode.
24-76 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.6.14.1. 2 modes in dma mode dma operation in this macro has 2 modes. 1) total transfer volume setting mode this mode notifies interrupt when data reaches to th e certain transfer volume w ith setting transfer volume of whole transaction (the amount of usb transfer by multiple packet is identified), and masks dma request to end the process. 2) normal mode unlike total transfer volume mode, this mode r eads/writes data from dm a interface without setting transfer volume. 24.6.14.2. dma interface dma interface operation is as follows. 1) reception endpoint (bulk): dma reading operation packet data volume is able to be confirmed by ufepds * register of dmac. a. start of dma reading operation when packet reception is completed in the dma m ode, dma request and number of byte are notified to dmac. (if they are masked by mskdmareq of function link register ufepdc, they are not notified.) b. dma reading operation when epde bit of applied dmac's ufepdc* regi ster is "1" during dma request is notified, transfer starts by master i/f. c. end of dma reading operation when 1 packet of data is read, dma request to dmac is cleared until reception of the next packet is completed. with completion of the next packet, reading by dma starts again. 2) transmission endpont: dma writing operation a. start of dma writing operation when packet data writing is enabled in the dma mode, applied dma's request is notified (if it is masked by mskdmareq of function link register ufepdc, it is not notified.) b. dma writing operation when epde bit of ufepdc* register of dmac is "1" while dma request is notified with setting transfer size in the ufepds* register , transfer starts by master i/f. if transfer size set to the ufepds* register exceeds max. transfer volume of 1 packet, it is divided into multiple max. packet and the last shortpacket. c. end of dma writing operation when master i/f receives the transfer size set to the ufepds* register, dma transfer is ended.
24-77 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.6.15. dma mode setting procedure 1) setting procedure example for normal mode figure 24-16 setting procedure example in normal mode dma mode setting dma request mask release dma writing/reading epd_irq (epdi) occurrence dma request notification yes yes no dma mode release no dmac's ufepda*, ufepds*, ufepdc* setting write ufepdc register's dmamode[*] = 1 ufepds* should be set only when dmac's startup process is in write ufepdc register's mskdmareg[*] = 0 write ufepdc register's dmamode[*] = 0
24-78 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 2) setting procedure example for total transfer volume mode out transfer ufeptc* = ufepds* + 1 in in transfer figure 24-17 out transfer example (ufeptc*=ufepds*+1 in in transfer) dma mode setting dma request mask release dma writing/reading int dend interrupt occurrence epd_irq (epdi) interrupt occurrence dma request notification no dma mode release total count transfer volume setting no yes write ufepdc register's dmamode[*] = 1 dmac's ufepda*, ufepds*, ufepdc* setting (eptc* = epds* + 1) write total count transfer volume setting value to ufeptc* register boot dmac only the case of in transfer, ufepds* should be set write ufepdc registers mskdmareq[*] = 0 yes write ufepdc register's dmamode[*] = 0
24-79 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller ufeptc* > ufepds* + 1 in in transfer (maxpacketsize x n - 1 at the first ufepds* setting) figure 24-18 out transfer example (for ufeptc*>ufepds*+1 in in transfer, maxpacketsize n?1 is set at the 1st ufepds* setting) dma mode setting dma request mask release dma writing/reading intdend interrupt occurrence dma request notification no dma mode release total count transfer volume setting no yes write ufepdc register's dmamode[*] = 1 dmac's ufepda*, ufepds*, ufepdc* setting (eptc* > epds* + 1) write total count transfer volume setting value to ufeptc* register boot dmac write ufepdc register's mskdmareq[*] = 0 yes epd_irq (epdi) interrupt occurrence no yes ufeptc* reading (check remaining transfer volume) dmac's ufepda*, ufepds*, ufepdc* setting (eptc* = epds* + 1)
24-80 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller ufeptc* < ufepds* + 1 in in transfer (maxpacketsize x n at the first ufepds * setting) figure 24-19 out transfer example (for ufeptc* 24-81 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.6.16. null packet transmission/reception null packet transmission/reception met hod excluding in the control transfer status stage is shown below. for the status stage, refer to " 24.6.8.3" and " 24.6.8.4". 1) null packet transmission (in transfer) write "1" to ready*i of corresponding endpoint without writing data. then in transfer with "0" byte is permitted. null packet is sent to in token from the phy interface. 2) null packet reception (out transfer) endpoint without master i/f when null packet is received, ready is asserted and the number of reception byte shows "0" byte. ready is cleared by writing "1". endpoint with master i/f when null packet is received, ready is asserted and it is notified to dmac. th en dmac sets epnf of its ufepdc*. if epne is already set, interrupt occurs, and the null packet informati on received in endpoint buffer at the same time is automatically cleared.
24-82 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.6.17. spr mode and spdd mode 24.6.17.1. spr mode buffer a buffer b buffer a buffer b buffer b usb operation (time) buffer a buffer b short packet reception maxsize packet reception maxsize packet reading short packet reading macro double buffer operation dma i/f operation (time) (2) (1) (3) (4) (5) short packet reading "reception side" of double buffer => "reading side" or, "reading side" => "reception side" switch dma request output timing from macro handshake input to macro interrupt output from macro (internal status) dma request mask's release process to macro data flow usb operation (time) dma i/f operation (time) (1) (2) (3) (4) short packet reception figure 24-20 spr mode operation (1) shortpacket reception the case that reading of previously received packet is not completed at the completion of reception. (2) reading operation of the previous packet (3) intspr occurrence intspr occurs when reading the previous packet is completed. when it is set to "1", dma request is masked in this step (it is set to mskdmareq = 1.) therefore, dma request is not output until the mask of the request is released (it is reset to mskdmareq = 0.) (4) mask release of dma request dma request is unmasked (it is reset to mskdmareq = 0) and dma request is notified. (5) shortpacket reading (1) shortpacket reception the case that reading of previously received packet is completed at the completion of reception. (2) intspr occurrence intspr occurs when r eception of shortpacket is completed. when enspr is set to "1", dma request is masked in this step (it is set to mskdmareq = 1.) therefore, dma request is not output until the mask of the request is released (it is reset to mskdmareq = 0.) (3) mask release of dma request when dma request is unmasked (it is reset to mskdmareq = 0), the request is notified. (4) shortpacket reading reading of previously received packet is not completed at the time of shortpacket reception reading of previously received packet is completed at the time of shortpacket reception.
24-83 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.6.17.2. spdd mode buffer b buffer a buffer b buffer a buffer b usb operation (time) short packet reception maxsize packet reception maxsize packet reading short packet reading macro double buffer operation dma i/f operation (time) (2) (3) buffer a (4) maxsize packet reading buffer a buffer b usb operation (time) short packet receptio maxsize packet reception maxsize packet reading short packet reading macro double buffer o p eration dma i/f operation (time) (2) (1) (5) (3) buffer a (4) maxsize packet reading buffer b buffer a buffer b maxsize packet reception (5) (1) figure 24-21 spdd mode operation (1) shortpacket reception (2) shortpacket reading (3) intspdd occurrence intspdd occurs when reading shortpacket is completed. when enspdd is set to "1", dma request is masked in this step. (it is set in mskdmareq = 1.)therefore, dma request is not output until the mask of the request is released (it is reset to mskdmareq = 0) the operation in this step does not relate to reception of the next packet. (4) mask release of dma request when dma request is unmasked (it is reset to mskdmareq = 0) and the request is notified. (5) reading of the next packet. the next packet's reception is not completed when shortpacket reading is completed. the next packet's reception is completed when shortpacket reading is completed.
24-84 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.6.17.3. mode and dma interface timing 1) normal mode (neither spr nor spdd mode) usb usb macro (function link) max size packet max size packet short size packet max size packet short size packet time max size packet dma request handshake dma i/f figure 24-22 dma interface timing in norm al mode (neither spr mode nor spdd mode)
24-85 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 2) spr mode usb usb macro (function link) max size packet max size packet short size packet max size packet short size packet time max size packet mskdmareq* setting intspr asserting mskdmareq* reset (firm) note: mskdmareq* setting and intspr asserting should be processed at the same time dma request handshake dma i/f mskdmareq* reset (firm) mskdmareq* setting intspr asserting figure 24-23 dma interface timing in spr mode
24-86 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 3) spdd mode usb usb macro (function link) max size packet max size packet short size packet max size packet short size packet time max size packet mskdmareq* setting intspdd asserting note: mskdmareq* setting and intspr asserting should be processed at the same time dma request handshake dma i/f mskdmareq* reset (firm) mskdmareq* setting intspdd asserting mskdmareq* reset (firm) figure 24-24 dma interface timing in spdd mode
24-87 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.6.18. operation timing of empty* status bit usb usb macro (function link) time dma request handshake empty * dma i/f figure 24-25 empty* status bit's operation timing
24-88 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.6.19. pull-up resistor internal resistor this macro contains pull-up resistance connected to d+ signal. when extrpu bit of the customcnt register is set to "0", internal pull-up resistor becomes valid and it is controlled by its control signal. initial value of extrpu bit is "0". when it is set to "1", internal pull-up resistor becomes invalid. control circuit d+ extrpu phy block function link usb_hsdp chip usb macro figure 24-26 internal pull-up resistor's control part for d+ signal
24-89 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.6.20. analog power supply control and analogue power down control internal link suspend/resume control circuit register physusp phy module analog pll driver receiver bias circuit core power supply analog power supply 1.2v 3.3v (avdp/avdf2) (avdb/avdf1) protection circuit to irregular output of analog output signal when analog power supply is off register: suspend analog module's pd pin te st i n pu t phy module: anpd phy module: suspend figure 24-27 analog power suppl y and analog power down control operation stop of analog module phy module's suspend signal becomes active when state becomes suspend in usb operation or register physusp bit is set to "1". when suspend signal of phy module becomes active, analog block shifts to power down mode and operation stops.
24-90 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.6.21. control for when configur ation setting value (wv alue) receives "0" setconfiguration command when setconfiguration command with "0" configuration setting value (wvalue) is received and this macro's configuration setting value is changed from "1" to "0", endpoint1~3 become invalid that reception/transmission are unable to be proceeded. in this time, interrupt signal of endpoint1~3 and dma request are not cleared automatically so that they should be manually reset as shown below. if they are not reset, interrupt signal and dma request are continuously notified. since intnack(*) and intclstall(*) interrupt signals do not have clear condition which is by "1" writing in init* bit, they should be cleared by writing "0". other statuses do not need to write "0" to clear since "1" writing to int* bit clears them. setconfiguration command reception (detecting intsetconf interrupt) yes no write "1" to init(*) bit of ufepc* register write "0" to intsetconf of ufdvs register reading ufdvs register conf[3:0] = 4?h0 write "0" to intnack(*) bit of ufeps* register write "0" to intclstall(*) of ufeps* register reading ufepc* register init = 0 no yes figure 24-28 operation flow at receiving "0" se tconfiguration command in configuration setting value (wvalue)
24-91 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.6.22. total count transfer setting value and transfer volume setting value of external d mac when using total count transfer at in transfer, correlation of tran sfer volume setting of total count (ufeptc* register setting value) and dmac (ufe pds* register setting value) is as follows. table 24-5 relation of total count transfer volume setting value (ufeptc* register setting value) and dmac transfer setting value (ufepds* register setting value) (using total count transfer in in transfer) transfer volume possible ufeptc* setting possible ufepds* setting ufeptc* register setting value < ufepds* setting value + 1 maxpacketsize n short can be set only at the end total transfer volume - 1 ufeptc* register setting value = ufepds* setting value + 1 total transfer volume total transfer volume - 1 ufeptc* register setting value > ufepds* setting value + 1 total transfer volume maxpacketsize n - 1 short can be set only at the end when stopping transfer with setting different tr ansfer volume between ufeptc* and ufepds*, set register that transfer volume becomes integral multip le of maxpacketsize in order to stop the transfer between packets. short packet is able to be transferred on ly at the last packet of all transfers.
24-92 fujitsu semiconductor confidential MB86R01 lsi product specifications usb function controller 24.6.23. interrupt factor (except usb bus reset) phenomenon after usb bus reset when bus reset is performed while config value is "1", followings might occur. ? interruption factor (except usb bus reset) occurs after usb bus reset ? cause of the interrupt is intempty of each endpoint ? interrupt is not output since in terrupt is masked in bus reset in this case, proceed following processes: measures by software measures 1: after bus reset's interrupt start signal (intusbrstb) is detected, write "0" to intempty* signal of the ufeps* (* = 1~3) register to clear. measures 2: after bus reset's interrupt start signal (intusbrst b) is detected, write "1" to init* bit of the ufepc* (* = 1~3) register.
25-1 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) 25. ide host controller (ide66) this chapter describes function and operation of ide host controller (ide66.) 25.1. outline ide66 corresponds to ata/atapi-5 and interfaces with ide storage de vice such as hard disk and cd- rom. 25.2. feature ide66 has following features: ? supporting primary ide channel (based on ide standard, up to 2 drives can be connected with 1 channel corresponding to master/slave) ? supporting pio mode (mode 0 ~ 4) ? supporting transfer with ultra dma mode (mode 0 ~ 4) ? ide signal output timing change with register setting ? direct access to ide drive's regi ster with program i/o access ? auto. generating crc at ultra dma transfer ? max. 66mbyte/sec. (ultra dma66) of transfer when ahb clock is 66mhz ? fifo for ultra dma (transmission: 512 byte 2, reception: 512 byte 2) note: neither singleword dma nor multiword dma transfer mode of ide is supported.
25-2 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) 25.3. block diagram figure 25-1 shows block diagram of ide66. ahb slave i/f txfifo (ide66_ram32b256wtx ) rxfifo (ide66_ram32b256wrx ) ahb bus pio control block module (ide66_cntl) f_ide66 macro ide66 module ide storage master ahb master i/f (ide66_ahbmw) ide storage slave dma control block module (ide66_dmacnt) figure 25-1 block diagram of ide66 detail of internal block ide66_cntl this module has ahb slave i/f and controls pio access to f_ide66 macro. ide66_dmacnt this module controls ultra dma transfer, ahb master i/f control, and register group including dma setting. ide66_ahbmw this is general-purpose module that equi ps master function to access to ahb bus. ide66_ram32b256wrx this module is dma data in burst (data reception) fifo. ide66_ram32b256wtx this module is dma data out burst (data transmission) fifo. f_ide66 this module is controller macro which interfaces with ide storage device.
25-3 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) 25.4. related pin ide interface uses following pins which are common with other functions. to use the pin, set mpx_mode_4[1:0] = 00 to pin mpx select register of chip control module (ccnt) to select pin function on ide side. in addition, this pin is for 3.3v, not 5v. table 25-1 ide66 related pin pin direction qty. description ide_xdcs[1:0] out 2 ide chip select (cs0-, cs1-) output. active low. ide_da[2:0] out 3 ide device address (da[2:0]) output ide_xdasp in 1 ide device activ e (dasp-) input. active low. ide_dd[15:0] in/out 16 ide device data (dd[15:0]) input/output. low order 8 bits become valid at register transfer, and all 16 bits become valid at data transfer. ide_xdior out 1 ide device i/o read (dior-) output. at ultra dma data in burst (hdmar dy-) and ultra dma data out burst (hstrobe.) ide_xdiow out 1 ide device i/o write (diow-) output. at ultra dma data burst (stop.) ide_xddmack out 1 ide device dma acknow ledge (dmack-) output. active low. ide_ddmarq in 1 ide device dma request (dmarq) input. ide_dintrq in 1 ide interrupt (intrq) input. dintrq is reflected to interrupt output signal of ide interface unit as it is. ide_diordy in 1 ide i/o channel ready (iordy) input. at ultra dma data in burst (dstro be) and ultra dma data out burst (ddmardy-.) ide_xcblid in 1 ide cable id (cblid-) input. active low. it is used for ide cable distinction (40 pin or 80 pin.) ide_xdreset out 1 ide reset (reset-) output. active low. reset is output to ide interface unit as it is, and the pin is synchronized with unit clock and negated. moreover, assertin g and negating can be controlled by register setting (icmr [6].) ide_csel out 1 ice cable select (csel) output. ide_xiocs16 in 1 ide's 16 bit i/o (iocs16-) input. active low. 25.5. supply clock ahb clock is supplied to ide interface unit. refer to "5. clock reset generator (crg)" for frequency setting and control specification of the clock.
25-4 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) 25.6. register this section describes ide interface register. 25.6.1. register list ide interface unit equips 1 chan nel and register shown in table 25-2. access to the first 16 word (fff 20000h ~ fff2001ch and fff20038h) is access to ide drive register; therefore, status of these addresse s is not maintained in the unit. the access from fff20040h or later address should be the access to internal register. for accessing to cs0/cs1 registers of other than cs0dat register (fff20 000h), only low order 8 bits out of 32 bit in the internal register become valid; in addition, only low order 16 bits become valid for cs0dat register in cs0 register. refer to ata/at api-5 specifications for detail of each register, cs0 (command block register) and cs1 (control block register.) table 25-2 ide66 register list address register description fff20000h cs0dat cs0 data register fff20004h cs0er/cs0ft cs0 erro r/features register fff20008h cs0sc cs0 sector count register fff2000ch cs0sn cs0 sector number register fff20010h cs0cl cs0 cylinder low register fff20014h cs0ch cs0 cylinder high register fff20018h cs0dh cs0 device head register fff2001ch cs0st/cs0cmd cs0 status/command register fff20020h ? fff20037h reserved access prohibited fff20038h cs1as/cs1dc cs1 alternate st atus/device control register fff2003ch reserved access prohibited fff20040h idedata data register fff20044h? fff20047h reserved access prohibited fff20048h ideptcr pio timing control register fff2004ch idepasr pio address setup register fff20050h ideicmr ide command register fff20054h ideistr ide status register fff20058h ideiner interrupt enable register fff2005ch ideinsr interrupt status register fff20060h idefcmr fifo command register fff20064h idefstr fifo status register fff20068h idetfcr transmission fifo count register fff2006ch reserved access prohibited fff20070h iderfcr reception fifo count register fff20074h ? fff200c7h reserved access prohibited fff200c8h ideutcr udma timing control register fff200cdh ? fff200cfh reserved access prohibited fff200d0h ideucmr udma command register
25-5 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) address register description fff200d4h ideustr udma status register fff200d8h ? fff2014fh reserved access prohibited fff20150h iderrcc rxfifo rest count compare value fff20154h ideutc1 ultra dma timing control 1 fff20158h ideutc2 ultra dma timing control 2 fff2015ch ideutc3 ultra dma timing control 3 fff20160h ? fff201ffh reserved access prohibited fff20200h idestatus dma status register fff20204h ideint interrupt register fff20208h ideintmsk interrupt mask register fff2020ch idepioctl pio access control register fff20210h idedmactl dma control register fff20214h idedmatc dma transfer control register fff20218h idedmasad dma source address register fff2021ch idedmadad dma destin ation address register
25-6 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) description format of register following format is used for description of register?s each bit in " 25.6.2 cs0 data register (cs0dat)" to " 25.6.39 dma destination address register (idedmadad)". address base address + offset bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r/w initial value bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r/w initial value meaning of item and sign address address (base address + offset address) of the register bit bit number of the register name bit field name of the register r/w attribution of read/write of each bit field ? r0:read value is always "0" ? r1: read value is always "1" ? w0: write value is always "0", and write access of "1" is ignored ? w1: write value is always "1", and write access of "0" is ignored ? r: read ? w: write initial value each bit field?s value after reset ? 0: value is "0" ? 1: value is "1" ? x: value is undefined
25-7 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) 25.6.2. cs0 data register (cs0dat) address fff2_0000 + 000h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name data[15:8] data[7:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x x this register is data port where low order 16 bits become valid. spec of ide device connected to mb86r0 1 is applied to contents of this register (field configuration), therefore check ide device spec. to be connected. 25.6.3. cs0 error register (cs0er) address fff2_0000 + 004h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) wp mc idnf mcr abrt nm med r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r r r r r r initial value 0 0 0 0 0 0 0 0 x x x x x x x x spec of ide device connected to mb86r0 1 is applied to contents of this register (field configuration), therefore check ide device spec. to be connected. 25.6.4. cs0 features register (cs0ft) address fff2_0000 + 004h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) features r/w r/w r/w r/w r/w r/ w r/w r/w r/w w w w w w w w w initial value 0 0 0 0 0 0 0 0 x x x x x x x x spec of ide device connected to mb86r0 1 is applied to contents of this register (field configuration), therefore check ide device spec. to be connected.
25-8 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) 25.6.5. cs0 sector count register (cs0sc) address fff2_0000 + 008h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) sector count[7:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 x x x x x x x x spec of ide device connected to mb86r0 1 is applied to contents of this register (field configuration), therefore check ide device spec. to be connected. 25.6.6. cs0 sector number register (cs0sn) address fff2_0000 + 00ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) sector number[7:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 x x x x x x x x spec of ide device connected to mb86r0 1 is applied to contents of this register (field configuration), therefore check ide device spec. to be connected. 25.6.7. cs0 cylinder low register (cs0cl) address fff2_0000 + 010h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) cylinder low[7:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 x x x x x x x x lba bit 7 - 0 are indicated at lba mode. spec of ide device connected to mb86r0 1 is applied to contents of this register (field configuration), therefore check ide device spec. to be connected.
25-9 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) 25.6.8. cs0 cylinder high register (cs0ch) address fff2_0000 + 014h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) cylinder high[7:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 x x x x x x x x lba bit 15 - 8 are indicated in lba mode. spec of ide device connected to mb86r0 1 is applied to contents of this register (field configuration), therefore check ide device spec. to be connected. 25.6.9. cs0 device/head register (cs0dh) address fff2_0000 + 018h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) l (reserved) dev head[3:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 x x x x x x x x bit[3:0] indicates lba bit 23 - 16 at lba mode. spec of ide device connected to mb86r0 1 is applied to contents of this register (field configuration), therefore check ide device spec. to be connected. 25.6.10. cs0 status register (cs0st) address fff2_0000 + 01ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) bsy drdy df dsc drq (reserved) err r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r r r r r r initial value 0 0 0 0 0 0 0 0 x x x x x x x x contents of this register (field configuration) is ide device specification connect ed to MB86R01, therefore check ide device spec. to be connected.
25-10 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) 25.6.11. cs0 command register (cs0cmd) address fff2_0000 + 01ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) command code[7:0] r/w r/w r/w r/w r/w r/ w r/w r/w r/w w w w w w w w w initial value 0 0 0 0 0 0 0 0 x x x x x x x x spec of ide device connected to mb86r0 1 is applied to contents of this register (field configuration), therefore check ide device spec. to be connected. 25.6.12. cs1 alternate status register (cs1as) address fff2_0000 + 038h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) bsy drdy df dsc drq (reserved) err r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r r r r r r initial value 0 0 0 0 0 0 0 0 x x x x x x x x spec of ide device connected to mb86r0 1 is applied to contents of this register (field configuration), therefore check ide device spec. to be connected. 25.6.13. cs1 device control register (cs1 dc) address fff2_0000 + 038h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) srst xien 0 r/w r/w r/w r/w r/w r/ w r/w r/w r/w w w w w w w w w0 initial value 0 0 0 0 0 0 0 0 x x x x x x x x spec of ide device connected to mb86r0 1 is applied to contents of this register (field configuration), therefore check ide device spec. to be connected.
25-11 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) 25.6.14. data register (idedat) address fff2_0000 + 040h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name data[15:8] data[7:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x x data[15:0] is 16 bit access port to access to recep tion fifo and transmission fifo. access during dma transfer on host is invalid. 25.6.15. pio timing control register (ideptcr) address fff2_0000 + 048h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) active count[3:0] recovery count[3:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit position field description bit 7:4 active count[3:0] access to ide drive register and active time of ide_xdior/ide_xdiow in pio access are defined (definition of active time is low pulse width of dior/diow.) bit 3:0 recovery count[3:0] access to ide drive register and recovery time of ide_xdior/ide_xdiow in pio access are defined (definition of recovery ti me is holding time of the address data to rising edge of ide_xdior/ide_xdiow.) please refer to " 25.7.1 active time and recovery time" for active time and recovery time setting since i nternal ahbclk input frequency should be considered not to violate ata spec. refer to " 25.7.2 example setting of pio mode register" for setting example.
25-12 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) 25.6.16. pio address setup register (idepasr) address fff2_0000 + 04ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) address setup[2:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 x x x x x 0 0 0 bit position field description bit 2:0 address setup[2:0] address setup time of ide_xdior/ide_ xdiow in pio access is defined (its definition is setup time of ide_da[2:0] and ide_xdcs[1:0] to falling edge of ide_xdior/ide_xdiow.) "000" ? 8 clocks "001" ? 1 clocks "010" ? 2 clocks "011" ? 3 clocks "100" ? 4 clocks "101" ? 5 clocks "110" ? 6 clocks "111" ? 7 clocks refer to " 25.7.2 example setting of pio mode register" for setting example.
25-13 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) 25.6.17. ide command register address fff2_0000 + 050h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) csel dreset rst (reserved) *1 *2 *3 *4 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 *1: interrupt clear *2: dma interface direction *3: dma interface enable *4: interrupt enable bit position field description bit 7 csel ide_csel at ide access is defined. th e setting status is reflected to ide_csel pin as it is. bit 6 dreset ide_xdreset output is asserted by writing "1". "1": ide_xdreset is asserted ("l" is output) "0": ide_xdreset is negated ("h" is output) bit 5 rst internal macro is reset by writing "1". applied range is all bl ocks except certain part in register and certain part of host interface in the block chart. "1": internal reset is asserted "0": internal reset is negated bit 4 (reserved) bit 3 interrupt clear the interrupt occurred from internal ide host controller unit is cleared by writing "1" at asserting interrupt, however, the interrupt cau sed by dintrq (interrupt input from ide device) is not cleared. bit 2 dma interface direction rewriting this bit during dma transfer is invalid. "1": from host to transmission fifo "0": from reception fifo to host bit 1 dma interface enable when dma transmission is stop, the value of this bit becomes "0". in order to proceed dma transfer again, "1" needs to be set again. current b it value is indicated at reading. "1": host side dma interface is enabled note: when ultra dma data in burst is used, do not write "0" to dma interface enable bit. transfer might not be proceeded properly. bit 0 interrupt enable ideiner register setting is validated. "1": ide host controller's interrupt is enabled "0": interrupt signal is disabled
25-14 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) 25.6.18. ide status register (ideistr) address fff2_0000 + 054h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) xcblid xiocs16 xdasp intrq r/w r/w r/w r/w r/w r/w r/w r /w r/w r/w r/w r/w r/w r r r r initial value 0 0 0 0 0 0 0 0 x x x x x x x x bit position field description bit 7:4 (reserved) bit 3 xcblid input value to ide_xcblid pin is read. bit 2 xiocs16 input value to ide_xiocs16 pin is read. bit 1 xdasp input value to ide_xdasp pin is read. bit 0 intrq input value to ide_dintrq pin is read. 25.6.19. interrupt enable register (ideiner) address fff2_0000 + 058h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) rxfifo empty txfifo empty (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 x x x x x 0 0 x bit position field description bit 7:3 (reserved) bit 2 rxfifo empty "1": the interrupt by having reception's fifo full is enabled bit 1 txfifo empty "1": the interrupt by having transmission's fifo empty is enabled bit 0 (reserved) this register setting is valid only when interrupt en able bit of ideicmr register is "1"; moreover, interrupt output signal is cleared by writing "1" to interrupt clear bit of the register.
25-15 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) 25.6.20. interrupt status register (ideinsr) address fff2_0000 + 05ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) rxfifo empty txfifo empty intrq r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r initial value 0 0 0 0 0 0 0 0 x x x x x 0 0 x bit position field description bit 7:3 (reserved) bit 2 rxfifo empty interrupt occurs by having reception's fifo become full. bit 1 txfifo empty interrupt occurs by having transmi ssion's fifo become empty. bit 0 intrq input value to ide_dintrq pin is read as it is. 25.6.21. fifo command register (idefcmr) address fff2_0000 + 060h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) txfifo clear rxfifo clear txfifo enable rxfifo enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 x x x x x x 0 0 bit position field description bit 7:4 (reserved) bit 3 txfifo clear "1": transmission fifo is cleared bit 2 rxfifo clear "1": reception fifo is cleared bit 1 txfifo enable "1": transmission fifo is enabled bit 0 rxfifo enable "1": reception fifo is enabled to proceed ultra dma transfer, be sure to set "1" to bit 0 and bit 1.
25-16 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) 25.6.22. fifo status register (idefstr) address fff2_0000 + 064h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) txfifo full rxfifo full txfifo empty rxfifo empty r/w r/w r/w r/w r/w r/w r/w r /w r/w r/w r/w r/w r/w r r r r initial value 0 0 0 0 0 0 0 0 x x x x 0 0 1 1 bit position field description bit 7:4 (reserved) bit 3 txfifo full "1": transmission fifo is full bit 2 rxfifo full "1": reception fifo is full bit 1 txfifo empty "1": tr ansmission fifo is empty bit 0 rxfifo empty "1": reception fifo is empty 25.6.23. transmission fifo count register (idetfcr) address fff2_0000 + 068h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) xcnt[7:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit position field description bit 7:0 xcnt[7:0] status of transmi ssion fifo counter is indicated.
25-17 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) 25.6.24. reception fifo count register (iderfcr) address fff2_0000 + 070h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) rcnt[7:0] r/w r/w r/w r/w r/w r/w r/w r /w r/w r/w r/w r/w r/w r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit position field description bit 7:0 rcnt[7:0] status of reception fifo counter is indicated. 25.6.25. udma timing control register (ideutcr) address fff2_0000 + 0c8h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) active count[3:0] recovery count[3:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit position field description bit 7:4 active count[3:0] active time of ide_xdior (hst robe) in the ultra dma access is defined. active time defines "1" width of ide_xdior (hstrobe) at udma transfer. bit 3:0 recovery count[3:0] recovery time of ide_xdior (hstrobe) in ultra dma access is defined. recovery time defines "0" width of id e_xdior (hstrobe) at udma transfer. refer to " 25.7.1 active time and recovery time" for active time and recovery time, and " 25.7.3 example setting of ultra dma mode register" for setting example. "0 001" is not able to be set to both active count a nd recovery count, in add ition rewriting this register during ultra dma tran sfer is invalid.
25-18 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) 25.6.26. udma command register (ideucmr) address fff2_0000 + 0d0h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) pause or term udma direction udma enable (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit position field description bit 7:4 (reserved) bit 3 pause or term operation for when reception fifo becomes full in ultra dma data in burst, or transmission fifo becomes empty in ultra dma data out burst is defined as follows. "0": state shifts to pause phase "1": state shifts to termination phase note: ? when ultra dma data in burst is used, be sure to set "0" to "pause or term" bit (pause phase.) setting "1" might not able to proceed transfer properly. ? when ultra dma data out burst is used, be sure to set "1" to "pause or term" bit (termination phase.) setti ng "0" might not able to proceed transfer properly. bit 2 udma direction direction of ultra dma transfer is defined. rewriting this bit during the transfer is invalid. "0": ultra dma data in burst. "1": ultra dma data out burst bit 1 udma enable ultra dm a transfer is enabled. current bit value is indicated at reading. "1": ultra dma is enabled. note: when ultra dma data in burst is us ed, do not write "0" to udma enable bit. transfer might not be proceeded properly. bit 0 (reserved)
25-19 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) 25.6.27. udma status register (ideustr) address fff2_0000 + 0d4h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) udma dataout burst udma datain burst r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r initial value 0 0 0 0 0 0 0 0 x x x x x x 0 0 bit position field description bit 7:2 (reserved) bit 1 udma dataout burst "1": ultra dma data out burst is in process bit 0 udma datain burst "1": ultra dma data in burst is in process 25.6.28. rxfifo rest count compare value (iderrcc) address fff2_0000 + 150h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) rrcc[7:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 bit position field description bit 7:0 rrcc[7:0] comparison value of reception fifo counter value when reception fifo counter value is matched to th is register?s at ultra dma data in transfer, the operation shifts to pause phase. in the default value, it starts the pause operation when counter value of reception fifo becomes 6 pieces to go. rewriting this register during ultra dma transfer is invalid. note: this register is used for maintaining compatibility with various drives, not for register value change during normal operation.
25-20 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) 25.6.29. ultra dma timing control 1 (ideutc1) address fff2_0000 +154h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) tack[3:0] tenv[3:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 bit position field description bit 7:4 tack[3:0] setup and hold t ime for asserting/negating dmack. ? mode0, 1, 2, 3, 4 (min. 20ns) ? initial value: 2 (cycle) ? adjustment range: 1 ~ 7 (cycle) bit 3:0 tenv[3:0] envelope time. the time from ide_xddmack (dmack) to ide_xdiow (stop) and xdior (hdmardy) in data in burst initiation, and from ide_xddmack (dmack) to ide_xdiow (stop) in data out burst initiation ? mode0, 1, 2 (min. 20ns/max. 70ns) ? mode3, 4 (min. 20ns/max. 55ns) ? initial value: 2 (cycle) ? adjustment range: 1 ~ 4 (cycle) rewriting this register during ultra dma transfer is invalid. note: this register is used for maintaining compatibility with various drives, not for register value change during normal operation.
25-21 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) 25.6.30. ultra dma timing control 2 (ideutc2) address fff2_0000 + 158h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) tli[3:0] tui[3:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 bit position field description bit 7:4 tli[3:0] interlock time (limitation on upper bound.) ? mode0, 1, 2 (min. 0ns/max. 150ns) ? mode3, 4 (min. 0ns/max. 100ns) ? initial value: 1 (cycle) ? adjustment range: 1 ~ 4 (cycle) bit 3:0 tui[3:0] interlock time (no limitation on upper bound) ? mode0, 1, 2, 3, 4 (min 0ns) ? initial value: 1(cycle) ? adjustment range: 1 ~ 4 (cycle) rewriting this register during ultra dma transfer is invalid. note: this register is used for maintaining compatibility with various drives, not for register value change during normal operation.
25-22 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) 25.6.31. ultra dma timing control 3 (ideutc3) address fff2_0000 + 15ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) tss[3:0] tmli[3:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 bit position field description bit 7:4 tss[3:0] negating time of ide_ddmarq (dmarq) or asserting time of ide_xdiow (stop) from ide_xdior (strobe) edge ? mode0, 1, 2, 3, 4 (min. 50ns) ? initial value: 4 (cycle) ? adjustment range: 1 ~ 7 (cycle) bit 3:0 tmli[3:0] interlock time (lower bound) ? mode0, 1, 2, 3, 4 (min. 20ns) ? initial value: 2 (cycle) ? adjustment range: 1 ~ 4 (cycle) rewriting this register during ultra dma transfer is invalid. note: this register is used for maintaining compatibility with various drives, not for register value change during normal operation. 25.6.32. dma status register (idestatus) address fff2_0000 + 200h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) dmabsy r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit position field description bit 7:1 (reserved) bit 0 dmabsy this bit displays "1" when ide i/f is in dma transfer. since this bit shows status, ?0? is displayed when ide i/f is not accesse d though dma is active (dma start = "1".) this bit is able to perform only reading so that the value is not changed even writing is proceeded. 0 (initial value) dma transfer is stop 1 dma transfer is in process
25-23 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) 25.6.33. interrupt register (ideint) address fff2_0000 + 204h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) drive access error ahbmw error dma end r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit position field description bit 7:3 (reserved) bit 2 drive access error this bit displays "1" when id e drive is accessed (cs0 and cs1) from ahb slave i/f at dma transfer (status.dmabusy = "1".) writing "0" to this bit clears int information to "0". when bit 2 is set to mask ("1"), o_ide66_irq is masked but not this bit. 0 (initial value) no interrupt 1 interrupt bit 1 ahbmw error when response error occurs at a ccessing to ahb i/f master during dma transfer, "1" is written. writing "0" to this bit clears int information to "0". when bit 1 of interrupt mask register is set to mask (" 1"), o_ide66_irq is mask ed but not this bit. 0 (initial value) no interrupt 1 interrupt bit 0 dma end when data transfer of which number of data transfer is set to dtc and sc is completed, "1" is written. writing "0" to this bit clears int information to "0". when bit 0 of interrupt mask register is set to mask ("1"), o_ide66_irq is masked but not this bit. 0 (initial value) no interrupt 1 interrupt
25-24 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) 25.6.34. interrupt mask register (ideintmsk) address fff2_0000 + 208h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) f_ide66 macro int mask (reserved) drive access error mask ahbmw error mask dma end mask r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 bit position field description bit 7:5 (reserved) bit 4 f_ide66 macro int mask mask of interrupt output (o_ide66_int ) from f_ide66 macro is released b y writing "0" to this bit. 0 no interrupt mask 1(initial value) interrupt mask bit 3 (reserved) bit 2 drive access error mask mask of interrupt output (o_ide66_int) caus ed by drive access error interrupt is released by writing "0" to this bit. although the value of this bit is "1", bit 2 (drive access error) value of interrupt regi ster is not masked ("0" display.) 0 no interrupt mask 1(initial value) interrupt mask bit 1 ahbmw error mask mask of interrupt output (o_ide66_int ) caused by ahbmw error interrupt is released by writing "0" to this bit. a lthough the value of this bit is "1", bit 1 (ahbmw error) value of interrupt regi ster is not masked ("0" display.) 0 no interrupt mask 1(initial value) interrupt mask bit 0 dma end mask mask of interrupt output (o_ide 66_int) caused by dma end interrupt is released b y writing "0" to this bit. although the value of this bit is "1", bit 0 (dma end) value of interrupt register is not masked ("0" display.) 0 no interrupt mask 1(initial value) interrupt mask
25-25 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) 25.6.35. pio access control register (idepioctl) address fff2_0000 + 20ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) pio control r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit position field description bit 7:1 (reserved) bit 0 pio control pio access is performed to f_ide66 macro by writing "1" to this bit when ready from f_ide66 macro is "0". however pio access may not be performed properly when "1" is written to this bit. normally, this bit is used with ?0? as default.
25-26 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) 25.6.36. dma control register (idedmactl) address fff2_0000 + 210h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dma start (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) trans mode r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit position field description bit 31 dma start this is start bit for dma transf er which starts by writing "1" to this bit. since the operation starts based on each dma transfer setting value at "1" writing, the setting should be completed before "1" is written to this bit. after all data transfer is completed, this bit becomes "0". for the case of ultra dma data out burst, dma transfer is able to stop by writing "0" to this bit, however the data at dma transfer stop is not guaranteed. ahb master i/f stops the access after the transaction at dma transfer stop is completed. ide i/f stops the access when fifo in f_ide66 macro becomes empty (data out burst) or full (data in burst.) when writing "0" to this bit to end dma tr ansfer, "0" should be written to dma enable in f_ide66 macro to stop the transfer. (icmr[1] = "0" and ucmr[1] = "0") 0 (initial value) dma transfer stops 1 dma transfer starts note: when ultra dma data in burst is used, do not write "0" to dma start bit. transfer might not be proceeded properly. bit 30:1 (reserved) bit 0 trans mode this bit sets tr ansfer mode for dma transfer. when this bit is "0" (initi al value), dma transfer is performed in 512 byte unit. sc bit of dma transfer control register becomes valid for number of dma transfer setting. when "1" is written to this bit, transfer is performed in 4 byte unit to the transfer for 512 byte or less. dtc bit of dma transfer control register becomes valid for number of dma transfer setting. 0 (initial value) 512 byte unit transfer 1 4 byte unit transfer
25-27 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) 25.6.37. dma transfer control register (idedmatc) address fff2_0000 + 214h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) dtc[8:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r initial value 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sc[7:0] (reserved) div[1:0] incr type[2:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 bit position field description bit 31:25 (reserved) bit 24:16 dtc[8:0] (dma data transfer count) this bit sets number of byte for dma transfer (9' h000 in the case of 4 byte.) this bit becomes valid at bit 0 = "1" of dma control register. since ahb i/f burst transfer is performed w ith 32 bit (4 byte) data width, [17:16] is fixed to 0. 4 byte transfer is performed by all "0", and it is able to be set from 4 to 512 byte in 4 byte unit. when this bit is read, number of remaining transfer byte is indicated (remaining amount - 1 is displayed.) bit 15:8 sc[7:0] (sector count) this bit sets number of sector for transferring to consecutive sector. this bit becomes valid at bit 0 = "0" of dma control register. set the same value as cs0 sector count - 1 (8'h00 in the case of 1 sector.) data transfer for 512 byte sc setting value is performed. when this bit is read, number of remaining transfer sector is indicated (remaining amount - 1 is displayed.) during ultra dma transfer, rewriting this register is invalid bit 7:6 (reserved) bit 5:4 div[1:0] (division of increment burst) when type bit setting is undefined length of increment type burst ("001"), this bit performs the burst by dividing number of transfer set with dtc bit into 64 and 32 burst regarding max. number of transfer as 512byte. 00: no division undefined length increment type burst is performed for the number of transfer byte set with dtc regarding max. value as 512 byte. 128 burst at 512 byte transfer. 01: 64 burst 64 burst 2 at 512 byte transfer 10: 32 burst 32 burst 4 at 512 byte transfer 11: unused (no division) bit 3 incr (dma transfer address increment) whether to transfer with incrementing address for number of transfer or to repeatedly transfer dmsar and dmadar addresses after each burst transfer to ahb i/f and single transfer is set. 0 (initial value) increment (initial value) first address is incremented * at single transfer: previous address + 0x4 at 16 burst: previous address + 0x40 1 fixed address is not incremented * at single transfer: address is fixed bit 2:0 type (dma transfer type) 000: single single transfer 001: incr (initial value) undefine d length increment type burst 01x incr4 4 increment type burst 10x: incr8 8 increment type burst 11x: incr16 16 increment type burst
25-28 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) 25.6.38. dma source address register (idedmasad) address fff2_0000 + 218h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dma source address r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dma source address r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit position field description bit 31:0 dma source address this register specifies source address on memory at dma data out burst transfer. when memory is read by this module, it is performed in 32 bit unit so that low order 2 bits of source address is fixed to 2'b00. during ultra dma transfer, rewriting this register is invalid. 25.6.39. dma destination address register (idedmadad) address fff2_0000 + 21ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dma destination address r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dma destination address r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit position field description bit 31:0 dma destination address this register specifies address of transfer destination on memory at dma data in burst transfer. when memory is written by this m odule, it is performed in 32 bit unit so that low order 2 bits of destination address is fixed to 2'b00. during ultra dma transfer, rewriting this register is invalid.
25-29 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) 25.7. ide operation 25.7.1. active time and recovery time definition of active and recovery time of pio timing control register (ptcr) and udma timing control register (utcr) is as follows. active/recovery count r/w cycle time 0000 16 clocks 0001 1 clocks 0010 2 clocks 0011 3 clocks 0100 4 clocks 0101 5 clocks 0110 6 clocks 0111 7 clocks 1000 8 clocks 1001 9 clocks 1010 10 clocks 1011 11 clocks 1100 12 clocks 1101 13 clocks 1110 14 clocks 1111 15 clocks active and recovery time should be set in consideration of internal input frequency not to violate the ata specification. the settable min. value in each transfer mode is indicated in " 25.7.2 example setting of pio mode register" and " 25.7.3 example setting of ultra dma mode register".
25-30 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) 25.7.2. example setting of pio mode register table 25-3 shows register value for setting mi n. time of pio mode standard value. table 25-3 example setting of pio mode register (case of input internal frequency is 83.3mhz (12ns for 1 cycle)) mode(t0 standard value) t1 standard value/pasr[2:0] t2 standard value/ptcr[7:4] t2i standard value/ptcr[3:0] mode4 (120ns) min. 25ns/"011" mi n. 70ns/"0110" min. 25ns/"0100" mode3 (180ns) min. 30ns/"011" min. 80ns/"1000" min. 70ns/"0111" mode2 (240ns) min. 30ns/"011" min. 100ns/"1010" "1010" mode1 (383ns) min.50ns/"101" min. 125ns/"0000" "0000" mode0 (600ns) min. 70ns/"110" min. 165ns/"0000" "0000" the value setting less than the min. value sh own the above to each mode is prohibited. register must be set with "t0 t2 + t2i". although t2i standard value for mode2 or less is not defined, it should be set in compliance with the above definition. e.g. pio mode2 is set when internal input is clk83mhz pasr[2:0] = "011" ptcr[7:4] = "1010" ptcr[3:0] = "1010" t2(12ns 11) + t2i(12ns 11) = 264ns note: the contents described above are to meet min. time of the standard that it does not secure the operation. perform connection evaluation with the driv e to change register value to operate properly.
25-31 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) 25.7.3. example setting of ultra dma mode register table 25-4 shows register value for setting min. time of ultra dma mode standard value. table 25-4 setting example of ultra dma mode register (case of internal input frequency is 83.3mhz (12ns for 1 cycle)) mode (t2cyctyp standard value) tcyc standard value/utcr[7:4] or utcr[3:0] mode4 (60ns) min.25ns/"0011" mode3 (90ns) min. 39ns/"0100" mode2 (120ns) min. 54ns/"0101" mode1 (160ns) min.73ns/"0111" mode0 (240ns) min. 112ns/"1010" note: the contents described above are to meet min. time of the standard that it does not secure the operation. perform connection evaluation with the driv e to change register value to operate properly.
25-32 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) 25.8. function ahb slave i/f when write access is performed from ahb i/f, o_sh ready is disabled (low output) until writing to f_ide66 macro is completed. when read access is performed from ahb i/f, o_shready is disabled (low output) until read data output to ahb i/f is ready. all transfer types and burst transfer can be accepted; however, burst transfer is handled the same as single access at importing to the module. since access to the storage device regist er during dma transfer is prohibite d, error interrupt is output if the register is accessed. ahb master i/f burst transfer transfer type is able to be set with type regist er setting, and all types ex cept wrapping burst can be transmitted. during dma transfer, ahb burst transfer with norm al setting transfers dma data by max. 512 byte of undefined length increment burst. undefined length increment burst's burst length is able to be changed with div register at undefined length increment burst setting. 1kb boundary transfer when increment burst exceeding 1kb boundary is proceeded, only the transaction goes over 1kb boundary is converted to single transfer to access. for other transactions, the transfer type set to the register is used.
25-33 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) program i/o access example setting of pio mode register when pio access is performed with this module, pi o timing control register (ptcr) needs to be set in compliance with pio mode standard value. storage device internal register access internal register of storage device is ab le to be accessed by cs0/1 register access. ultra dma transfer ultra dma transfer is able to be proceeded by setting transfer mode in dma related register (0x0210 or later) and writing "1" to dma start bit of dma contro l register after f_ide66 register?s dma transfer setup. transfer in byte unit ultra dma transfer is performed to 512 bytes or less data access, and it is able to set up to 512 byte in 4 byte unit. this function becomes valid by setting dmactl.dma mode bit to "1 ". if remaining transfer is less than the number of tr ansfer set to fixed length burst and the number of undefined burst set in dvi register, the remaining is transferred with undefined length burst. transfer in sector unit in order to set number of transfer sector in sc (sector count) register, dma transfer is proceeded in sector unit (512 byte) with having necessary data for the transfer by 512 byte 2 double buffer configuration. this function becomes valid by setting dmactl.dma mode bit = "0".
25-34 MB86R01 lsi product specifications fujitsu semiconductor confidential ide host controller (ide66) interrupt process interrupt factor interrupt output, o_ide_irq is or output caused by followings: ? interrupt from ide drive(dintrq) ? interrupt factor in f_ide66 (normally unused) 1. fifo status interrupt by having txfifo become empty interrupt by having rxfifo become full ? dma related interrupt factor 1. completion of dma transfer interrupt by having completed all dma transfer 2. ahb master i/f error interrupt by detecting response error due to access of ahm master i/f 3. ahb slave i/f error interrupt by accessing to storage device register from ahb slave i/f during dma transfer the host detected the interrupt should confirm all of the above interrupt factors. output of o_ide_irq can mask output according to the interrupt mask register. (refer to interrupt mask register.) interrupt clear ? ide drive interrupt is cleared by either of the followings: ? device selects and reads status in bsy = "0" ? device selects and writes command in bsy = "0" and drq = "0" ? assert xdreset ? set srst bit to "1" ? internal interrupt of f_ide66 is cleared by writing "1" to interrupt clear (icmr[3]) of icmr. ? dma related interrupt is cleared by writing "0" to the bit showing each interrupt factor of interrupt register.
26-1 MB86R01 lsi product specifications fujitsu semiconductor confidential ccnt 26. ccnt this chapter describes function and operation of chip control module (ccnt.) 26.1. outline chip control module (hereafter called ccnt) performs pin multiplex control, software reset control, axi interconnect control and others. 26.2. feature ? multiplex pin interface: mode selection setting of pin multiplex groups 2 and 4 ? software reset interface: issuing software reset to each module in the register ? external pin interface: indicating signal level of the external pin in status ? axi interconnect interface: setting axi wait and priority of bus right ? int interface: setting interrupt mask and interrupt information clear ? byte swap interface: setting byte swap of ide66, sdmc, i2s, and usb 2.0 host ? ddr2 controller interface: reset control in ddr2 controller ? gpio interface ? medialb interface: switching read data output method of medialb's ahb ? usb 2.0 interface (host system): usb 2.0 host controller's stop control this is asserted when high order system detects error in ahb system or others ? usb 2.0 interface (host ehci power): this asserts signal when overcurrent is detected, and it disables port
26-2 MB86R01 lsi product specifications fujitsu semiconductor confidential ccnt 26.3. block diagram ccnt int register each macro interrupt usb setting register axi wait register axi polarity setting register soft reset all register macro software reset register hreset apb i/f apb external pin's mpx setting status register pin multiplex control signal mpx_mode2[3:0] mpx_mode4 external pin mpx_mode1[1:0] mpx_mode5[1:0] usb_mode (apb reset) irc (interrupt controller) usb2.0 host axi interconnection rest signal connected to each macro byte swap control register byte swap control signal connected to ide66, sdmc, i2s, and usb2.0 host ddr2c reset control register ddr2 controller gpio interrupt register gpio medialb setting register medialb figure 26-1 block diagram of ccnt 26.4. supply clock ahb clock is supplied to ccnt. refer to "5. clock reset generator (crg)" for frequency setting and control specification of the clock.
26-3 MB86R01 lsi product specifications fujitsu semiconductor confidential ccnt 26.5. register this section describes ccnt module register. 26.5.1. register list ccnt unit contains register shown in table 26-1. t able 26-1 ccnt register list address register description fff42000 ccid chip id register fff42004 csrst software reset register fff42008 ? fff4200f reserved access prohibited fff42010 cist interrupt status register fff42014 cistm interrupt st atus mask register fff42018 cgpio_ist gpio interrupt status register fff4201c cgpio_istm gpio interr upt status mask register fff42020 cgpio_ip gpio interrupt polarity setting register fff42024 cgpio_im gpio interrupt mode setting register fff42028 caxi_bw axi bus wait cycle setting register fff4202c caxi_ps axi polarity setting register fff42030 cmux_md multiplex mode setting register fff42034 cex_pin_st external pin status register fff42038 cmlb medialb setting register fff4203c reserved access prohibited fff42040 cusb usb setting register fff42044 - fff420e7 reserved access prohibited fff420e8 cbsc byte swap switching register fff420ec cdcrc ddr2 controller reset control register fff420f0 cmsr0 software reset register 0 for macro fff420f4 cmsr1 software reset register 1 for macro
26-4 MB86R01 lsi product specifications fujitsu semiconductor confidential ccnt description format of register following format is used for descri ption of register?s each bit in " 26.5.2 chip id register (ccid)" to " 26.5.19 software reset register 1 for macro (cmsr1)". address base address + offset bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r/w initial value bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r/w initial value meaning of item and sign address address (base address + offset address) of the register bit bit number of the register name bit field name of the register r/w attribution of read/write of each bit field ? r0:read value is always "0" ? r1: read value is always "1" ? w0: write value is always "0", and write access of "1" is ignored ? w1: write value is always "1", and write access of "0" is ignored ? r: read ? w: write initial value each bit field?s value after reset ? 0: value is "0" ? 1: value is "1" ? x: value is undefined
26-5 MB86R01 lsi product specifications fujitsu semiconductor confidential ccnt 26.5.2. chip id register (ccid) address fff4_2000 + 00h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name year[15:0] r/w r r r r r r r r r r r r r r r r initial value 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name chipname[7:0] version[7:0] r/w r r r r r r r r r r r r r r r r initial value 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 bit field no. name function 31-16 year[15:0] date of lsi development is indicated in 4 digit dominical year. in this lsi, 2006(h) is read. 15-8 chipname[7:0] lsi identification name is indicated in id number. in this lsi, 10(h) is read. 7-0 version[7:0] lsi version is indicated. in this lsi, 02(h) is read.
26-6 MB86R01 lsi product specifications fujitsu semiconductor confidential ccnt 26.5.3. software reset register (csrst) address fff4_2000 + 04h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) sftrst r/w r r r r r r r r r r r r r r r r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name function 31-1 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 0 sftrst (software reset) writing "1" to this bit outputs reset to macro (gdc, ddr2 controller, can, sdmc, medialb, i2s, spi, ide66, i2c, pwm, uart, usb, gpio, and dmac) in chip. since register value is output as it is (level output), "0" shoul d be set again to release reset. 0 not reset (initial value) 1 reset ccnt macro software reset register apb software reset register hresetn rst0 from crg rst1 rstx to macro sftrst figure 26-2 details of software reset
26-7 MB86R01 lsi product specifications fujitsu semiconductor confidential ccnt 26.5.4. interrupt status register (cist) address fff4_2000 + 10h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name int31 (reserved) int28 int27 int26 (reserved) int24 (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name reserved) int5 (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name function 31 int31 when medialb dint interrupt occurs, "1" is set. writing "0" to this bit clears int information to "0". when bit 31 of the interrupt status mask register is set to mask "0", this bit is fixed to "0". 0 no interrupt (initial value) 1 interrupt (medialb dint) 30-29 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 28 int28 when hbus2axi error interrupt occurs, "1" is set. writing "0" to this bit clears int information to "0". when bit 28 of the interrupt status mask register is set to mask "0", this bit is fixed to "0". 0 no interrupt (initial value) 1 interrupt (hbus2axi) 27 int27 when mbus2axi (draw) error interrupt oc curs, "1" is set. writing "0" to this bit clears int information to "0". when bit 27 of the interrupt status mask register is set to mask "0", this bit is fixed to "0". 0 no interrupt (initial value) 1 interrupt (mbus2axi (draw)) 26 int26 when mbus2axi (dispcap) error interrupt occurs, "1" is set. writing "0" to this bit clears int information to "0". when bit 26 of the interrupt status mask register is set to mask "0", this bit is fixed to "0". 0 no interrupt (initial value) 1 interrupt (mbus2axi (dispcap)) 25 (reserved) reserved bit. initial value is 0 h . setting other values than the initial value is prohibited. 24 int24 (ahb2axi) when ahb2axi error interrupt occurs, "1" is set. writing "0" to this bit clears int information to "0". when bit 24 of the interrupt status mask register is set to mask "0", this bit is fixed to "0". 0 no interrupt (initial value) 1 interrupt (ahb2axi) 23-6 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0".
26-8 MB86R01 lsi product specifications fujitsu semiconductor confidential ccnt bit field no. name function 5 int5 when mbus2axi (cap) error interrupt occu rs, "1" is set. writing "0" to this bit clears int information to "0". when bit 5 of the interr upt status mask register is set to mask "0", this bit is fixed to "0". 0 no interrupt (initial value) 1 interrupt (mbus2axi (cap) ) 4-0 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0".
26-9 MB86R01 lsi product specifications fujitsu semiconductor confidential ccnt 26.5.5. interrupt status mask register cistm address fff4_2000 + 14h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name int31 mask (reserved) int28 mask int27 mask int26 mask (reserved) int24 mask (reserved) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name reserved) int5 mask (reserved) int1 mask int0 mask r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name function 31 int31 mask writing "1" to this bit validates mlb_dint interrupt. 0 mask (initial value) 1 int31 is valid (mlb_dint interrupt) 30-29 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 28 int28 mask writing "1" to this bi t validates hbus2axi interrupt. 0 mask (initial value) 1 int28 is valid (hbus2axi interrupt) 27 int27 mask writing "1" to this bit va lidates mbus2axi (draw) interrupt. 0 mask (initial value) 1 int27 is valid (mbus2axi (draw)) 26 int26 mask writing "1" to this bit validates mbus2axi (disp) interrupt. 0 mask (initial value) 1 int26 is valid (mbus2axi (disp) interrupt) 25 (reserved) reserved bit. initial value is 0 h . setting other values than the initial value is prohibited. 24 int24 mask writing "1" to this bit validates ahb2axi interrupt. 0 mask (initial value) 1 int24 is valid (ahb2axi interrupt) 23-6 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 5 int5 mask writing "1" to this bit validates mbus2axi (cap) interrupt. 0 mask (initial value) 1 int5 is valid (mbus2axi (cap) interrupt) 4-2 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0".
26-10 MB86R01 lsi product specifications fujitsu semiconductor confidential ccnt bit field no. name function 1 int1 mask writing "1" to this bit validates adc ch1 interrupt. 0 mask (initial value) 1 int1 is valid (adc ch1 interrupt) 0 int0 mask writing "1" to this bit validates adc ch0 interrupt. 0 mask (initial value) 1 int0 is valid (adc ch0 interrupt)
26-11 MB86R01 lsi product specifications fujitsu semiconductor confidential ccnt 26.5.6. gpio interrupt status register (cgpio_ist) this register is to indicate gpio related interrupt status. address fff4_2000 + 18h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) gpio_int_status[23:16] r/w r0/w0 r0/w0 r0/w0 r0/w0 r0/w0 r0/w0 r0/w0 r0/w0 r/w0 r/w0 r/w0 r/w0 r/ w0 r/w0 r/w0 r/w0 initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio_int_status[15:0] r/w r/w0 r/w0 r/w0 r/w0 r/w0 r/w0 r/w0 r/w0 r/w0 r/w0 r/w0 r/w0 r/ w0 r/w0 r/w0 r/w0 initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name function 31-24 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 23-0 gpio_int_status (gpio interrupt status) this is cleared by "0" writing. gpio's applied bit indicate s interrupt is occurred. 0 interrupt is not occurred 1 interrupt is occurred 26.5.7. gpio interrupt status mask register (cgpio_istm) this register is to control gpio related interrupt which is judged by the setting status regardless of input/output. each setting bit can be set corres ponding to each bit one- by-one from msb to lsb. address fff4_2000 + 1ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) gpio_int_enable[23:16] r/w r0/w0 r0/w0 r0/w0 r0/w0 r0/w0 r0/w0 r0/w0 r0/w0 r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio_int_enable[15:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name function 31-24 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 23-0 gpio_int_enable (gpio interrupt enable) whether to generate interrupt with the value sampled external pin, gpio23-0 in internal clock is set by bit. 0 interrupt does not occur 1 interrupt occurs based on the regi ster setting shown from the next page
26-12 MB86R01 lsi product specifications fujitsu semiconductor confidential ccnt 26.5.8. gpio interrupt polarity s etting register (c gpio_ip) this register is to control gpio related interrupt which is judged by the setting status regardless of input/output. each setting bit can be set corres ponding to each bit one- by-one from msb to lsb. address fff4_2000 + 20h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) gpio_int_polarity[23:16] r/w r0/w0 r0/w0 r0/w0 r0/w0 r0/w0 r0/w0 r0/w0 r0/w0 r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio_int_polarity[15:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name function 31-24 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 23-0 gpio_int_polarity (gpio interrupt polarity) interrupt occurs with the following value. 0 level "0" or negative edge is de tected (gpio_int_ mode dependant) 1 level "1" or positive edge is detected (gpio_int_mode dependant) 26.5.9. gpio interrupt mode setting register (cgpio_im) this register is to control gpio related interrupt which is judged by the setting status regardless of input/output. each setting bit can be set corres ponding to each bit one- by-one from msb to lsb. address fff4_2000 + 24h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) gpio_int_mode[23:16] r/w r0/w0 r0/w0 r0/w0 r0/w0 r0/w0 r0/w0 r0/w0 r0/w0 r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio_int_mode[15:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name function 31-24 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 23-0 gpio_int_polarity (gpio interrupt polarity) gpio_int_mode (gpio interrupt mode) 0 level sensitive ("0" or "1" is gpio_int_polarity dependant) 1 edge sensitive ("pos" or "neg " is gpio_int_polarity dependant)
26-13 MB86R01 lsi product specifications fujitsu semiconductor confidential ccnt 26.5.10. axi bus wait cycle setting register (caxi_bw) address fff4_2000 + 28h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name disp_rwait[3:0] disp_wwait[3:0] draw_rwait[3:0] draw_wwait[3:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) primaryahb_rwait[3:0] primaryahb_wwait[3:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name function 31-28 disp_rwait (read wait) wait time of axi write (between the transacti ons) is able to be set in the range of 0 h (no wait) - f h (15 cycle wait.) initial value is 0 h (no wait.) (note) 1 cycle is axi 1 clock. 27-24 disp_wwait (write wait) wait time of axi read (between the transactions) is able to be set in the range of 0 h (no wait) - f h (15cycle wait.) initial value is 0 h (no wait.) (note) 1 cycle is axi 1 clock. 23-20 draw_rwait (read wait) wait time of axi write (between the transacti ons) is able to be set in the range of 0 h (no wait) - f h (15cycle wait.) initial value is 0 h (no wait.) (note) 1 cycle is axi 1 clock. 19-16 draw_wwait (write wait) wait time of axi read (between the transactions) is able to be set in the range of 0 h (no wait) - f h (15cycle wait.) initial value is 0 h (no wait.) (note) 1 cycle is axi 1 clock. 15-8 (reserved) reserved bit. initial value is 0h. setting other than initial value is prohibited. 7-4 primaryahb_rwa it (write wait) wait time of axi write (between the transacti ons) is able to be set in the range of 0 h (no wait) - f h (15cycle wait.) initial value is 0 h (no wait.) (note) 1 cycle is axi 1 clock. 3-0 primaryahb_ww ait (read wait) wait time of axi read (between the transactions) is able to be set in the range of 0 h (no wait) - f h (15cycle wait.) initial value is 0 h (no wait.) (note) 1 cycle is axi 1 clock.
26-14 MB86R01 lsi product specifications fujitsu semiconductor confidential ccnt 26.5.11. axi polarity setting register (caxi_ps) this register is to prioritize the bus right on axi inter connect. the priority on th e axi bus is as follows. psel_0 > psel_1 > psel_2 >psel_3 > psel_4 set bus master identification code 0-4 to each setting bit. 5 or more of value and overlapping value are not available; in this case, register writing is ignored and the previous setting value is kept. note: the psel_2 setting bit should be fixed to "010". setting "010" to psel_0, psel_1, psel_3, and psel_4 is prohibited. address fff4_2000 + 2ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) p_sel4 r/w r r r r r r r r r r r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) p_sel3 (reserved) p_sel2 (reserved) p_sel1 (reserved) p_sel0 r/w r r/w r/w r/w r r/w r/w r/w r r/w r/w r/w r r/w r/w r/w initial value 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 bit field no. name function 31-19 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 18-16 p_sel4 (priority select4) priority order of axi inter connect is set. 000 dispcap 001 ahb 010 (setting prohibited) 011 hbus 100 draw (initial value) 101-111 (setting prohibited) 15 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 14-12 p_sel3 (priority select3) priority order of axi inter connect is set. 000 dispcap 001 ahb 010 (setting prohibited) 011 hbus (initial value) 100 draw 101-111 (setting prohibited) 11 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0".
26-15 MB86R01 lsi product specifications fujitsu semiconductor confidential ccnt bit field no. name function 10-8 p_sel2 (priority select2) priority order of axi inter connect is set. 000 (setting prohibited) 001 (setting prohibited) 010 this bit field should be fi xed to 010 (initial value). 011 (setting prohibited) 100 (setting prohibited) 101-111 (setting prohibited) 7 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 6-4 p_sel1 (priority select1) priority order of axi inter connect is set. 000 dispcap 001 ahb (initial value) 010 (setting prohibited) 011 hbus 100 draw 101-111 (setting prohibited) 3 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 2-0 p_sel0 (priority select0) priority order of axi inter connect is set. 000 dispcap (initial value) 001 ahb 010 (setting prohibited) 011 hbus 100 draw 101-111 (setting prohibited
26-16 MB86R01 lsi product specifications fujitsu semiconductor confidential ccnt 26.5.12. multiplex mode setting register (cmux_md) address fff4_2000 + 30h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) mpx_mode_4 (reserved) mpx_mode_2 r/w r r r r r r r r r r r/w r/w r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 bit field no. name function 31-6 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 5-4 mpx_mode_4 external pin's multiplexed group #4 is set. 00 mode 0 01 mode 1 10 reserved 11 (initial value) 3 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 2-0 mpx_mode_2 external pin's multiplexed group #2 is set. 000 mode 0 001 mode 1 010 mode 2 011 mode 3 100 mode 4 101 ? 0110 reserved 111 (initial value) note: be sure to set each group of the pin mu ltiplex to any of the modes after power-on.
26-17 MB86R01 lsi product specifications fujitsu semiconductor confidential ccnt 26.5.13. external pin status register (cex_pin_st) address fff4_2000 + 34h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) *1 cripm[3:0] (reserved) mpx_mode_5 mpx_mode_1 r/w r r r r r r r r r r r r r r r r initial value 0 0 0 x x x x x 0 0 0 0 x x x x *1: usb_mode bit field no. name function 31-13 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 12 usb_mode external pin status for usb mode switch is displayed. 0 mode 0 1 mode 1 11-8 cripm status of pll multiple number setting pin is displayed. 7-4 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 3-2 mpx_mode_5 setting pin status for extern al pin's multiplexed group #5 is displayed. 00 mode 0 01 mode 1 10 mode 2 11 mode 0 1-0 mpx_mode_1 setting pin status for extern al pin's multiplexed group #1 is displayed. 00 mode 0 01 mode 1 10 mode 2 11 mode 0
26-18 MB86R01 lsi product specifications fujitsu semiconductor confidential ccnt 26.5.14. medialb setting register (cmlb) address fff4_2000 + 38h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) sel_sp read r/w r r r r r r r r r r r r r r r r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name function 31-1 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 0 sel_spread read data output me thod of medialb is switched. 0 case a 1 case b ahb read data output method of medialb is switched. > case(a) ... output the word data. hrdata 31-24 23-16 15-8 7-0 bigendian word 0h byte0, byte1, byte2, byte3 half word 0h byte0, byte1, byte2, byte3 half word 2h byte0, byte1, byte2, byte3 byte 0h byte0, byte1, byte2, byte3 byte 1h byte0, byte1, byte2, byte3 byte 2h byte0, byte1, byte2, byte3 byte 3h byte0, byte1, byte2, byte3 littleendian word 0h byte3, byte2, byte1, byte0 half word 0h byte3, byte2, byte1, byte0 half word 2h byte3, byte2, byte1, byte0 byte 0h byte3, byte2, byte1, byte0 byte 1h byte3, byte2, byte1, byte0 byte 2h byte3, byte2, byte1, byte0 byte 3h byte3, byte2, byte1, byte0
26-19 MB86R01 lsi product specifications fujitsu semiconductor confidential ccnt > case(b) ... output by filling with valid data hrdata 31-24 23-16 15-8 7-0 bigendian word 0h byte0, byte1, byte2, byte3 half word 0h byte0, byte1, byte0, byte1 half word 2h byte2, byte3, byte2, byte3 byte 0h byte0, byte0, byte0, byte0 byte 1h byte1, byte1, byte1, byte1 byte 2h byte2, byte2, byte2, byte2 byte 3h byte3, byte3, byte3, byte3 littleendian word 0h byte3, byte2, byte1, byte0 half word 0h byte1, byte0, byte1, byte0 half word 2h byte3, byte2, byte3, byte2 byte 0h byte0, byte0, byte0, byte0 byte 1h byte1, byte1, byte1, byte1 byte 2h byte2, byte2, byte2, byte2 byte 3h byte3, byte3, byte3, byte3
26-20 MB86R01 lsi product specifications fujitsu semiconductor confidential ccnt 26.5.15. usb set register (cusb) address fff4_2000 + 40h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) *1 (reserved) *2 r/w r r r r r r r r r r r r/w r r r r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 *1: app_prt_ovrcur *2: sys_interrupt bit field no. name function 31-5 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 4 app_prt_ovrcur usb host ehci power control usb 2.0 host port is disabled, and this is us ed when overcurrent is detected and others. 0 port is enabled 1 port is disabled 3-1 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 0 sys_interruppt usb host system usb 2.0 host is stopped, and this is used wh en high order system de tects error and others. 0 usb 2.0 host is in normal operation 1 usb 2.0 host stops
26-21 MB86R01 lsi product specifications fujitsu semiconductor confidential ccnt 26.5.16. byte swap switching register (cbsc) this register is for byte swap switching and is set as follows. wsel 0 (little) 1 (big) hwswap - (no swap) 0 (swap) 1 (no swap) wswap - (no swap) 0 (swap) 1 (no swap) wsel: little/big switching signal hwswap: hword byte swap switc hing signal at big endian wswap: word byte swap switching signal at big endian address fff4_2000 + e8h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) *1 (reserved) *2 (reserved) sdmc_endian[2:0] (reserved) i2s0_endian[2:0] r/w rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) i2s1_endian[2:0] (reserved) i2s2_endian[2:0] (reserved) usb_host_endian[2:0] (reserved) r/w rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 *1: ide_master_dma_endian[2:0] *2: ide_slave_pio_endian [2:0] bit field no. name function 31 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 30-28 ide_master_ dma_endian endian switch of ide66 (master: dma) is controlled. bit 30 wsel endian switch 0:little, 1:big bit 29 hwsap hword byte swap switching signal at big bit 27 wswap word byte swap switching signal at big 27 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 26-24 ide_slave_pio_ endian endian switch of ide66 (sla ve: pio) is controlled. bit 26 wsel endian switch 0:little, 1:big bit 25 hwsap hword byte swap switching signal at big bit 24 wswap word byte swap switching signal at big 23 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 22-20 sdmc_endian endian switch of sdmc is controlled. bit 22 wsel endian switch 0:little, 1:big bit 21 hwsap hword byte swap switching signal at big bit 20 wswap word byte swap switching signal at big 19 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0".
26-22 MB86R01 lsi product specifications fujitsu semiconductor confidential ccnt bit field no. name function 18-16 i2s0_endian endian switch of i2s0 is controlled. bit 18 wsel endian switch 0:little, 1:big bit 17 hwsap hword byte swap switching signal at big bit 16 wswap word byte swap switching signal at big 15 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 14-12 i2s1_endian endian switch of i2s1 is controlled. bit 14 wsel endian switch 0:little, 1:big bit 13 hwsap hword byte swap switching signal at big bit 12 wswap word byte swap switching signal at big 11 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 10-8 i2s2_endian endian switch of i2s2 is controlled. bit 10 wsel endian switch 0:little, 1:big bit 9 hwsap hword byte swap switching signal at big bit 8 wswap word byte swap switching signal at big 7 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 6-4 usb_host_ endian endian switch of usb 2.0 host is controlled. bit 6 wsel endian switch 0:little, 1:big bit 5 hwsap hword byte swap switching signal at big bit 4 wswap word byte swap switching signal at big 3-2 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 1-0 (reserved) reserved bit. initial value is 0 h . setting other values than the initial value is prohibited.
26-23 MB86R01 lsi product specifications fujitsu semiconductor confidential ccnt 26.5.17. ddr2 controller reset control register (cdcrc) this register is to output reset to ddr-if macro in ddr2 controller by writing "0" to each bit. since register value is output as it is (level ou tput), "1" should be set again to release reset. address fff4_2000 + ech bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) r/w rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) *1 *2 r/w rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 *1: ireset&iusrrst *2: idllrst bit field no. name function 31-2 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 1 ireset&iusrrst ireset and iusrrst to ddr-if macro in ddr2 controller is controlled. 0 reset (initial value) 1 not reset 0 idllrst idllrst to ddr-if macro in ddr2 controller is controlled. 0 reset (initial value) 1 not reset
26-24 MB86R01 lsi product specifications fujitsu semiconductor confidential ccnt 26.5.18. software reset register 0 for macro (cmsr0) address fff4_2000 + f0h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) srst0_25 srst0_24 (reserved) srst0_16 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name (reserved) srst0_7 (reserved) srst0_5 srst0_4 srst0_3 srst0_2 srst0_1 srst0_0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name function 31-26 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 25 srst0_25 (uart1 software reset) reset is output to uart1 macro by writing "1" to this bit. since register value is output as it is (level output), "0" shoul d be set again to release reset. 0 no software reset (initial value) 1 software reset 24 srst0_24 (uart0 software reset) reset is output to uart0 macro by writing "1" to this bit. since register value is output as it is (level output), "0" shoul d be set again to release reset. 0 no software reset (initial value) 1 software reset 23-17 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 16 srst0_16 (dmac software reset) reset is output to dmac macro by writing "1" to this bit. since register value is output as it is (level output), "0" shoul d be set again to release reset. 0 no software reset (initial value) 1 software reset 15-8 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 7 srst0_7 (gpio software reset) reset is output to gpio macro by writing "1" to this bit. since register value is output as it is (level output), "0" shoul d be set again to release reset. 0 no software reset (initial value) 1 software reset 6-5 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 4 srst0_4 (gdc disp1 software reset) reset is output to gdc disp1 macro by writing "1" to this bit. since register value is output as it is (level output), "0" shoul d be set again to release reset. 0 no software reset (initial value) 1 software reset
26-25 MB86R01 lsi product specifications fujitsu semiconductor confidential ccnt bit field no. name function 3 srst0_3 (gdc disp0 software reset) reset is output to gdc disp0 macro by writing "1" to this bit. since register value is output as it is (level output), "0" shoul d be set again to release reset. 0 no software reset (initial value) 1 software reset 2 srst0_2 (gdc cap1 software reset) reset is output to gdc cap1 macro by writing "1" to this bit. since register value is output as it is (level output), "0" shoul d be set again to release reset. 0 no software reset (initial value) 1 software reset 1 srst0_1 (gdc cap0 software reset) reset is output to gdc cap0 macro by writing "1" to this bit. since register value is output as it is (level output), "0" shoul d be set again to release reset. 0 no software reset (initial value) 1 software reset 0 srst0_0 (gdc draw software reset) reset is output to gdc draw macro by writing "1" to this bit. since register value is output as it is (level output), "0" shoul d be set again to release reset. 0 no software reset (initial value) 1 software reset
26-26 MB86R01 lsi product specifications fujitsu semiconductor confidential ccnt 26.5.19. software reset register 1 for macro (cmsr1) address fff4_2000 + f4h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name (reserved) srst1_29 srst1_28 srst1_27 srst1_26 srst1_25 srst0_24 srst1_23 srst1_22 srst1_21 srst1_20 srst1_19 srst1_18 srst1_17 srst1_16 r/w r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name srst1_15 srst1_14 srst1_13 srst1_12 srst1_11 srst1_10 srst1_9 srst1_8 srst1_7 srst1_6 srst1_5 srst1_4 srst1_3 srst1_2 srst1_1 srst1_0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit field no. name function 31-30 (reserved) reserved bit. write access is ignored. read valu e of these bits is always "0". 29 srst1_29 (medialb software reset) reset is output to medialb macro by writing "1" to this bit. since register value is output as it is (level output), "0" should be set again to release reset. 0 no software reset (initial value) 1 software reset 28 srst1_28 (hbus2axi software reset) reset is output to hbus2axi macro by writing "1" to this bit. since register value is output as it is (level output), "0" should be set again to release reset. 0 no software reset (initial value) 1 software reset 27 srst1_27 (mbus2axi(draw ) software reset) reset is output to mbus2axi (draw) macro by writing "1" to this bit. since register value is output as it is (level output), "0" should be set again to release reset. 0 no software reset (initial value) 1 software reset 26 srst1_26 (mbus2axi(disp) software reset) reset is output to mbus2axi (disp) macro by writing "1" to this bit. since register value is output as it is (level output), "0" should be set again to release reset. 0 no software reset (initial value) 1 software reset 25 srst1_25 (ahb2axi(cpuro ot) software reset) reset is output to ahb2axi (cpuroot) macro by writing "1" to this bit. since register value is output as it is (level output), "0" should be set again to release reset. 0 no software reset (initial value) 1 software reset 24 srst1_24 (ahb2axi(ahbb us) software reset) reset is output to ahb2axi (ahb bus) macro by writing "1" to this bit. since register value is output as it is (level output), "0" should be set again to release reset. 0 no software reset (initial value) 1 software reset
26-27 MB86R01 lsi product specifications fujitsu semiconductor confidential ccnt bit field no. name function 23 srst1_23 (usb 2.0 function dmac software reset) reset is output to usb 2.0 function dmac macro by writing "1" to this bit. since register value is output as it is (level output), "0" should be set again to release reset. 0 no software reset (initial value) 1 software reset 22 srst1_22 (usb 2.0 function software reset) reset is output to usb 2.0 function m acro by writing "1" to this bit. since register value is output as it is (level output), "0" should be set again to release reset. 0 no software reset (initial value) 1 software reset 21 srst1_21 (usb 1.1 ohci host software reset) reset is output to usb 1.1 ohci host macro by writing "1" to this bit. since register value is output as it is (level output), "0" should be set again to release reset. 0 no software reset (initial value) 1 software reset 20 srst1_20 (usb 2.0 ehci host software reset) reset is output to usb 2.0 ehci host macro by writing "1" to this bit. since register value is output as it is (level output), "0" should be set again to release reset. 0 no software reset (initial value) 1 software reset 19 srst1_19 (usb 2.0 host phycnt software reset) reset is output to usb 2.0 host phycnt macro by writing "1" to this bit. since register value is output as it is (level output), "0" should be set again to release reset. 0 no software reset (initial value) 1 software reset 18 srst1_18 (uart5 software reset) reset is output to uart5 macro by writing "1" to this bit. since register value is output as it is (level output), "0" should be set again to release reset. 0 no software reset (initial value) 1 software reset 17 srst1_17 (uart4 software reset) reset is output to uart4 macro by writing "1" to this bit. since register value is output as it is (level output), "0" should be set again to release reset. 0 no software reset (initial value) 1 software reset 16 srst1_16 (uart3 software reset) reset is output to uart3 macro by writing "1" to this bit. since register value is output as it is (level output), "0" should be set again to release reset. 0 no software reset (initial value) 1 software reset
26-28 MB86R01 lsi product specifications fujitsu semiconductor confidential ccnt bit field no. name function 15 srst1_15 (uart2 software reset) reset is output to uart2 macro by writing "1" to this bit. since register value is output as it is (level output), "0" should be set again to release reset. 0 no software reset (initial value) 1 software reset 14 srst1_14 (pwm_1 software reset) reset is output to pwm_1 macro by writing "1" to this bit. since register value is output as it is (level output), "0" should be set again to release reset. 0 no software reset (initial value) 1 software reset 13 srst1_13 (pwm_0 software reset) reset is output to pwm_0 macro by writing "1" to this bit. since register value is output as it is (level output), "0" should be set again to release reset. 0 no software reset (initial value) 1 software reset 12 srst1_12 (i2c_0 software reset) reset is output to i2c_0 macro by writing "1" to this bit. since register value is output as it is (level output), "0" should be set again to release reset. 0 no software reset (initial value) 1 software reset 11 srst1_11 (i2c_0 software reset) reset is output to i2c_0 macro by writing "1" to this bit. since register value is output as it is (level output), "0" should be set again to release reset. 0 no software reset (initial value) 1 software reset 10 srst1_10 (ide66 software reset) reset is output to ide66 macro by writing "1" to this bit. since register value is output as it is (level output), "0" should be set again to release reset. 0 no software reset (initial value) 1 software reset 9 srst1_9 (spi software reset) reset is output to spi macro by writing "1" to this bit. since register value is output as it is (level output), "0" should be set again to release reset. 0 no software reset (initial value) 1 software reset 8 srst1_8 (i2s_2 software reset) reset is output to i2s_2 macro by writing "1" to this bit. since register value is output as it is (level output), "0" should be set again to release reset. 0 no software reset (initial value) 1 software reset
26-29 MB86R01 lsi product specifications fujitsu semiconductor confidential ccnt bit field no. name function 7 srst1_7 (i2s_1 software reset) reset is output to i2s_1 macro by writing "1" to this bit. since register value is output as it is (level output), "0" should be set again to release reset. 0 no software reset (initial value) 1 software reset 6 srst1_6 (i2s_0 software reset) reset is output to i2s_0 macro by writing "1" to this bit. since register value is output as it is (level output), "0" should be set again to release reset. 0 no software reset (initial value) 1 software reset 5 srst1_5 (mbus2axi(cap)) reset is output to mbus2axi (cap) macro by writing "1" to this bit. since register value is output as it is (level output), "0" should be set again to release reset. 0 no software reset (initial value) 1 software reset 4 srst1_4 (sdmc software reset) reset is output to sdmc macro by writing "1" to this bit. since register value is output as it is (level output), "0" should be set again to release reset. 0 no software reset (initial value) 1 software reset 3 srst1_3 (can1 software reset) reset is output to can1macro by writing "1" to this bit. since register value is output as it is (level output), "0" should be set again to release reset. 0 no software reset (initial value) 1 software reset 2 srst1_2 (can0 software reset) reset is output to can0 macro by writing "1" to this bit. since register value is output as it is (level output), "0" should be set again to release reset. 0 no software reset (initial value) 1 software reset 1 srst1_1 (ddr2 software reset) reset is output to ddr2 controller m acro by writing "1" to this bit. since register value is output as it is (level output), "0" should be set again to release reset. 0 no software reset (initial value) 1 software reset 0 srst1_0 (gdc software reset) reset is output to gdc macro by writing "1" to this bit. since register value is output as it is (level output), "0" should be set again to release reset. 0 no software reset (initial value) 1 software reset
27-1 MB86R01 lsi product specification fujitsu semiconductor confidential external interrupt controller (exirc) 27. external interrupt controller (exirc) this chapter describes function and operatio n of external interrupt controller (exirc.) 27.1. outline exirc is block to control external interrupt as well as external interrupt request input to external pin of int_a[3] ~ int_a [0]. "h" level, "l " level, rising edge, and falling edge are selectable as detected input request level. 27.2. feature exirc has following features: ? operating as bus slave of amba (apb) ? 4 channels of external interrupt control ? 4 input request level selections ? "h" level ? "l" level ? rising edge ? falling edge ? utilization of external interrupt as returning factor from stop mode
27-2 MB86R01 lsi product specification fujitsu semiconductor confidential external interrupt controller (exirc) 27.3. block diagram figure 27-1 shows block diagram of exirc. irc0 (interrupt controller 0) ei_level ei_enable ei_request 0 ei_request 1 ei_request 2 ei_request 3 ei_dout apb bus int_a[0] irq10 int_a[1] irq11 int_a[2] irq12 int_a[3] irq13 exirc (external interrupt controller) figure 27-1 block diagram of exirc table 27-1 shows block function included in exirc. table 27-1 block function included in exirc block function ei_enable enabling external interrupt re quest for interrupt controller (irc0) ei_level setting input request level: "h" level/"l" leve l/rising edge/falling edge ei_request synchronizing and maintaining interrupt request ei_dout generating data for reading 27.4. supply clock apb clock is supplied to exirc. refer to "5. clock reset generator (crg)" for frequency setting and control specification of the clock.
27-3 MB86R01 lsi product specification fujitsu semiconductor confidential external interrupt controller (exirc) 27.5. register this section describes exirc register. 27.5.1. register list table 27-2 shows exirc register list. table 27-2 exirc register list address base offset register abbreviation description fffe_4000 h + 00 h external interrupt enable register eienb en able control of external interrupt request output + 04 h external interrupt request register eireq clear function of external interrupt display and interrupt request + 08 h external interrupt level register eilvl selection of input request level detection of external interrupt
27-4 MB86R01 lsi product specification fujitsu semiconductor confidential external interrupt controller (exirc) description format of register following format is used for descri ption of register?s each bit in " 27.5.2 external interrupt enable register (eie nb)" to " 27.5.4 external interrupt level register (eilvl)". address base address + offset bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r/w initial value bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r/w initial value meaning of item and sign address address (base address + offset address) of the register bit bit number of the register name bit field name of the register r/w attribution of read/write of each bit field ? r0:read value is always "0" ? r1: read value is always "1" ? w0: write value is always "0", and write access of "1" is ignored ? w1: write value is always "1", and write access of "0" is ignored ? r: read ? w: write initial value each bit field?s value after reset ? 0: value is "0" ? 1: value is "1" ? x: value is undefined
27-5 MB86R01 lsi product specification fujitsu semiconductor confidential external interrupt controller (exirc) 27.5.2. external interrupt enable register (eienb) this register is to control maskin g external interrupt request output. address fffe_4000 h + 00 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ? ? ? ? ? ? ? ? ? ? ? ? enb3 enb2 enb1 enb0 r/w r/w r/w r/w r/w r/w r/w r /w r/w r0 r0 r0 r0 r/w r/w r/w r/w initial value x x x x x x x x 0 0 0 0 0 0 0 0 bit field no. name description 31-8 ? unused bit. write access is ignored. read valu e of these bits is undefined. 7-4 ? unused bit. write access is ignored. read valu e of these bits is always "0". 3-0 enb3-0 masking external interr upt request output is controlled. 0 external interrupt request is disabled 1 external interrupt request is enabled. the interrupt request output corresponding to the bit written "1" is perm itted (enb0 controls int_a[0] permission), and the request is output to interrupt controller (irc0.) although the pin corresponding to the bit written "0" maintains in terrupt factor, interrupt is not requested to the controller. these bits are initialized to "0000 b " by reset.
27-6 MB86R01 lsi product specification fujitsu semiconductor confidential external interrupt controller (exirc) 27.5.3. external interrupt request register (eireq) this register is to indicate and clear external interrupt request. address fffe_4000 h + 04 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ? ? ? ? ? ? ? ? ? ? ? ? req3 req2 req1 req0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r0 r0 r0 r0 r/w0 r/w0 r/w0 r/w0 initial value x x x x x x x x 0 0 0 0 0 0 0 0 bit field no. name description 31-8 ? unused bit. write access is ignored. read valu e of these bits is undefined. 7-4 ? unused bit. write access is ignored. read valu e of these bits is always "0". 3-0 req3-0 external interrupt request is indicated and cleared. 0 at reading: there is no external interrupt request at writing: external interrupt request is cleared 1 at reading: there is ex ternal interrupt request at writing: external interrupt request invalid read value of "1" shows external interrupt is requested. these bits correspond to external interrupt channel as follows. ? req0: external interrupt 0 (int_a[0] pin) ? req1: external interrupt 1 (int_a[1] pin) ? req2: external interrupt 2 (int_a[2] pin) ? req3: external interrupt 3 (int_a[3] pin) when "0" is written to these bits, exte rnal interrupt request is cleared. writing "1" is invalid. these bits are initialized to "0000 b " by reset.
27-7 MB86R01 lsi product specification fujitsu semiconductor confidential external interrupt controller (exirc) 27.5.4. external interrupt level register (eilvl) this register is to select input request level detection. address fffe_4000 h + 08 h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ? ? ? ? ? ? ? ? lvl3[1] lvl3[0] lvl2 [1 ] lvl2 [0 ] lvl1 [1 ] lvl1 [0 ] lvl0 [1 ] lvl0 [0 ] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x 0 1 0 1 0 1 0 1 bit field no. name description 31-8 ? unused bit. write access is ignored. read va lue of these bits is undefined. 7-0 lvl3[1:0] - lvl0[1:0] input request level dete ction of external interrupt is selected. 2 bit is allocated to each external interrupt channel. this is initialized to "01 b " by reset. ? lvl0[1:0]: external interrupt 0 (int_a[0] pin) ? lvl1[1:0]: external interrupt 1 (int_a[1] pin) ? lvl2[1:0]: external interrupt 2 (int_a[2] pin) ? lvl3[1:0]: external interrupt 3 (int_a[3] pin) lvl3-0[1] lvl3-0[0] input request level 0 0 "l" level 0 1 "h" level 1 0 rising edge 1 1 falling edge
27-8 MB86R01 lsi product specification fujitsu semiconductor confidential external interrupt controller (exirc) 27.6. operation external interrupt controller issues request signal to interrupt controller (irc0) when input request level of external interrupt is input to corresponding ch annel after setting eienb and eilvl registers. if interrupt from this module is higher than interrupt level set in ilm register and it is highest priority as a result of interrupt prioritization occurred in irq level decision circuit, irq interrupt request is issued to arm core. irc0 (interrupt controller 0) irqyy compare interrupt level ilm irq external interrupt controller from external pins figure 27-2 operation of external interrupt 27.7. operation procedure external interrupt register setting procedure is as followings. 1. disable eienb register related bit 2. set eilvl register related bit 3. clear eireq register related bit 4. enable eienb register related bit eienb register must be disabled to set register in the module; moreover, eireq register needs to be cleared before eienb register is enabled. this op eration is to prevent accident caused by incidental interrupt source during register setting. 27.8. instruction for use this section indicates notice for using external interrupt. notice for returning from stop mode when external interrupt is used to return from stop mode, where clock is stopped, set input request level to "h" since "l" level request may cause malfunction. more over, the edge request is not able to return from the stop mode.
28-1 MB86R01 lsi product specifications sd memory controller (sdmc) fujitsu semiconductor confidential 28. sd memory controller (sdmc) only sd card licensee is disclosed.

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